Epson S1C33210 Manuals

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Epson S1C33210 Technical Manual

Epson S1C33210 Technical Manual (559 pages)

CMOS 32-Bit Single Chip Microcomputer

Brand: Epson | Category: Computer Hardware | Size: 3.75 MB

Table of Contents

Table of Contents
5
Outline

15
- Features
  15
- Block Diagram
  17
- Pin Description
  18
  - Pin Layout Diagram (Plastic Package
    18
  - Pin Functions
    19
Power Supply

25
- Power Supply Pins
  25
- Operating Voltage
  25
  - DD Ss
    25
- Power Supply for Analog Circuits (AV DD
  26
Internal Memory

27
- ROM and Boot Address
  27
- Ram
  27
Peripheral Circuits

28
- List of Peripheral Circuits
  28
- I/O Memory Map
  29
Power-Down Control

76
Basic External Wiring Diagram

79
Precautions on Mounting

80
Electrical Characteristics

82
- Absolute Maximum Rating
  82
- Recommended Operating Conditions
  83
- DC Characteristics
  84
- Current Consumption
  85
- A/D Converter Characteristics
  86
- AC Characteristics
  88
- Oscillation Characteristics
  99
- PLL Characteristics
  100
Package

101
- Plastic Package
  101
Pad Layout

102
- Pad Layout Diagram
  102
- Pad Coordinate
  103
Appendix A <Reference> External Device Interface Timings

106
- DRAM (70Ns
  107
- DRAM (60Ns
  110
- ROM and Burst ROM
  114
- SRAM (55Ns
  116
- SRAM (70Ns
  118
- 8255A
  120
Appendix B Pin Characteristics

124
Ioutline

127
Introduction

129
Block Diagram

131
List of Pins

133
- List of External I/O Pins
  133
- Core Block
  
  139
Introduction

141
Cpu and Operating Mode

143
- Cpu
  143
- Standby Mode
  144
  - HALT Mode
    144
  - SLEEP Mode
    144
  - Notes on Standby Mode
    145
  - Test Mode
    145
  - Debug Mode
    145
  - Trap Table
    146
Initial Reset

149
- Pins for Initial Reset
  149
- Cold Start and Hot Start
  149
- Power-On Reset
  150
- Reset Pulse
  150
- Boot Address
  151
- Notes Related to Initial Reset
  151
Bcu (Bus Control Unit)

153
- Pin Assignment for External System Interface
  153
  - I/O Pin List
    153
  - Combination of System Bus Control Signals
    155
  - Memory Area
    156
    
    Memory Map
    156
    
    External Memory Map and Chip Enable
    157
    
    Using Internal Memory on External Memory Area
    159
    
    Exclusive Signals for Areas
    159
    
    Area 10
    160
    
    Area 3
    160
  - Setting External Bus Conditions
    161
    
    Setting Device Type and Size
    161
    
    Setting SRAM Timing Conditions
    162
    
    Setting Timing Conditions of Burst ROM
    163
  - Bus Operation
    164
    
    Data Arrangement in Memory
    164
    
    Bus Operation of External Memory
    164
  - Bus Clock
    168
  - Bus Speed Mode
    169
  - Bus Clock Output
    169
- Bus Cycles in External System Interface
  170
  - SRAM Read Cycles
    170
  - Bus Timing
    171
  - SRAM Write Cycles
    172
  - Burst ROM Read Cycles
    174
- DRAM Direct Interface
  175
  - Outline of DRAM Interface
    175
  - DRAM Setting Conditions
    176
  - DRAM Read/Write Cycles
    179
  - DRAM Refresh Cycles
    182
- Releasing External Bus
  183
- Power-Down Control by External Device
  184
- I/O Memory of BCU
  185
ITC (Interrupt Controller)

199
- Outline of Interrupt Functions
  199
  - Maskable Interrupts
    199
  - Interrupt Factors and Intelligent DMA
    201
  - Nonmaskable Interrupt (NMI)
    201
  - Interrupt Processing by the CPU
    201
  - Clearing Standby Mode by Interrupts
    201
- Trap Table
  202
- Control of Maskable Interrupts
  203
- IDMA Invocation
  207
- HSDMA Invocation
  209
- I/O Memory of Interrupt Controller
  210
- Programming Notes
  223
CLG (Clock Generator)

225
- Configuration of Clock Generator
  225
- I/O Pins of Clock Generator
  226
- High-Speed (OSC3) Oscillation Circuit
  226
- Pll
  227
- Controlling Oscillation
  227
- Setting and Switching over the CPU Operating Clock
  228
- Power-Control Register Protection Flag
  229
- Operation in Standby Mode
  229
- I/O Memory of Clock Generator
  230
- Programming Notes
  233
DBG (Debug Unit)

235
- Debug Circuit
  235
- I/O Pins of Debug Circuit
  235
- Peripheral Block
  
  237
Introduction

239
Prescaler

241
- Configuration of Prescaler
  241
- Source Clock
  241
- Selecting Division Ratio and Output Control for Prescaler
  242
- Source Clock Output to 8-Bit Programmable Timer
  242
- I/O Memory of Prescaler
  243
- Programming Notes
  247
8-Bit Programmable Timers

249
16-Bit Programmable Timers

267
Watchdog Timer

293
- Configuration of Watchdog Timer
  293
- Control of Watchdog Timer
  293
- Operation in Standby Modes
  294
- I/O Memory of Watchdog Timer
  295
- Programming Notes
  295
Low-Speed (Osc1) Oscillation Circuit

297
Clock Timer

305
- Configuration of Clock Timer
  305
- Control and Operation of the Clock Timer
  306
- Interrupt Function
  308
- Examples of Use of Clock Timer
  310
- I/O Memory of Clock Timer
  311
- Programming Notes
  316
Serial Interface

317
- Configuration of Serial Interfaces
  317
  - Features of Serial Interfaces
    317
- I/O Pins of Serial Interface
  318
  - Setting Transfer Mode
    319
- Clock-Synchronized Interface
  320
- Asynchronous Interface
  328
- Irda Interface
  337
  - Outline of Irda Interface
    337
  - Setting Irda Interface
    337
  - Control and Operation of Irda Interface
    339
- Serial Interface Interrupts and DMA
  340
- I/O Memory of Serial Interface
  344
- Programming Notes
  362
Input/Output Ports

363
- Input Ports (K Ports)
  363
  - Structure of Input Port
    363
  - Input-Port Pins
    364
  - Notes on Use
    364
  - I/O Memory of Input Ports
    365
- I/O Ports (P Ports)
  366
  - Structure of I/O Port
    366
  - I/O Port Pins
    366
  - I/O Control Register and I/O Modes
    367
  - I/O Memory of I/O Ports
    368
- Input Interrupt
  373
  - Port Input Interrupt
    373
  - Key Input Interrupt
    375
  - Control Registers of the Interrupt Controller
    377
  - I/O Memory for Input Interrupts
    379
  - Programming Notes
    385
Mobile Access Interfaces

387
- Configuration of Mobile Access Interfaces
  387
  - I/O Pins for Mobile Access Interfaces
    388
  - Basic Settings for Mobile Access Interfaces
    390
- UART Communications Mode
  393
  - Overview
    393
- PDC Communications Mode
  394
  - Overview
    394
  - Output Port Control
    395
  - PDC Communications Control and Operation
    396
- PHS Communications Mode
  397
  - PHS Communications Control and Operation
    399
- HDLC Communications Mode
  400
  - Overview
    400
  - HDLC Communications Control and Operation
    401
- Mobile Access Interface Interrupts
  404
  - Overview
    404
  - Mobile Access Interface Interrupt Outputs
    406
- I/O Memory for Mobile Access Interfaces
  407
- Important Notes on Debugging
  428
Analog Block

429
Introduction

431
A/D Converter

433
- Features and Structure of A/D Converter
  433
- I/O Pins of A/D Converter
  434
- Setting A/D Converter
  435
- Control and Operation of A/D Conversion
  437
- A/D Converter Interrupt and DMA
  439
- I/O Memory of A/D Converter
  441
- Programming Notes
  447
Dma Block

449
Introduction

451
Hsdma (High-Speed Dma)

453
- Functional Outline of HSDMA
  453
- I/O Pins of HSDMA
  454
- Programming Control Information
  455
  - Setting the Registers in Dual-Address Mode
    455
  - Setting the Registers in Single-Address Mode
    458
- Enabling/Disabling DMA Transfer
  459
- Trigger Factor
  460
- Operation of HSDMA
  461
  - Operation in Dual-Address Mode
    461
  - Operation in Single-Address Mode
    464
  - Timing Chart
    465
- Interrupt Function of HSDMA
  467
- I/O Memory of HSDMA
  469
- Programming Notes
  488
IDMA (Intelligent DMA)

489
- Functional Outline of IDMA
  489
- Programming Control Information
  489
- IDMA Invocation
  493
- Operation of IDMA
  496
- Linking
  500
- Interrupt Function of Intelligent DMA
  501
- I/O Memory of Intelligent DMA
  502
- Programming Notes
  505
Appendix I/O Map

507

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