Timing Chart - Epson S1C33210 Technical Manual

Timing Chart

Dual-address mode
(1) SRAM
Example: When 2 (RD)/1 (WR) wait cycles are inserted
BCLK
A[23:0]
#CE(src)
#CE(dst)
#RD
#WRH/#WRL
#DMAEND
(2) DRAM
Example: Page mode, RAS: 1 cycle; CAS: 2 cycles; Precharge: 1 cycle
BCLK
ROW
A[11:0]
#RASx
#HCAS/
#LCAS
#RD
#WR
#DMAEND
S1C33210 FUNCTION PART
Read cycle
source address
Figure 2.6 #DMAEND Signal Output Timing (SRAM)
Read cycle
COL #1 COL #2
Figure 2.7 #DMAEND Signal Output Timing (DRAM)
V DMA BLOCK: HSDMA (High-Speed DMA)
destination address
ROW COL #1
EPSON
Write cycle
Write cycle
COL #2
B-V-2-13