Bus Clock - Epson S1C33210 Technical Manual

II CORE BLOCK: BCU (Bus Control Unit)
Little-endian
Destination (general-purpose register)
31
Sign or Zero extension
Big-endian
Destination (general-purpose register)
31
Sign or Zero extension

Bus Clock

The bus clock is generated by the BCU using the CPU system clock output from the clock generator.
Figure 4.17 shows the clock system.
High-speed (OSC3)
OSC3_CLK
oscillation circuit
PLL_CLK
PLL
Low-speed (OSC1)
oscillation circuit
OSC3_CLK (PLL: off)
PLL_CLK (PLL: x2 mode)
PLL_CLK (PLL: x4 mode)
CPU_CLK (CLKDT = 1/1)
CPU_CLK (CLKDT = 1/2)
CPU_CLK (CLKDT = 1/4)
CPU_CLK (CLKDT = 1/8)
BCU_CLK(#X2SPD=H, x1 speed mode)
BCU_CLK(#X2SPD=L, x2 speed mode)
B-II-4-16
Byte 0
1
8
A[1:0]=
Source (8-bit device)
Byte 0
1
8
A[1:0]=
Source (8-bit device)
Figure 4.16 Byte Data Reading from an 8-bit Device
PLLS[1:0] pins
CLKDT[1:0]
1/2-1/8
A
A
CPU_CLK
1 1
1 1
Figure 4.17 Clock System
0
No.
A1 A0 #WRH
1
X
0
0
No.
A1 A0 #WRH
1
1
0
#X2SPD pin
CLG
CLKCHG
BCU
CPU_CLK
1/1 or 1/2
(when the CPU system clock source is OSC3)
2 1 2
2 1
1 Access to the internal RAM
2 Access to the external memory
EPSON
Bus operation
Data bus
#WRL 15
Ignored Byte 0
1
(X: Not connected/Unused)
Bus operation
Data bus
#WRL 15
Byte 0 Ignored
1
To CPU
Bus clock
BCLKSEL[1:0]
BCU_CLK
2
S1C33210 FUNCTION PART
0
0
BCLK pin