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Epson S1C17704 Technical Manual

Cmos 16-bit single chip microcomputer
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CMOS 16-BIT SINGLE CHIP MICROCOMPUTER
S1C17704
TECHNICAL MANUAL

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Summary of Contents for Epson S1C17704

  • Page 1 CMOS 16-BIT SINGLE CHIP MICROCOMPUTER S1C17704 TECHNICAL MANUAL...
  • Page 2 Seiko Epson. Seiko Epson reserves the right to make changes to this material without notice. Seiko Epson does not assume any liability of any kind arising out of any inaccuracies contained in this material or due to its application or use in any product or circuit and, further, there is no representation that this material is applicable to products requiring high level reliability, such as, medical products.
  • Page 3 S1C17704 Technical Manual Revision History Code No. Page Chapter/Section Contents 411511901 1.1 Features Descriptions modified. Shipping form Part number for plastic package modified. Part number for package modified. Descriptions added. • VFBGA10H-144 package (10 mm 10 mm 1.0 mm, ball pitch: 0.8 mm) 1.3.1 Pin Arrangement...
  • Page 4 Configuration of product number Devices 17xxx 00E1 Packing specifications 00 : Besides tape & reel 0A : TCP BL 2 directions 0B : Tape & reel BACK 0C : TCP BR 2 directions 0D : TCP BT 2 directions 0E : TCP BD 2 directions 0F : Tape &...

  • Page 5: Table Of Contents

    4.4 Heavy Load Protection Function ..................4-5 4.5 Details of Control Registers .....................4-6 0x5120: V Control Register (VD1_CTL) ................. 4-7 0x50a3: LCD Voltage Regulator Control Register (LCD_VREG) ..........4-8 0x50a4: LCD Power Voltage Booster Control Register (LCD_PWR) ........4-9 4.6 Precautions ........................4-10 EPSON S1C17704 TECHNICAL MANUAL...
  • Page 6 0x5061: Oscillation Control Register (OSC_CTL) ..............7-13 0x5062: Noise Filter Enable Register (OSC_NFEN) ..............7-14 0x5063: LCD Clock Setup Register (OSC_LCLK) ..............7-15 0x5064: FOUT Control Register (OSC_FOUT) ................ 7-16 0x5065: T8OSC1 Clock Control Register (OSC_T8OSC1) ............7-17 7.10 Precautions ........................7-18 EPSON S1C17704 TECHNICAL MANUAL...
  • Page 7 11.3 Count Mode ........................11-5 11.4 16-bit Timer Reload Register and Underflow Period .............11-6 11.5 Resetting the 16-bit Timer .....................11-7 11.6 16-bit Timer Run/Stop Control ..................11-8 11.7 16-bit Timer Output Signal .....................11-9 11.8 16-bit Timer Interrupt ....................11-10 EPSON S1C17704 TECHNICAL MANUAL...
  • Page 8 14.6 8-bit OSC1 Timer Run/Stop Control ................14-6 14.7 8-bit OSC1 Timer Interrupt ....................14-7 14.8 Details of Control Registers ..................14-9 0x50c0: 8-bit OSC1 Timer Control Register (T8OSC1_CTL) ..........14-10 0x50c1: 8-bit OSC1 Timer Counter Data Register (T8OSC1_CNT) ........14-11 EPSON S1C17704 TECHNICAL MANUAL...
  • Page 9 18 UART ...........................18-1 18.1 Outline of the UART ......................18-1 18.2 UART Pins ........................18-2 18.3 Transfer Clock .......................18-3 18.4 Setting Transfer Data Conditions ..................18-4 18.5 Data Transmit/Receive Control ..................18-5 18.6 Receive Errors ......................18-8 18.7 UART Interrupt ......................18-9 EPSON S1C17704 TECHNICAL MANUAL...
  • Page 10 0x5343: REMC L Carrier Length Setup Register (REMC_CARL) ........... 21-14 0x5344: REMC Status Register (REMC_ST) ................21-15 0x5345: REMC Length Counter Register (REMC_LCNT) ............21-16 0x5346: REMC Interrupt Mask Register (REMC_IMSK) ............21-17 0x5347: REMC Interrupt Flag Register (REMC_IFLG) ............21-18 21.8 Precaution ........................21-19 EPSON S1C17704 TECHNICAL MANUAL...
  • Page 11 0xffff90: Debug RAM Base Register (DBRAM) ................ 24-5 25 Basic External Wiring Diagram ................25-1 26 Electrical Characteristics ..................26-1 26.1 Absolute Maximum Rating ....................26-1 26.2 Recommended Operating Conditions ................26-1 26.3 DC Characteristics ......................26-2 26.4 Analog Circuit Characteristics ..................26-3 26.5 Current Consumption ....................26-5 EPSON S1C17704 TECHNICAL MANUAL...
  • Page 12 Appendix C Power Saving ................... AP-30 C.1 Power Saving by Clock Control ................... AP-30 C.2 Power Saving by Power Supply Control ............... AP-33 Appendix D Precautions on Mounting ............... AP-34 Appendix E Initialize Routine ..................AP-38 EPSON viii S1C17704 TECHNICAL MANUAL...

  • Page 13: Overview

    The S1C17704 is a 16-bit MCU that features high-speed operation, low power consumption, small size, large address space, and on-chip ICE. The S1C17704 consists of an S1C17 CPU Core, a 64K-byte Flash memory, a 4K-byte RAM, serial interface modules (UART that supports high bit rate and IrDA 1.0, SPI and I C) for connecting various sensor modules, 8-bit timers, 16-bit timers, a PWM &...

  • Page 14: Features

    1 OVERVIEW 1.1 Features The main functions and features of the S1C17704 are outlined below. • Seiko Epson original 16-bit RISC CPU core S1C17 Main (OSC3) oscillator • Crystal/ceramic oscillator 8.2 MHz (max.) • CR oscillator 2.2 MHz (max.) Sub (OSC1) oscillator •...

  • Page 15: Block Diagram

    (P16, P07, P06) SIN, SOUT, SCLK PWM & capture UART EXCL3(P27), (P23–25) timer TOUT(P26) SDI, SDO, SPICLK Remote controller REMI(P04), (P20–22) REMO(P05) I/O port/ SDA, SCL P00–07, P10–17, I/O MUX (P14–15) P20–27, P30–33 Figure 1.2.1 Block Diagram EPSON S1C17704 TECHNICAL MANUAL...

  • Page 16: Pins

    COM19/SEG68 SEG2 COM20/SEG67 SEG3 COM21/SEG66 SEG4 COM22/SEG65 SEG5 COM23/SEG64 SEG6 COM24/SEG63 SEG7 COM25/SEG62 SEG8 COM26/SEG61 SEG9 COM27/SEG60 SEG10 COM28/SEG59 SEG11 COM29/SEG58 SEG12 COM30/SEG57 SEG13 COM31/SEG56 SEG14 SEG55 SEG15 SEG54 SEG16 SEG53 Figure 1.3.1.1 Pin Arrangement (TQFP24-144-pin) EPSON S1C17704 TECHNICAL MANUAL...
  • Page 17 N.C. COM31 COM22 SEG56 SEG65 N.C. N.C. N.C. N.C. N.C. Figure 1.3.1.2 Pin Arrangement （PFBGA6U96） Note: The LCD driver cannot be used with the PFBGA6U96 package. It should be used with COM31 to 16 left open. EPSON S1C17704 TECHNICAL MANUAL...
  • Page 18 SEG60 SEG64 SEG67 SEG70 SEG52 SEG51 SEG54 COM30 COM26 COM22 COM19 COM16 OSC4 SEG57 SEG61 SEG65 SEG68 SEG71 SEG53 SEG55 COM29 COM25 COM21 COM18 OSC3 SEG58 SEG62 SEG66 SEG69 N.C. N.C. Figure 1.3.1.3 Pin Arrangement （VFBGA7H-161） EPSON S1C17704 TECHNICAL MANUAL...
  • Page 19 COM27 COM22 COM18 OSC4 SEG56 SEG60 SEG65 SEG69 SEG50 SEG51 SEG54 COM30 COM26 COM21 COM16 OSC3 SEG57 SEG61 SEG66 SEG71 SEG52 SEG53 SEG55 COM29 COM25 COM20 COM17 SEG58 SEG62 SEG67 SEG70 Figure 1.3.1.4 Pin Arrangement （VFBGA10H-144） EPSON S1C17704 TECHNICAL MANUAL...

  • Page 20: Pin Description

    I/O I （Pull-UP）Input/output port pin*/SPI data output pin P20/SDI I/O I （Pull-UP）Input/output port pin*/SPI data input pin P17/#SPISS I/O I （Pull-UP）Input/output port pin (with interrupt)*/SPI slave select input pin P16/EXCL0 I/O I （Pull-UP）Input/output port pin (with interrupt)*/T16 Ch.0 external clock input pin EPSON S1C17704 TECHNICAL MANUAL...
  • Page 21 ∗13: SEG0 to 16 （ VFBGA10） C6, D6, E6, A5, B5, C5, A4, D5, E5, C4, B4, A3, D4, B3, A2, C3, B2 Note: Bold text (for pins) and an asterisk (for functions) indicate default settings. EPSON S1C17704 TECHNICAL MANUAL...
  • Page 22 1 OVERVIEW THIS PAGE IS BLANK. EPSON 1-10 S1C17704 TECHNICAL MANUAL...

  • Page 23: Cpu

    2 CPU 2 CPU The S1C17704 contains the S1C17 Core as its core processor. The S1C17 Core is a Seiko Epson original 16-bit RISC-type processor. It features low power consumption, high-speed operation, large address space, main instructions executable in one clock cycle, and a small sized design.

  • Page 24: Cpu Registers

    2 CPU 2.2 CPU Registers The S1C17 Core contains eight general-purpose registers and three special registers. Special registers General-purpose registers bit 23 bit 0 bit 23 bit 0 IL[2:0] Figure 2.2.1 Registers EPSON S1C17704 TECHNICAL MANUAL...

  • Page 25: Instruction Set

    General-purpose register (32 bits, zero-extended) → memory (∗1) [imm7],%rs SP → general-purpose register %rd,%sp PC → general-purpose register %rd,%pc Stack (32 bits) → general-purpose register (∗1) %rd,[%sp] %rd,[%sp]+ Stack pointer post-increment, post-decrement, and pre-decrement functions %rd,[%sp]- can be used. %rd,-[%sp] EPSON S1C17704 TECHNICAL MANUAL...
  • Page 26 Exclusive OR of general-purpose register and immediate %rd,%rs Logical inversion between general-purpose registers (1's complement) not/c Supports conditional execution (/c: executed if C = 1, /nc: executed if C = 0). not/nc %rd,sign7 Logical inversion of general-purpose register and immediate (1's complement) EPSON S1C17704 TECHNICAL MANUAL...
  • Page 27 32-bit data in which the eight high-order bits are set to 0 is written to the memory. During reading from a memory, the eight high-order bits of the read data are ignored. ∗2 The S1C17704 does not include a coprocessor. Therefore, the coprocessor instructions are not available. EPSON...
  • Page 28 Memory addressed by general-purpose register with address pre-decremented Stack pointer [%sp],[%sp+imm7] Stack [%sp]+ Stack with address post-incremented [%sp]- Stack with address post-decremented -[%sp] Stack with address pre-decremented imm3,imm5,imm7,imm13 Unsigned immediate (numerals indicating bit length) sign7,sign10 Signed immediate (numerals indicating bit length) EPSON S1C17704 TECHNICAL MANUAL...

  • Page 29: Vector Table

    The vector table is located at address 0x8000 in the S1C17704. The vector table base address can be read out from TTBR (Vector Table Base Register) located at address 0xffff80.

  • Page 30: Processor Information

    2 CPU 2.5 Processor Information The S1C17704 has the Processor ID Register (0xffff84) shown below that allow the application software to identify CPU core type. 0xffff84: Processor ID Register (IDIR) Register name Address Name Function Setting Init. R/W Remarks Processor ID 0xffff84 D7–0 IDIR[7:0]...

  • Page 31: Memory Map, Bus Control

    3 MEMORY MAP, BUS CONTROL 3 Memory Map, Bus Control Figure 3.1 shows the S1C17704 memory map. Peripheral function (Device size) 0xff ffff Reserved for core I/O area reserved – 0x5360–0x5fff (1K bytes, 1 cycle) Remote controller (8 bits) 0x5340–0x535f...

  • Page 32: Bus Cycle

    This prolongs the instruction fetch cycle for the number of data area access cycles. • When the S1C17704 executes the instruction stored in the Flash area and accesses data in the Flash area, display RAM area or internal peripheral area 2 (0x5000–) •...

  • Page 33: Flash Area

    1 to 5 cycles. 3.2.2 Flash Programming The S1C17704 supports on-board programming of the Flash memory, it makes it possible to program the Flash memory with the application programs/data by using the debugger through the ICD Mini. Furthermore, the S1C17704 supports self-programming by the application program stored in the Flash memory.

  • Page 34: Access Control For The Flash Controller

    3 MEMORY MAP, BUS CONTROL 3.2.4 Access Control for the Flash Controller The S1C17704 on-chip Flash memory is accessed via the exclusive Flash controller. A MISC register is used to set the access condition for the Flash controller. Setting number of read access cycles for the Flash controller In order to read data from the Flash memory properly, set the appropriate number of read access cycles according to the CCLK frequency using the FLCYC[2:0] bits (D[2:0]/MISC_FL register).

  • Page 35: Internal Ram Area

    3.3.1 Internal RAM The S1C17704 contains a RAM in the 4K-byte area from address 0x0 to address 0xfff. The RAM is accessed in one cycle for both reading and writing and allows high-speed execution of the instruction codes copied into it as well as storing variables and other data.

  • Page 36: Display Ram Area

    3.4.2 Access Control for the SRAM Controller The S1C17704 display RAM is accessed via the exclusive SRAM controller. A MISC register is used to set the access condition for the SRAM controller. Setting number of access cycles for the SRAM controller In order to read/write data from/to the display RAM properly, set the appropriate number of access cycles according to the CCLK frequency using the SRCYC[1:0] bits (D[1:0]/ MISC_SR register).

  • Page 37: Internal Peripheral Area

    • Power supply circuit (VD1, 8-bit device) • I/O port & port MUX (P, 8-bit device) • PWM & capture timer (T16E, 16-bit device) • MISC register (MISC, 8-bit device) • Remote controller (REMC, 8-bit device) EPSON S1C17704 TECHNICAL MANUAL...

  • Page 38: I/O Map

    0x4342 I2C_CTL C Control Register Controls the I C operation and indicates transfer status. 0x4344 I2C_DAT C Data Register Transmit/receive data 0x4346 I2C_ICTL C Interrupt Control Register Controls the I C interrupt. 0x4348–0x435f – – Reserved EPSON S1C17704 TECHNICAL MANUAL...
  • Page 39 P1 Port Pull-up Control Register Controls the P1 port pull-up resistor. 0x5214 P1_SM P1 Port Schmitt Trigger Control Register Controls the P1 port Schmitt trigger input. 0x5215 P1_IMSK P1 Port Interrupt Mask Register Enables/disables the P1 port interrupt. EPSON S1C17704 TECHNICAL MANUAL...
  • Page 40 Indicates/resets interrupt occurrence status. 0x5348–0x535f – – Reserved Note: Do not access the “Reserved” address in the table above and unused areas in the peripheral area that are not described in the table from the application program. EPSON 3-10 S1C17704 TECHNICAL MANUAL...

  • Page 41: S1C17 Core I/O Area

    0xffff90 DBRAM Debug RAM Base Register Indicates the debug RAM base address. See Section 2.4, “Vector Table,” and Section 2.5, “Processor Information,” for TTBR and IDIR, respectively. For DBRAM, see Chapter 24, “On-chip Debugger (DBG).” EPSON S1C17704 TECHNICAL MANUAL 3-11...
  • Page 42 3 MEMORY MAP, BUS CONTROL THIS PAGE IS BLANK. EPSON 3-12 S1C17704 TECHNICAL MANUAL...

  • Page 43: Power Supply

    4 POWER SUPPLY 4 Power Supply 4.1 Power Supply Voltage The operating voltage range of the S1C17704 is as follows: For normal operation: 1.8 V to 3.6 V For Flash programming: 2.7 V to 3.6 V Supply a voltage within the range to the V pins with the V pins as the GND level.

  • Page 44: Internal Power Supply Circuit

    4 POWER SUPPLY 4.2 Internal Power Supply Circuit The S1C17704 has a built-in power supply circuit shown in Figure 4.2.1 to generate all the power voltages required for the internal circuits. The power supply module consists of three circuits. Table 4.2.1 Power Supply Circuit...

  • Page 45: Controlling The Power Supply Circuit

    Switching the operating mode The S1C17704 has two kinds of operating modes. 1. Normal operation mode This mode is provided for running the application program.
  • Page 46 1.8 to 2.7 V – (use prohibited) program 2.7 to 3.6 V Used Other than 0x0 2.7 to 3.6 V Not used For the DSPC[1:0] settings, see “0x50a0: LCD Display Control Register (LCD_DCTL)” in Section 22.8. EPSON S1C17704 TECHNICAL MANUAL...

  • Page 47: Heavy Load Protection Function

    ∗ LHVLD: LCD Heavy Load Protection Mode Bit in the LCD Voltage Regulator Control (LCD_VREG) Register (D4/0x50a3) Note: Current consumption increases in heavy load protection mode, therefore do not set heavy load protection mode with software if unnecessary. EPSON S1C17704 TECHNICAL MANUAL...

  • Page 48: Details Of Control Registers

    Controls the LCD voltage booster. The following describes each power control register. These are all 8-bit registers. Note: When setting the registers, be sure to write a 0, and not a 1, for all “reserved bits.” EPSON S1C17704 TECHNICAL MANUAL...

  • Page 49: 0X5120: V D1 Control Register (Vd1_Ctl)

    = 1.8 V, default setting). It should be set to 1 before erasing/ programming the Flash memory. Note: When the operating mode is switched, the internal operating voltage requires 5 ms (max.) to stabilize. Flash memory programming should be started after the stabilization time has elapsed. EPSON S1C17704 TECHNICAL MANUAL...

  • Page 50: 0X50A3: Lcd Voltage Regulator Control Register (Lcd_Vreg)

    The LCD system voltage regulator enters heavy load protection mode by writing 1 to LHVLD and it ensures stable V –V outputs. Use the heavy load protection function when the LCD display has inconsistencies in density. Current consumption increases in heavy load protection mode, therefore do not set if unnecessary. D[3:0] Reserved EPSON S1C17704 TECHNICAL MANUAL...

  • Page 51: X50A4: Lcd Power Voltage Booster Control Register (Lcd_Pwr)

    Note: When the power voltage booster is turned on, the V output voltage requires about 1 ms to stabilize. Do not switch the power source for the LCD system voltage regulator to V until the stabilization time has elapsed. EPSON S1C17704 TECHNICAL MANUAL...

  • Page 52: Precautions

    LCD system voltage regulator to V until the stabilization time has elapsed. • Current consumption increases in heavy load protection mode, therefore do not set heavy load protection mode with software if unnecessary. EPSON 4-10 S1C17704 TECHNICAL MANUAL...

  • Page 53: Initial Reset

    By setting the #RESET pin to low level, the S1C17704 enters initial reset state. In order to initialize the S1C17704 for sure, the #RESET pin must be held at low for more than the prescribed time (see Section 26.6, “AC Characteristics”) after the power supply voltage is supplied.

  • Page 54: P0 Port Key-Entry Reset

    5.1.3 Resetting by the Watchdog Timer The S1C17704 has a built-in watchdog timer to detect runaway of the CPU. The watchdog timer overflows if it is not reset with software (due to CPU runaway) in four-second cycles. The overflow signal can generate either NMI or reset.

  • Page 55: Initial Reset Sequence

    SLEEP mode is canceled may be longer than that indicated in the figure below. OSC3 clock #RESET Reset canceled Internal reset Internal reset canceled Internal data request Internal data address Boot vector Oscillation stabilization Booting waiting time Figure 5.2.1 Operation Sequence Following Cancellation of Initial Reset EPSON S1C17704 TECHNICAL MANUAL...

  • Page 56: Initial Settings After An Initial Reset

    The internal peripheral modules are initialized to the default values (except some undefined registers). Change the settings with software if necessary. For the default values set at initial reset, see the list of I/O registers in Appendix or descriptions for each peripheral module. EPSON S1C17704 TECHNICAL MANUAL...

  • Page 57: Interrupt Controller (Itc)

    6 INTERRUPT CONTROLLER (ITC) 6 Interrupt Controller (ITC) 6.1 Configuration of ITC The S1C17704 provides 16 interrupt systems listed below. 1. P00–P07 input interrupt (8 types) 2. P10–P17 input interrupt (8 types) 3. Stopwatch timer interrupt (3 types) 4. Clock timer interrupt (4 types) 5.

  • Page 58: Vector Table

    S1C17 Core to execute the handler when an interrupt occurs. The vector table is located at address 0x8000 in the S1C17704. The vector table base address can be read out from TTBR (Vector Table Base Register) located at address 0xffff80.

  • Page 59: Control Of Maskable Interrupts

    1. Those interrupt flags are reset when the interrupt signal is negated by the interrupt source. For the occurrence conditions of the causes of interrupt and the module specific settings, refer to the section that describes the interrupt source module. EPSON S1C17704 TECHNICAL MANUAL...

  • Page 60: Enabling/Disabling Interrupts

    S1C17 Core must be set to 1 to actually generate an interrupt. If the IE bit has been set to 0, the S1C17 Core cannot accept a maskable interrupt request. In this case, the interrupt request sent from the ITC is held and it will be accepted after the IE bit is set to 1. EPSON S1C17704 TECHNICAL MANUAL...

  • Page 61: Processing When Multiple Interrupts Occur

    If another cause of interrupt of higher priority occurs during outputting an interrupt request signal, the ITC changes the vector number and interrupt level to that of the new cause of interrupt. The first interrupt request is left pending. EPSON S1C17704 TECHNICAL MANUAL...

  • Page 62: Interrupt Trigger Mode

    The software writes 1 to the interrupt flag to reset. Figure 6.3.5.1 Pulse Trigger Mode Note: The following S1C17704 interrupts use pulse trigger mode. When an interrupt occurs, reset (write 1 to) the interrupt flag IIFTx in the interrupt handler routine.
  • Page 63 The interrupt source negates the interrupt signal. Figure 6.3.5.2 Level Trigger Mode Note: The following S1C17704 interrupts use level trigger mode. The interrupt handler routine must reset (write 1 to) the interrupt flag provided in the peripheral module, not EIFTx.

  • Page 64: Interrupt Processing By The S1C17 Core

    When the interrupt handler routine is terminated by the reti instruction, the PSR is restored to its previous status before the interrupt has occurred. The program restarts processing after branching to the instruction next to the one that was being executed when the interrupt occurred. EPSON S1C17704 TECHNICAL MANUAL...

  • Page 65: Nmi

    6 INTERRUPT CONTROLLER (ITC) 6.4 NMI In the S1C17704, the watchdog timer generates a non-maskable interrupt (NMI). The vector number of NMI is 2, with the vector address set to the vector table's starting address + 8 bytes. This interrupt is prioritized over other interrupts and is unconditionally accepted by the S1C17 Core.

  • Page 66: Software Interrupts

    The operand imm5 specifies a vector number (0–31) in the vector table. In addition to this, the intl instruction has the operand imm3 to specify the interrupt level (0–7) to be set to the IL field in the PSR. The processor performs the same interrupt handling as that of the hardware interrupt. EPSON 6-10 S1C17704 TECHNICAL MANUAL...

  • Page 67: Clearing Halt And Sleep Modes By Interrupt Causes

    The program execution sequence (whether it branches to the interrupt handler routine) after the CPU starts up depends on the clock status in HALT/SLEEP mode. See “C.1 Power Saving by Clock Control” in Appendix C for details. EPSON S1C17704 TECHNICAL MANUAL 6-11...

  • Page 68: Details Of Control Registers

    Sets the SPI and I C interrupt levels. The following describes each ITC register. These are all 16-bit registers. Note: When setting the registers, be sure to write a 0, and not a 1, for all “reserved bits.” EPSON 6-12 S1C17704 TECHNICAL MANUAL...

  • Page 69: 0X4300: Interrupt Flag Register (Itc_Iflg)

    UART interrupt: transmit buffer empty/receive buffer full/receive error IIFT5 (D13) Remote controller interrupt: data length counter underflow/input rising edge/ input falling edge IIFT6 (D14) SPI interrupt: transmit buffer empty/receive buffer full IIFT7 (D15) C interrupt: transmit buffer empty/receive buffer full EPSON S1C17704 TECHNICAL MANUAL 6-13...
  • Page 70 The interrupt flag of the level triggered interrupt must be reset using the control register in the peripheral module. EPSON 6-14 S1C17704 TECHNICAL MANUAL...

  • Page 71: 0X4302: Interrupt Enable Register (Itc_En)

    UART interrupt: transmit buffer empty/receive buffer full/receive error IIEN5 (D13) Remote controller interrupt: data length counter underflow/input rising edge/ input falling edge IIEN6 (D14) SPI interrupt: transmit buffer empty/receive buffer full IIEN7 (D15) C interrupt: transmit buffer empty/receive buffer full EPSON S1C17704 TECHNICAL MANUAL 6-15...

  • Page 72: 0X4304: Itc Control Register (Itc_Ctl)

    0 Disable D[15:1] Reserved ITEN: ITC Enable Bit Enables the ITC to control interrupt generation. 1 (R/W): Enable 0 (R/W): Disable (default) Before the ITC can be used, this bit must be set to 1. EPSON 6-16 S1C17704 TECHNICAL MANUAL...

  • Page 73: 0X4306: External Interrupt Level Setup Register 0 (Itc_Elv0)

    0x0 R/W D[15:13] Reserved EITG1: P1 Port Interrupt Trigger Mode Select Bit Selects the trigger mode of the P1 port interrupt. Set this bit 1 in the S1C17704. 1 (R/W): Level trigger mode 0 (R/W): Pulse trigger mode (default) In pulse trigger mode, the ITC samples interrupt signals at the rising edge of the system clock. When a high pulse is sampled, the ITC sets the interrupt flag (EIFTx) to 1 and stops sampling of that interrupt signal.

  • Page 74: 0X4308: External Interrupt Level Setup Register 1 (Itc_Elv1)

    0x0 R/W D[15:13] Reserved EITG3: Clock Timer Interrupt Trigger Mode Select Bit Selects the trigger mode of the clock timer interrupt. Set this bit 1 in the S1C17704. 1 (R/W): Level trigger mode 0 (R/W): Pulse trigger mode (default) See the description of EITG1 (D12) in the ITC_ELV0 register (0x4306).

  • Page 75: 0X430A: External Interrupt Level Setup Register 2 (Itc_Elv2)

    D[7:5] Reserved EITG4: 8-bit OSC1 Timer Interrupt Trigger Mode Select Bit Selects the trigger mode of the 8-bit OSC1 timer interrupt. Set this bit 1 in the S1C17704. 1 (R/W): Level trigger mode 0 (R/W): Pulse trigger mode (default) See the description of EITG1 (D12) in the ITC_ELV0 register (0x4306).

  • Page 76: 0X430C: External Interrupt Level Setup Register 3 (Itc_Elv3)

    D[15:13] Reserved EITG7: PWM & Capture Timer Interrupt Trigger Mode Select Bit Selects the trigger mode of the PWM & capture timer interrupt. Set this bit 1 in the S1C17704. 1 (R/W): Level trigger mode 0 (R/W): Pulse trigger mode (default) See the description of EITG1 (D12) in the ITC_ELV0 register (0x4306).

  • Page 77: 0X430E: Internal Interrupt Level Setup Register 0 (Itc_Ilv0)

    ITC changes the vector number and interrupt level to those of the new cause of interrupt. The first interrupt request is left pending. D[7:3] Reserved D[2:0] IILV0[2:0]: 8-bit Timer Interrupt Level Bits Sets the interrupt level (0 to 7) of the 8-bit timer interrupt. (Default: 0) See the description of IILV1[2:0] (D[10:8]). EPSON S1C17704 TECHNICAL MANUAL 6-21...

  • Page 78: 0X4310: Internal Interrupt Level Setup Register 1 (Itc_Ilv1)

    Reserved D[2:0] IILV2[2:0]: 16-bit Timer Ch.1 Interrupt Level Bits Sets the interrupt level (0 to 7) of the 16-bit timer Ch.1 interrupt. (Default: 0) See the description of IILV1[2:0] (D[10:8]) in the ITC_ILV0 register (0x430e). EPSON 6-22 S1C17704 TECHNICAL MANUAL...

  • Page 79: 0X4312: Internal Interrupt Level Setup Register 2 (Itc_Ilv2)

    See the description of IILV1[2:0] (D[10:8]) in the ITC_ILV0 register (0x430e). D[7:3] Reserved D[2:0] IILV4[2:0]: UART Interrupt Level Bits Sets the interrupt level (0 to 7) of the UART interrupt. (Default: 0) See the description of IILV1[2:0] (D[10:8]) in the ITC_ILV0 register (0x430e). EPSON S1C17704 TECHNICAL MANUAL 6-23...

  • Page 80: 0X4314: Internal Interrupt Level Setup Register 3 (Itc_Ilv3)

    See the description of IILV1[2:0] (D[10:8]) in the ITC_ILV0 register (0x430e). D[7:3] Reserved D[2:0] IILV6[2:0]: SPI Interrupt Level Bits Sets the interrupt level (0 to 7) of the SPI interrupt. (Default: 0) See the description of IILV1[2:0] (D[10:8]) in the ITC_ILV0 register (0x430e). EPSON 6-24 S1C17704 TECHNICAL MANUAL...

  • Page 81: Precautions

    • To prevent another interrupt from being generated for the same cause again after generation of an interrupt, be sure to reset the interrupt flag before enabling interrupts and setting the PSR again or executing the reti instruction. • The following S1C17704 interrupts use level trigger mode. - P0 port interrupt - P1 port interrupt...
  • Page 82 6 INTERRUPT CONTROLLER (ITC) THIS PAGE IS BLANK. EPSON 6-26 S1C17704 TECHNICAL MANUAL...

  • Page 83: Oscillator (Osc)

    7.1 Configuration of OSC Module The S1C17704 has two built-in oscillators (OSC3 and OSC1). The OSC3 oscillator generates the main clock (Max. 8.2 MHz) for operating the S1C17 Core and peripheral circuits at high speed. The OSC1 oscillator generates the sub clock (Typ.

  • Page 84: Osc3 Oscillator

    ∗ OSC3EN: OSC3 Enable Bit in the Oscillation Control (OSC_CTL) Register (D0/0x5061) At initial reset, OSC3EN is set to 1 for enabling OSC3 oscillation. Furthermore, the OSC3 clock is selected as the system clock, so the S1C17 Core starts operating with the OSC3 clock. EPSON S1C17704 TECHNICAL MANUAL...
  • Page 85 Note: The oscillation start time varies depending on the resonator and externally attached parts. Set the stable oscillation wait time with a safety margin. Refer to the oscillation start time example described in Chapter 26, “Electrical Characteristics.” EPSON S1C17704 TECHNICAL MANUAL...

  • Page 86: Osc1 Oscillator

    S1C17 Core is woken from SLEEP mode or when software turns the OSC1 oscillator circuit on. The OSC1 clock supply to the system is disabled for 256 OSC1 clock cycles after the OSC1 oscillator starts oscillating. EPSON S1C17704 TECHNICAL MANUAL...

  • Page 87: Switching The System Clock

    Set the stable oscillation wait time with a safety margin. Refer to the oscillation start time example described in Chapter 26, “Electrical Characteristics.” • The OSC1 oscillation cannot be stopped before switching the system clock to OSC3. EPSON S1C17704 TECHNICAL MANUAL...

  • Page 88: Controlling The Lcd Clock

    When LCKEN is set to 1, the clock generated with the above conditions is supplied to the LCD driver. If display on the LCD is not necessary, disable the clock supply to reduce current consumption. ∗ LCKEN: LCD Clock Enable Bit in the LCD Clock Setup (OSC_LCLK) Register (D0/0x5063) EPSON S1C17704 TECHNICAL MANUAL...

  • Page 89: Controlling The 8-Bit Osc1 Timer Clock

    8-bit OSC1 timer. When the application does not need the 8-bit OSC1 timer to run, disable the clock supply to reduce current consumption. ∗ T8O1CE: T8OSC1 Clock Enable Bit in the T8OSC1 Clock Control (OSC_T8OSC1) Register (D0/0x5065) EPSON S1C17704 TECHNICAL MANUAL...

  • Page 90: External Output Clock (Fout3, Fout1)

    ∗ FOUT3E: FOUT3 Output Enable Bit in the FOUT Control (OSC_FOUT) Register (D1/0x5064) FOUT3E FOUT3 output (P30) Figure 7.7.2 FOUT3 Output Note: The FOUT3 signal is generated asynchronously with writing to FOUT3E, therefore, a hazard will occur when the output is enabled or disabled. EPSON S1C17704 TECHNICAL MANUAL...
  • Page 91 ∗ FOUT1E: FOUT1 Output Enable Bit in the FOUT Control (OSC_FOUT) Register (D0/0x5064) FOUT1E FOUT1 output (P13) Figure 7.7.3 FOUT1 Output Note: The FOUT1 signal is generated asynchronously with writing to FOUT1E, therefore, a hazard will occur when the output is enabled or disabled. EPSON S1C17704 TECHNICAL MANUAL...

  • Page 92: Noise Filters For Reset And Nmi Inputs

    Notes: • Enable the filter for the RESET input under normal circumstances. • Although the S1C17704 has no external NMI input pin, the NMI request signal of the watchdog timer pass through the filter.

  • Page 93: Details Of Control Registers

    Sets up the 8-bit OSC1 timer clock. The following describes each OSC module control register. These are all 8-bit registers. Note: When setting the registers, be sure to write a 0, and not a 1, for all “reserved bits.” EPSON S1C17704 TECHNICAL MANUAL 7-11...

  • Page 94: 0X5060: Clock Source Select Register (Osc_Src)

    OSC3 oscillation to reduce current consumption. Note: When the system clock is switched from OSC3 to OSC1 immediately after the OSC1 oscillator starts oscillating, the system clock is halted until the OSC1 clock is activated (256 OSC1 clock-cycle period). EPSON 7-12 S1C17704 TECHNICAL MANUAL...

  • Page 95: 0X5061: Oscillation Control Register (Osc_Ctl)

    OSC1 clock-cycle period when the OSC1 oscillation is started by setting OSC1EN from 0 to 1. OSC3EN: OSC3 Enable Bit Enables/disables the OSC3 oscillator. 1 (R/W): Enable (On) (default) 0 (R/W): Disable (Off) Note: The OSC3 oscillator cannot be disabled when OSC3 is used as the system clock. EPSON S1C17704 TECHNICAL MANUAL 7-13...

  • Page 96: 0X5062: Noise Filter Enable Register (Osc_Nfen)

    S1C17 Core. Pulses that have a width of less than 16 cycles will be rejected as noise. Note: Although the S1C17704 has no external NMI input pin, the NMI request signal of the watchdog timer passes through the filter.

  • Page 97: X5063: Lcd Clock Setup Register (Osc_Lclk)

    LCKEN is set to 0 and the clock supply is disabled by default. By setting LCKEN to 1, the clock configured using the control bits above is supplied to the LCD driver. If an LCD display is unnecessary, disable the clock supply to reduce current consumption. EPSON S1C17704 TECHNICAL MANUAL 7-15...

  • Page 98: 0X5064: Fout Control Register (Osc_Fout)

    FOUT1 output, write 1 to the P13MUX bit (D3/P1_PMUX register) to switch the pin function. ∗ P13MUX: P13 Port Function Select Bit in the P1 Port Function Select (P1_PMUX) Register (D3/0x52a1) EPSON 7-16 S1C17704 TECHNICAL MANUAL...

  • Page 99: X5065: T8Osc1 Clock Control Register (Osc_T8Osc1)

    T8O1CE is set to 0 and the clock supply is disabled by default. By setting T8O1CE to 1, the clock configured using the control bits above is supplied to the 8-bit OSC1 timer. If 8-bit OSC1 timer function is unnecessary, disable the clock supply to reduce current consumption. EPSON S1C17704 TECHNICAL MANUAL 7-17...

  • Page 100: Precautions

    • The OSC1 oscillator cannot be disabled when OSC1 is used as the system clock. • Since the FOUT3/FOUT1 signals are generated asynchronously with writing to FOUT3E/FOUT1E, a hazard may be generated when the signal is turned on or off. EPSON 7-18 S1C17704 TECHNICAL MANUAL...

  • Page 101: Clock Generator (Clg)

    Figure 8.1.1 Structure of the CLG Module Current consumption can be reduced by controlling the clocks according to the processing requirements as well as by using the standby mode. For methods to reduce current consumption, see Appendix C, “Power Saving.” EPSON S1C17704 TECHNICAL MANUAL...

  • Page 102: Controlling The Cpu Core Clock (Cclk)

    Executing the slp instruction disables system clock supply to the CLG, therefore it also stops CCLK. When SLEEP mode is canceled by an external interrupt, supplying CCLK is resumed as well as the system clock supply to the CLG. For control of the system clock, see Chapter 7, “Oscillator (OSC).” EPSON S1C17704 TECHNICAL MANUAL...

  • Page 103: Controlling The Peripheral Module Clock (Pclk)

    The LCD driver operates with the OSC1 clock or a divided OSC3 clock. Although the control registers cannot be accessed for read and write when the PCLK supply is disabled, the LCD driver keeps refreshing the display. Also PCLK is not necessary for accessing the display memory. EPSON S1C17704 TECHNICAL MANUAL...

  • Page 104: Details Of Control Registers

    Configures the CCLK division ratio. The following describes each CLG module control register. These are all 8-bit registers. Note: When setting the registers, be sure to write a 0, and not a 1, for all “reserved bits.” EPSON S1C17704 TECHNICAL MANUAL...

  • Page 105: 0X5080: Pclk Control Register (Clg_Pclk)

    Therefore, PCLK is not required after the control registers are set once and the module starts operating. • Clock timer • Stopwatch timer • Watchdog timer • 8-bit OSC1 timer • LCD driver Note: Be sure to avoid setting PCKEN[1:0] to 0x2 or 0x1, as it stops some peripheral modules. EPSON S1C17704 TECHNICAL MANUAL...

  • Page 106: 0X5081: Cclk Control Register (Clg_Cclk)

    Selects a gear ratio to decelerate the system clock. This determines the rate of the CCLK clock for driving the S1C17 Core. Drive the S1C17 Core with the slowest clock possible to reduce current consumption. Table 8.4.3 Selecting CCLK Gear Ratio CCLKGR[1:0] Gear ratio (Default: 0x0) EPSON S1C17704 TECHNICAL MANUAL...

  • Page 107: Precautions

    - 8-bit OSC1 timer - LCD driver • Be sure to avoid setting PCKEN[1:0] (D[1:0]/CLG_PCLK register) to 0x2 or 0x1, as it stops some peripheral modules. ∗ PCKEN[1:0]: PCLK Enable Bits in the PCLK Control (CLG_PCLK) Register (D[1:0]/0x5080) EPSON S1C17704 TECHNICAL MANUAL...
  • Page 108 8 CLOCK GENERATOR (CLG) THIS PAGE IS BLANK. EPSON S1C17704 TECHNICAL MANUAL...

  • Page 109: Prescaler (Psc)

    9.1 Configuration of the Prescaler The S1C17704 incorporates a prescaler for generating the source clock of the timers and other peripheral modules. The prescaler divides the PCLK clock, which is supplied from the clock generator, by 1 to 16K to generate 15 clocks with different frequencies.

  • Page 110: Details Of Control Register

    1 (R/W): Run 0 (R/W): Stop (default) Write 1 to PRUN to run the prescaler and write 0 to stop the prescaler. When the timer and interface modules are idle, stop the prescaler to reduce current consumption. EPSON S1C17704 TECHNICAL MANUAL...

  • Page 111: Precaution

    9 PRESCALER (PSC) 9.3 Precaution Supply PCLK from the clock generator before the prescaler can be used. EPSON S1C17704 TECHNICAL MANUAL...
  • Page 112 9 PRESCALER (PSC) THIS PAGE IS BLANK. EPSON S1C17704 TECHNICAL MANUAL...

  • Page 113: O Ports (P)

    10.1 Structure of I/O Port The S1C17704 contains 28 I/O ports (P0[7:0], P1[7:0], P2[7:0], and P3[3:0]) that can be directed for input or output with software. Although the I/O pins, except for some I/O ports, are shared with internal peripheral modules, the pins can be used as general-purpose input/output ports unless they are used for the peripheral modules.

  • Page 114: Selecting I/O Pin Functions (Port Mux)

    For the pin function other than the I/O port, see the descriptions for the peripheral module indicated in ( ). The subsequent sections explain the port functions assuming that the pin has been set for the general-purpose I/O port. EPSON 10-2 S1C17704 TECHNICAL MANUAL...

  • Page 115: Data Input/Output

    ∗ P2OUT[7:0]: P2[7:0] Port Output Data Bits in the P2 Port Output Data (P2_OUT) Register (D[7:0]/0x5221) ∗ P3OUT[3:0]: P3[3:0] Port Output Data Bits in the P3 Port Output Data (P3_OUT) Register (D[3:0]/0x5231) Even in the input mode, data can be written to PxOUT[7:0] without affecting the pin status. EPSON S1C17704 TECHNICAL MANUAL 10-3...

  • Page 116: Pull-Up Control

    10 I/O PORTS (P) 10.4 Pull-Up Control The S1C17704 I/O ports have a built-in pull-up resistor and whether it is used or not can be selected using PxPU[7:0] (Px_PU register) for each bit individually. ∗ P0PU[7:0]: P0[7:0] Port Pull-up Enable Bits in the P0 Port Pull-up Control (P0_PU) Register (D[7:0]/0x5203) ∗...

  • Page 117: Input Interface Level

    When PxSM[7:0] is set to 1 (default), the port is configured with a CMOS Schmitt level input interface. When the bit is set to 0, the port is configured with a CMOS level input interface. EPSON S1C17704 TECHNICAL MANUAL 10-5...

  • Page 118: Chattering Filter For P0 Ports

    This causes the input interrupt to malfunction, therefore setup the input signal so that the rise/fall time is 25 ns or less. EPSON 10-6 S1C17704 TECHNICAL MANUAL...

  • Page 119: Port Input Interrupt

    When PxEDGE[7:0] is set to 1, an input interrupt of the corresponding port will be generated at the falling edge; when the bit is set to 0 (default), an interrupt will be generated at the rising edge. EPSON S1C17704 TECHNICAL MANUAL 10-7...
  • Page 120 • No other cause of interrupt having higher priority, such as NMI, has occurred. For details on these interrupt control registers, as well as the device operation when an interrupt has occurred, refer to Chapter 6, “Interrupt Controller (ITC).” EPSON 10-8 S1C17704 TECHNICAL MANUAL...

  • Page 121: Interrupt Vectors

    10 I/O PORTS (P) Interrupt vectors The following shows the vector numbers and vector addresses for the port interrupts: Table 10.7.2 Port Interrupt Vectors Port Vector number Vector address 4 (0x04) 0x8010 5 (0x05) 0x8014 EPSON S1C17704 TECHNICAL MANUAL 10-9...

  • Page 122: Details Of Control Registers

    Selects the P3 port function. The following describes each I/O port control register. These are all 8-bit registers. Note: When setting the registers, be sure to write a 0, and not a 1, for all “reserved bits.” EPSON 10-10 S1C17704 TECHNICAL MANUAL...

  • Page 123: X5200/0X5210/0X5220/0X5230: Px Port Input Data Registers (Px_In)

    If the pin voltage is high, 1 is read out as input data; if the pin voltage is low, 0 is read out as input data. In the output mode, an indefinite value is read out. PxIN[7:0] are read only bits and write operation is ineffective. EPSON S1C17704 TECHNICAL MANUAL 10-11...

  • Page 124: X5201/0X5211/0X5221/0X5231: Px Port Output Data Registers (Px_Out)

    I/O port pin. If the data written to the port is 1, the port pin goes high; if the data is 0, the port pin goes low. Even in input mode, data can be written to the port data register. EPSON 10-12 S1C17704 TECHNICAL MANUAL...

  • Page 125: 0X5202/0X5212/0X5222/0X5232: Px Port I/O Direction Control Registers (Px_Io)

    When a bit is set to 1, the corresponding I/O port is directed for output; if it is set to 0, the I/O port is directed for input. When the pin is used for a peripheral module, the input/output direction depends on the peripheral function. EPSON S1C17704 TECHNICAL MANUAL 10-13...

  • Page 126: 0X5203/0X5213/0X5223/0X5233: Px Port Pull-Up Control Registers (Px_Pu)

    This wait time should be the amount of time or more calculated by the following expression. × (C + load capacitance on the board) × 1.6 [seconds] Wait time = R : Pull-up resistance Max. value : Pin capacitance Max. value EPSON 10-14 S1C17704 TECHNICAL MANUAL...

  • Page 127: 0X5204/0X5214/0X5224/0X5234: Px Port Schmitt Trigger Control Registers (Px_Sm)

    The PxSM[7:0] bits are the Schmitt input control bits corresponding to the Px[7:0] ports respectively. When a bit is set to 1, the Schmitt trigger input buffer is enabled; if it is set to 0, the I/O port uses a CMOS level input buffer. EPSON S1C17704 TECHNICAL MANUAL 10-15...

  • Page 128: 0X5205/5215: Px Port Interrupt Mask Registers (Px_Imsk)

    The input level transition at the port pin whose interrupt has been disabled does not affect occurrence of the interrupt. In addition, it is necessary to set the P0 and P1 port interrupt enable bits in the ITC to interrupt enabled to actually generate an interrupt. EPSON 10-16 S1C17704 TECHNICAL MANUAL...

  • Page 129: X5206/5216: Px Port Interrupt Edge Select Registers (Px_Edge)

    When a PxEDGE[7:0] bit is set to 1, an input interrupt of the corresponding port will be generated at the falling edge; when it is set to 0, an interrupt will be generated at the rising edge. EPSON S1C17704 TECHNICAL MANUAL 10-17...

  • Page 130: 0X5207/5217: Px Port Interrupt Flag Registers (Px_Iflg)

    PxIE[7:0] (Px_IMSK register). ∗ P0IE[7:0]: P0[7:0] Port Interrupt Enable Bits in the P0 Port Interrupt Mask (P0_IMSK) Register (D[7:0]/0x5205) ∗ P1IE[7:0]: P1[7:0] Port Interrupt Enable Bits in the P1 Port Interrupt Mask (P1_IMSK) Register (D[7:0]/0x5215) EPSON 10-18 S1C17704 TECHNICAL MANUAL...

  • Page 131: 0X5208: P0 Port Chattering Filter Control Register (P0_Chat)

    This causes the input interrupt to malfunction, therefore setup the input signal so that the rise/fall time is 25 ns or less. EPSON S1C17704 TECHNICAL MANUAL 10-19...

  • Page 132: 0X5209: P0 Port Key-Entry Reset Configuration Register (P0_Krst)

    • The P0 port key-entry reset function cannot be used for power-on reset as it must be enabled with software. • The P0 port key-entry reset function cannot be used in SLEEP mode. EPSON 10-20 S1C17704 TECHNICAL MANUAL...

  • Page 133: 0X52A0: P0 Port Function Select Register (P0_Pmux)

    The P04 and P05 I/O port pins are shared with a peripheral module. This register configures the pin functions. D[7:6] Reserved P05MUX: P05 Port Function Select Bit 1 (R/W): REMO (REMC) 0 (R/W): P05 port (default) P04MUX: P04 Port Function Select Bit 1 (R/W): REMI (REMC) 0 (R/W): P04 port (default) D[3:0] Reserved EPSON S1C17704 TECHNICAL MANUAL 10-21...

  • Page 134: 0X52A1: P1 Port Function Select Register (P1_Pmux)

    0 (R/W): P15 port (default) P14MUX: P14 Port Function Select Bit 1 (R/W): SDA (I2C) 0 (R/W): P14 port (default) P13MUX: P13 Port Function Select Bit 1 (R/W): FOUT1 (OSC) 0 (R/W): P13 port (default) D[2:0] Reserved EPSON 10-22 S1C17704 TECHNICAL MANUAL...

  • Page 135: 0X52A2: P2 Port Function Select Register (P2_Pmux)

    0 (R/W): P22 port (default) P21MUX: P21 Port Function Select Bit 1 (R/W): SDO (SPI) 0 (R/W): P21 port (default) P20MUX: P20 Port Function Select Bit 1 (R/W): SDI (SPI) 0 (R/W): P20 port (default) EPSON S1C17704 TECHNICAL MANUAL 10-23...

  • Page 136: 0X52A3: P3 Port Function Select Register (P3_Pmux)

    0 (R/W): DST2 (DBG) (default) P31MUX: P31 Port Function Select Bit 1 (R/W): P31 port 0 (R/W): DCLK (DBG) (default) P30MUX: P30 Port Function Select Bit 1 (R/W): FOUT3 (OSC) 0 (R/W): P30 port (default) EPSON 10-24 S1C17704 TECHNICAL MANUAL...

  • Page 137: Precautions

    • The P0 port key-entry reset function cannot be used for power-on reset as it must be enabled with software. • The P0 port key-entry reset function cannot be used in SLEEP mode. EPSON S1C17704 TECHNICAL MANUAL 10-25...
  • Page 138 10 I/O PORTS (P) THIS PAGE IS BLANK. EPSON 10-26 S1C17704 TECHNICAL MANUAL...

  • Page 139: 16-Bit Timers (T16)

    11 16-bit Timers (T16) 11.1 Outline of the 16-bit Timers The S1C17704 is equipped with three channels of 16-bit timers (T16). The 16-bit timer includes a 16-bit presettable down counter and a 16-bit reload data register for setting the preset value.

  • Page 140: 16-Bit Timer Operating Mode

    Notes: • Before the 16-bit timer can start counting in internal clock mode, the prescaler must be run. • When setting the count clock, make sure the 16-bit timer counter is stopped. For controlling the prescaler, see Chapter 9, “Prescaler (PSC).” EPSON 11-2 S1C17704 TECHNICAL MANUAL...

  • Page 141: External Clock Mode

    The 16-bit timer set in this mode does not use the prescaler. If the prescaler clocks are not used in other peripheral modules, the prescaler can be stopped to reduce current consumption. (Note that the P0 port chattering filter uses a prescaler clock.) EPSON S1C17704 TECHNICAL MANUAL 11-3...

  • Page 142: Pulse Width Measurement Mode

    Example 2) When detecting a pulse that exceeds the specified width Internal count clock PRUN External input signal Counter (CKACTV = 0) 0x2 0x1 0x0 Underflow interrupt Figure 11.2.3.1 Count Operation in Pulse Width Measurement Mode EPSON 11-4 S1C17704 TECHNICAL MANUAL...

  • Page 143: Count Mode

    When an underflow occurs, the counter is preset with the reload data register value before the timer operation stops. Set the 16-bit timer in this mode when a certain waiting time must be generated or measuring pulse widths. EPSON S1C17704 TECHNICAL MANUAL 11-5...

  • Page 144: 16-Bit Timer Reload Register And Underflow Period

    The underflow period is calculated by the expression below. TR + 1 clk_in Underflow period = ———— [s] Underflow cycle = ———— [Hz] clk_in TR + 1 clk_in: Count clock (prescaler output clock) frequency [Hz] Reload data (0–65535) EPSON 11-6 S1C17704 TECHNICAL MANUAL...

  • Page 145: Resetting The 16-Bit Timer

    To reset the 16-bit timer, write 1 to the PRESER bit (D1/T16_CTLx register). This initializes the counter by presetting the reload data register value. ∗ PRESER: Timer Reset Bit in the 16-bit Timer Ch.x Control (T16_CTLx) Register (D1/0x4226/0x4246/0x4266) EPSON S1C17704 TECHNICAL MANUAL 11-7...

  • Page 146: 16-Bit Timer Run/Stop Control

    In pulse width measurement mode, the timer performs counting only when PRUN = 1 and the external input signal is the specified active level. When the external input signal goes inactive, the 16-bit timer stops counting and maintains the count value until the next active pulse is input. (See Figure 11.2.3.1.) EPSON 11-8 S1C17704 TECHNICAL MANUAL...

  • Page 147: 16-Bit Timer Output Signal

    The reload data register value to obtain a desired transfer rate is calculated by the expression below. clk_in TR = ———— - 1 bps × 2 clk_in TR = ———— - 1 bps × 2 clk_in: Count clock (prescaler output clock) frequency [Hz] Reload data (0–65535) bps: Transfer rate (bits/second) EPSON S1C17704 TECHNICAL MANUAL 11-9...

  • Page 148: 16-Bit Timer Interrupt

    The following shows the vector numbers and vector addresses for the timer interrupt: Table 11.8.2 Timer Interrupt Vectors Timer channel Vector number Vector address Timer Ch.0 13 (0x0d) 0x8034 Timer Ch.1 14 (0x0e) 0x8038 Timer Ch.2 15 (0x0f) 0x803c EPSON 11-10 S1C17704 TECHNICAL MANUAL...

  • Page 149: Details Of Control Registers

    Sets the timer mode and starts/stops the timer. The following describes each 16-bit timer register. These are all 16-bit registers. Note: When setting the registers, be sure to write a 0, and not a 1, for all “reserved bits.” EPSON S1C17704 TECHNICAL MANUAL 11-11...

  • Page 150: 0X4220/0X4240/0X4260: 16-Bit Timer Ch.x Input Clock Select Registers (T16_Clkx)

    Prescaler output clock Reserved PCLK•1/128 PCLK•1/16384 PCLK•1/64 PCLK•1/8192 PCLK•1/32 PCLK•1/4096 PCLK•1/16 PCLK•1/2048 PCLK•1/8 PCLK•1/1024 PCLK•1/4 PCLK•1/512 PCLK•1/2 PCLK•1/256 PCLK•1/1 (Default: 0x0) Note: When setting the count clock, make sure the 16-bit timer counter is stopped. EPSON 11-12 S1C17704 TECHNICAL MANUAL...

  • Page 151: 0X4222/0X4242/0X4262: 16-Bit Timer Ch.x Reload Data Registers (T16_Trx)

    (and between underflows). This makes it possible to obtain a desired wait time, a periodical interrupt interval, or programmable transfer clock for the serial interface. EPSON S1C17704 TECHNICAL MANUAL 11-13...

  • Page 152: 0X4224/0X4244/0X4264: 16-Bit Timer Ch.x Counter Data Registers (T16_Tcx)

    0x4264: 16-bit Timer Ch.2 Counter Data Register (T16_TC2) D[15:0] TC[15:0]: 16-bit Timer Counter Data The counter data can be read from this register. (Default: 0xffff) This is a read-only register, so the writing operation is invalid. EPSON 11-14 S1C17704 TECHNICAL MANUAL...

  • Page 153: 0X4226/0X4246/0X4266: 16-Bit Timer Ch.x Control Registers (T16_Ctlx)

    This makes it possible to generate an interrupt when a pulse longer than a specified width is input or to measure the input pulse width. D[7:5] Reserved EPSON S1C17704 TECHNICAL MANUAL 11-15...
  • Page 154 The timer starts counting by writing 1 to PRUN and stops counting by writing 0. In the stop state, the counter data is retained until the timer is reset or placed in a run state. EPSON 11-16 S1C17704 TECHNICAL MANUAL...

  • Page 155: Precautions

    11 16-BIT TIMERS (T16) 11.10 Precautions • Before the 16-bit timer can start counting, the prescaler must be run. • When setting the count clock or count mode, make sure the 16-bit timer is turned off. EPSON S1C17704 TECHNICAL MANUAL 11-17...
  • Page 156 11 16-BIT TIMERS (T16) THIS PAGE IS BLANK. EPSON 11-18 S1C17704 TECHNICAL MANUAL...

  • Page 157: 12 8-Bit Timer (T8F)

    12 8-bit Timer (T8F) 12.1 Outline of the 8-bit Timer The S1C17704 incorporates one channel of 8-bit timer with fine mode. The 8-bit timer module includes an 8-bit presettable down counter and an 8-bit reload data register for setting the preset value.

  • Page 158: Count Mode Of The 8-Bit Timer

    Set the 8-bit timer in this mode when a certain waiting time must be generated. Note: When setting the count mode, make sure the 8-bit timer counter is stopped. EPSON 12-2 S1C17704 TECHNICAL MANUAL...

  • Page 159: Count Clock

    Notes: • Before the 8-bit timer can start counting, the prescaler must be run. • When setting the count clock, make sure the 8-bit timer counter is stopped. For controlling the prescaler, see Chapter 9, “Prescaler (PSC).” EPSON S1C17704 TECHNICAL MANUAL 12-3...

  • Page 160: 8-Bit Timer Reload Register And Underflow Period

    Count clock (prescaler output clock) frequency [Hz] T8F_TR: Reload data (0–255) Note: The UART divides the 8-bit timer output by 16 to generate the sampling clock. Make sure of the division ratio when setting a transfer rate. EPSON 12-4 S1C17704 TECHNICAL MANUAL...

  • Page 161: Resetting The 8-Bit Timer

    To reset the 8-bit timer, write 1 to the PRESER bit (D1/T8F_CTL register). This initializes the counter by presetting the Reload Data Register value. ∗ PRESER: Timer Reset Bit in the 8-bit Timer Control (T8F_CTL) Register (D1/0x4206) EPSON S1C17704 TECHNICAL MANUAL 12-5...

  • Page 162: 8-Bit Timer Run/Stop Control

    One-shot mode Count clock PRESER write Set by software Reset by hardware PRUN Counter Interrupt request Repeat mode Count clock PRESER write PRUN Set by software Reset by software Counter Interrupt request Figure 12.6.1 Count Operation EPSON 12-6 S1C17704 TECHNICAL MANUAL...

  • Page 163: 8-Bit Timer Output Signal

    {(T8F_TR + 1) × 16 + TFMD} clk_in ÷ 16 T8F_TR = ——— - TFMD - 16 clk_in: Count clock (prescaler output clock) frequency [Hz] T8F_TR: Reload data (0–255) bps: Transfer rate (bits/second) TFMD: Fine mode setting value (0–15) EPSON S1C17704 TECHNICAL MANUAL 12-7...

  • Page 164: Fine Mode

    Underflow signal (corrected) Delayed Output clock (not corrected) Output clock (corrected) Figure 12.8.1 Delay Cycle Insertion in Fine Mode At initial reset, TFMD[3:0] is set to 0x0. No delay will be inserted in this setting. EPSON 12-8 S1C17704 TECHNICAL MANUAL...

  • Page 165: 8-Bit Timer Interrupt

    For details on these interrupt control registers, as well as the device operation when an interrupt has occurred, see Chapter 6, “Interrupt Controller (ITC).” Interrupt vector The following shows the vector number and vector address for the timer interrupt: Vector number: 12 (0x0c) Vector address: 0x8030 EPSON S1C17704 TECHNICAL MANUAL 12-9...

  • Page 166: Details Of Control Registers

    Sets the timer mode and starts/stops the timer. The following describes each 8-bit timer register. These are all 16-bit registers. Note: When setting the registers, be sure to write a 0, and not a 1, for all “reserved bits.” EPSON 12-10 S1C17704 TECHNICAL MANUAL...

  • Page 167: 0X4200: 8-Bit Timer Input Clock Select Register (T8F_Clk)

    Prescaler output clock Reserved PCLK•1/128 PCLK•1/16384 PCLK•1/64 PCLK•1/8192 PCLK•1/32 PCLK•1/4096 PCLK•1/16 PCLK•1/2048 PCLK•1/8 PCLK•1/1024 PCLK•1/4 PCLK•1/512 PCLK•1/2 PCLK•1/256 PCLK•1/1 (Default: 0x0) Note: When setting the count clock, make sure the 8-bit timer counter is stopped. EPSON S1C17704 TECHNICAL MANUAL 12-11...

  • Page 168: 0X4202: 8-Bit Timer Reload Data Register (T8F_Tr)

    (and between underflows). This makes it possible to obtain a desired wait time, a periodical interrupt interval, or programmable transfer clock for the serial interface. EPSON 12-12 S1C17704 TECHNICAL MANUAL...

  • Page 169: 0X4204: 8-Bit Timer Counter Data Register (T8F_Tc)

    TC7 = MSB (T8F_TC) TC0 = LSB D[15:8] Reserved D[7:0] TC[7:0]: 8-bit Timer Counter Data The counter data can be read from this register. (Default: 0xff) This is a read-only register, so the writing operation is invalid. EPSON S1C17704 TECHNICAL MANUAL 12-13...

  • Page 170: 0X4206: 8-Bit Timer Control Register (T8F_Ctl)

    – D: Indicates that a delay is inserted. Count clock Underflow signal (not corrected) Underflow signal (corrected) Delayed Output clock (not corrected) Output clock (corrected) Figure 12.10.1 Delay Cycle Inserted in Fine Mode D[7:5] Reserved EPSON 12-14 S1C17704 TECHNICAL MANUAL...
  • Page 171 The timer starts counting by writing 1 to PRUN and stops counting by writing 0. In the stop state, the counter data is retained until the timer is reset or placed in a run state. EPSON S1C17704 TECHNICAL MANUAL 12-15...

  • Page 172: Precautions

    12 8-BIT TIMER (T8F) 12.11 Precautions • Before the 8-bit timer can start counting, the prescaler must be run. • When setting the count clock or count mode, make sure the 8-bit timer is turned off. EPSON 12-16 S1C17704 TECHNICAL MANUAL...

  • Page 173: Pwm & Capture Timer (T16E)

    13 PWM & CAPTURE TIMER (T16E) 13 PWM & Capture Timer (T16E) 13.1 Outline of the PWM & Capture Timer The S1C17704 incorporates one channel of PWM & capture timer. Figure 13.1.1 shows the structure of the PWM & capture timer. PWM & capture timer...

  • Page 174: Pwm & Capture Timer Operating Mode

    The PWM & capture timer counts up at the rising edge of the input signal. The PWM & capture timer set in this mode does not use the prescaler. If the prescaler clocks are not used in other peripheral modules, the prescaler can be stopped to reduce current consumption. EPSON 13-2 S1C17704 TECHNICAL MANUAL...

  • Page 175: Setting/Resetting The Counter Value

    After the counter starts counting, it will be reset by the hardware when the counter reaches compare data B. Furthermore, any data can be set to the counter by writing it to T16ETC[15:0] (D[15:0]/T16E_TC register). ∗ T16ETC[15:0]: Counter Data in the PWM Timer Counter Data (T16E_TC) Register (D[15:0]/0x5304) EPSON S1C17704 TECHNICAL MANUAL 13-3...

  • Page 176: Setting Compare Data

    The counter reset period is calculated by the expression below. CB + 1 Counter reset period = ———— [s] clk_in clk_in Counter reset cycle = ———— [Hz] CB + 1 Compare data B (T16E_CB register value) clk_in: Prescaler output clock frequency EPSON 13-4 S1C17704 TECHNICAL MANUAL...

  • Page 177: Pwm & Capture Timer Run/Stop Control

    0. T16ERUN T16ERST T16E_CA T16E_CB Input clock T16E_TC Reset Compare A Reset and Compare A Reset and interrupt compare B interrupt compare B interrupt interrupt Figure 13.5.1 Basic Operation Timing of Counter EPSON S1C17704 TECHNICAL MANUAL 13-5...

  • Page 178: Controlling Clock Output

    INITOL and INVOUT. The output pin holds this level until the output level changes due to the counter value after the timer output is enabled. Table 13.6.1 Initial Output Level INITOL INVOUT Initial output level High High EPSON 13-6 S1C17704 TECHNICAL MANUAL...
  • Page 179 When the counter becomes equal to the compare data B set in the T16E_CB register (0x5302), the counter is reset and the output pin goes high. At the same time a cause of compare B interrupt occurs. EPSON S1C17704 TECHNICAL MANUAL 13-7...
  • Page 180 (2) When compare data are set as A > B (or set as A > B × 2 in fine mode), the compare B match signal will be generated but no compare A match signal will be generated. In this case, the timer output signal is fixed at the low (or high when INVOUT = 1). EPSON 13-8 S1C17704 TECHNICAL MANUAL...

  • Page 181: Pwm & Capture Timer Interrupt

    ITC, to clear the cause of interrupt. Note: To avoid occurrence of unnecessary interrupts, be sure to reset the CAIF or CBIF flag before the compare A match or compare B match interrupt is enabled using CAIE or CBIE. EPSON S1C17704 TECHNICAL MANUAL 13-9...
  • Page 182 (this also resets the interrupt flag in the ITC). Interrupt vector The following shows the vector number and vector address for the PWM & capture timer interrupt: Vector number: 11 (0x0b) Vector address: 0x802c EPSON 13-10 S1C17704 TECHNICAL MANUAL...

  • Page 183: Details Of Control Registers

    Indicates/resets interrupt occurrence status. The following describes each PWM & capture timer register. These are all 16-bit registers. Note: When setting the registers, be sure to write a 0, and not a 1, for all “reserved bits.” EPSON S1C17704 TECHNICAL MANUAL 13-11...

  • Page 184: 0X5300: Pwm Timer Compare Data A Register (T16E_Ca)

    The data set in this register is compared with the counter data. When the contents match, a cause of compare A interrupt is generated and the output signal rises (INVOUT (D4/T16E_CTL register) = 0) or falls (INVOUT = 1). This does not affect the counter value and count-up operation. EPSON 13-12 S1C17704 TECHNICAL MANUAL...

  • Page 185: 0X5302: Pwm Timer Compare Data B Register (T16E_Cb)

    The data set in this register is compared with the counter data. When the contents match, a cause of compare B interrupt is generated and the output signal rises (INVOUT (D4/T16E_CTL register) = 0) or falls (INVOUT = 1). Furthermore, the counter is reset to 0. EPSON S1C17704 TECHNICAL MANUAL 13-13...

  • Page 186: 0X5304: Pwm Timer Counter Data Register (T16E_Tc)

    T16ETC15 = MSB Register T16ETC0 = LSB (T16E_TC) D[15:0] T16ETC[15:0]: Counter Data The counter data can be read from this register. (Default: 0x0) Furthermore, data can be set to the counter by writing it to this register. EPSON 13-14 S1C17704 TECHNICAL MANUAL...

  • Page 187: 0X5306: Pwm Timer Control Register (T16E_Ctl)

    By writing 1 to INVOUT, an active-low signal (off level = high) is generated for the TOUT output. When INVOUT is set to 0, an active-high signal (off level = low) is generated. Writing 1 to this bit inverts the initial output level set using INITOL (D8) as well. EPSON S1C17704 TECHNICAL MANUAL 13-15...
  • Page 188 The PWM & capture timer starts counting up by writing 1 to T16ERUN and stops by writing 0. In Stop state, the counter data is retained until the timer is reset or placed in a Run state. By changing states from Stop to Run, the timer can restart counting beginning at the retained count. EPSON 13-16 S1C17704 TECHNICAL MANUAL...

  • Page 189: 0X5308: Pwm Timer Input Clock Select Register (T16E_Clk)

    Prescaler output clock Reserved PCLK•1/128 PCLK•1/16384 PCLK•1/64 PCLK•1/8192 PCLK•1/32 PCLK•1/4096 PCLK•1/16 PCLK•1/2048 PCLK•1/8 PCLK•1/1024 PCLK•1/4 PCLK•1/512 PCLK•1/2 PCLK•1/256 PCLK•1/1 (Default: 0x0) Note: When setting the count clock, make sure the PWM & capture timer counter is stopped. EPSON S1C17704 TECHNICAL MANUAL 13-17...

  • Page 190: 0X530A: Pwm Timer Interrupt Mask Register (T16E_Imsk)

    Setting CAIE to 1 enables the compare A interrupt; setting to 0 disables the interrupt. In addition, it is necessary to set the PWM & capture timer interrupt enable bits in the ITC to interrupt enabled to actually generate an interrupt. EPSON 13-18 S1C17704 TECHNICAL MANUAL...

  • Page 191: 0X530C: Pwm Timer Interrupt Flag Register (T16E_Iflg)

    The CAIF and CBIF flags are reset by writing 1. Note: To avoid occurrence of unnecessary interrupts, be sure to reset the CAIF or CBIF flag before the compare A match or compare B match interrupt is enabled using CAIE (D0/T16E_IMSK) or CBIE (D1/T16E_IMSK). EPSON S1C17704 TECHNICAL MANUAL 13-19...

  • Page 192: Precautions

    • To avoid occurrence of unnecessary interrupts, be sure to reset CAIF (D0/T16E_IFLG register) or CBIF (D1/ T16E_IFLG register) flag before the compare A match or compare B match interrupt is enabled using CAIE (D0/ T16E_IMSK register) or CBIE (D1/T16E_IMSK register). EPSON 13-20 S1C17704 TECHNICAL MANUAL...

  • Page 193: 14 8-Bit Osc1 Timer (T8Osc1)

    14 8-bit OSC1 Timer (T8OSC1) 14.1 Outline of the 8-bit OSC1 Timer The S1C17704 incorporates one channel of 8-bit OSC1 timer that uses OSC1 as its clock source. Figure 14.1.1 shows the structure of the 8-bit OSC1 timer. 8-bit OSC1 Timer...

  • Page 194: Count Mode Of The 8-Bit Osc1 Timer

    Set the 8-bit OSC1 timer in this mode when a certain waiting time must be generated. Note: When setting the count mode, make sure the 8-bit OSC1 timer counter is stopped. EPSON 14-2 S1C17704 TECHNICAL MANUAL...

  • Page 195: Count Clock

    ∗ T8O1CE: T8OSC1 Clock Enable Bit in the T8OSC1 Clock Control (OSC_T8OSC1) Register (D0/0x5065) Note: When setting the count clock, make sure the 8-bit OSC1 timer counter is stopped. For control of the clock, see Chapter 7, “Oscillator (OSC).” EPSON S1C17704 TECHNICAL MANUAL 14-3...

  • Page 196: Resetting The 8-Bit Osc1 Timer

    ∗ T8ORST: Timer Reset Bit in the 8-bit OSC1 Timer Control (T8OSC1_CTL) Register (D4/0x50c0) Normally, reset the counter before starting count-up by writing 1 to this control bit. After the counter starts counting, it will be reset by the hardware when the counter reaches compare data. EPSON 14-4 S1C17704 TECHNICAL MANUAL...

  • Page 197: Setting Compare Data

    The compare match period is calculated by the expression below. CMP + 1 Compare match period = ————— [s] clk_in clk_in Compare match cycle = ————— [Hz] CMP + 1 CMP: Compare data (T8OSC1_CMP register value) clk_in: 8-bit OSC1 timer count clock frequency EPSON S1C17704 TECHNICAL MANUAL 14-5...

  • Page 198: 8-Bit Osc1 Timer Run/Stop Control

    Input clock T8OCNT Reset Reset and compare match interrupt Repeat mode T8ORUN T8ORST T8OCMP Input clock T8OCNT Reset Reset and Reset and compare match compare match interrupt interrupt Figure 14.6.1 Basic Operation Timing of Counter EPSON 14-6 S1C17704 TECHNICAL MANUAL...

  • Page 199: 8-Bit Osc1 Timer Interrupt

    EIEN4 to 0. EIFT4 is always set to 1 by the interrupt signal sent from the T8OSC1 module, regardless of how EIEN4 is set (even when set to 0). EILV4[2:0] sets the interrupt level (0 to 7) of the 8-bit OSC1 timer interrupt. EPSON S1C17704 TECHNICAL MANUAL 14-7...
  • Page 200 (this also resets the interrupt flag in the ITC). Interrupt vector The following shows the vector number and vector address for the 8-bit OSC1 timer interrupt: Vector number: 8 (0x08) Vector address: 0x8020 EPSON 14-8 S1C17704 TECHNICAL MANUAL...

  • Page 201: Details Of Control Registers

    Indicates/resets interrupt occurrence status. The following describes each 8-bit OSC1 timer register. These are all 8-bit registers. Note: When setting the registers, be sure to write a 0, and not a 1, for all “reserved bits.” EPSON S1C17704 TECHNICAL MANUAL 14-9...

  • Page 202: 0X50C0: 8-Bit Osc1 Timer Control Register (T8Osc1_Ctl)

    The timer starts counting by writing 1 to T8ORUN and stops counting by writing 0. In the stop state, the counter data is retained until the timer is reset or placed in a run state. EPSON 14-10 S1C17704 TECHNICAL MANUAL...

  • Page 203: 0X50C1: 8-Bit Osc1 Timer Counter Data Register (T8Osc1_Cnt)

    The counter value should be obtained by one of the following procedures: • Read the counter value after stopping the counter. • Read the counter value twice to determine that both read results are the same and that the read value is significant. EPSON S1C17704 TECHNICAL MANUAL 14-11...

  • Page 204: 0X50C2: 8-Bit Osc1 Timer Compare Data Register (T8Osc1_Cmp)

    Sets the compare data for the 8-bit OSC1 timer. (Default: 0x0) The data set in this register is compared with the counter data. When the contents match, a cause of compare interrupt is generated. At the same time, the counter is reset to 0. EPSON 14-12 S1C17704 TECHNICAL MANUAL...

  • Page 205: 0X50C3: 8-Bit Osc1 Timer Interrupt Mask Register (T8Osc1_Imsk)

    Setting T8OIE to 1 enables the 8-bit OSC1 timer to request interrupts to the ITC; setting to 0 disables the interrupt. In addition, it is necessary to set the 8-bit OSC1 timer interrupt enable bits in the ITC to interrupt enabled to actually generate an interrupt. EPSON S1C17704 TECHNICAL MANUAL 14-13...

  • Page 206: 0X50C4: 8-Bit Osc1 Timer Interrupt Flag Register (T8Osc1_Iflg)

    (this also resets the interrupt flag in the ITC). The T8OIF flag is reset by writing 1. Note: To avoid occurrence of unnecessary interrupts, be sure to reset the T8OIF flag before the compare match interrupt is enabled using T8OIE (D0/T8OSC1_IMSK register). EPSON 14-14 S1C17704 TECHNICAL MANUAL...

  • Page 207: Precautions

    To obtain the counter value, read the counter data register after stopping the counter. Or read the counter value twice to determine that both read results are the same and that the read value is significant. EPSON S1C17704 TECHNICAL MANUAL 14-15...
  • Page 208 14 8-BIT OSC1 TIMER (T8OSC1) THIS PAGE IS BLANK. EPSON 14-16 S1C17704 TECHNICAL MANUAL...

  • Page 209: Clock Timer (Ct)

    15.1 Outline of the Clock Timer The S1C17704 incorporates one channel of clock timer that uses OSC1 as its clock source. The clock timer contains an 8-bit binary counter that operates with a divided OSC1 clock (256 Hz signal). The counter data bits (128 to 1 Hz) can be read with software.

  • Page 210: Operating Clock

    The OSC module does not provide a control bit for the 256 Hz clock. The 256 Hz clock is always supplied to the clock timer when the OSC1 oscillator is on. For control of the OSC1 oscillator, see Chapter 7, “Oscillator (OSC).” EPSON 15-2 S1C17704 TECHNICAL MANUAL...

  • Page 211: Resetting The Clock Timer

    To reset the clock timer, write 1 to the CTRST bit (D4/CT_CTL register). This initializes the counter to 0. ∗ CTRST: Clock Timer Reset Bit in the Clock Timer Control (CT_CTL) Register (D4/0x5000) The counter is also initialized to 0 at initial reset. EPSON S1C17704 TECHNICAL MANUAL 15-3...

  • Page 212: Clock Timer Run/Stop Control

    The CTRUN maintains 1 for reading until the timer actually enters Stop status. Figure 15.4.2 shows the timer operation at start/stop. 256 Hz CTRUN(RD) CTRUN(WR) CT_CNT register 0x57 0x58 0x59 0x5a 0x5b 0x5c Figure 15.4.2 Clock Timer Start/Stop Operation EPSON 15-4 S1C17704 TECHNICAL MANUAL...

  • Page 213: Clock Timer Interrupt

    ∗ EILV3[2:0]: CT Interrupt Level Bits in the External Interrupt Level Setup (ITC_ELV1) Register 1 (D[10:8]/0x4308) Interrupt trigger mode select bit in the ITC (fixed at 1) ∗ EITG3: CT Interrupt Trigger Mode Select Bit in the External Interrupt Level Setup (ITC_ELV1) Register 1 (D12/0x4308) EPSON S1C17704 TECHNICAL MANUAL 15-5...
  • Page 214 2. After an interrupt occurs, reset the CTIF∗ interrupt flag of the CT module in the interrupt handler routine (this also resets the interrupt flag in the ITC). Interrupt vector The following shows the vector number and vector address for the clock timer interrupt: Vector number: 7 (0x07) Vector address: 0x801c EPSON 15-6 S1C17704 TECHNICAL MANUAL...

  • Page 215: Details Of Control Registers

    Indicates/resets interrupt occurrence status. The following describes each clock timer register. These are all 8-bit registers. Note: When setting the registers, be sure to write a 0, and not a 1, for all “reserved bits.” EPSON S1C17704 TECHNICAL MANUAL 15-7...

  • Page 216: 0X5000: Clock Timer Control Register (Ct_Ctl)

    0 (R/W): Stop (default) The clock timer starts counting by writing 1 to CTRUN and stops by writing 0. In Stop state, the counter data is retained until the timer is reset or placed in a Run state. EPSON 15-8 S1C17704 TECHNICAL MANUAL...

  • Page 217: 0X5001: Clock Timer Counter Register (Ct_Cnt)

    The counter value should be obtained by one of the following procedures: • Read the counter value after stopping the counter. • Read the counter value twice to determine that both read results are the same and that the read value is significant. EPSON S1C17704 TECHNICAL MANUAL 15-9...

  • Page 218: 0X5002: Clock Timer Interrupt Mask Register (Ct_Imsk)

    CTIE2: 2 Hz Interrupt Enable Bit Enables/disables the 2 Hz interrupt. 1 (R/W): Enable interrupt 0 (R/W): Disable interrupt (default) CTIE1: 1 Hz Interrupt Enable Bit Enables/disables the 1 Hz interrupt. 1 (R/W): Enable interrupt 0 (R/W): Disable interrupt (default) EPSON 15-10 S1C17704 TECHNICAL MANUAL...

  • Page 219: 0X5003: Clock Timer Interrupt Flag Register (Ct_Iflg)

    No cause of interrupt has occurred (default) 1 (W): Flag is reset 0 (W): Has no effect CTIF1 is set to 1 at the falling edge of the 1 Hz signal only when CTIE1 (D0/CT_IMSK register) has been set to 1. EPSON S1C17704 TECHNICAL MANUAL 15-11...

  • Page 220: Precautions

    To obtain the counter value, read the counter register after stopping the counter. Or read the counter value twice to determine that both read results are the same and that the read value is significant. EPSON 15-12 S1C17704 TECHNICAL MANUAL...

  • Page 221: Stopwatch Timer (Swt)

    16.1 Outline of the Stopwatch Timer The S1C17704 incorporates a stopwatch timer that counts 1/100 and 1/10 seconds. The stopwatch timer consists of two 4-bit BCD counters (for 1/100 and 1/10 seconds) that operate with a divided OSC1 clock (256 Hz signal). The counter data can be read with software.

  • Page 222: Bcd Counters

    The 1/10-second counter counts the approximate 10 Hz signal output by the 1/100-second counter in 4:6 ratios to generate a 1 Hz signal. The counter counts up in 25/256-second and 26/256-second intervals, therefore the count cycle is an approximate 1/10 seconds. EPSON 16-2 S1C17704 TECHNICAL MANUAL...

  • Page 223: Operating Clock

    The OSC module does not provide a control bit for the 256 Hz clock. The 256 Hz clock is always supplied to the stopwatch timer when the OSC1 oscillator is on. For control of the OSC1 oscillator, see Chapter 7, “Oscillator (OSC).” EPSON S1C17704 TECHNICAL MANUAL 16-3...

  • Page 224: Resetting The Stopwatch Timer

    To reset the stopwatch timer, write 1 to the SWTRST bit (D4/SWT_CTL register). This initializes the counter to 0. ∗ SWTRST: Stopwatch Timer Reset Bit in the Stopwatch Timer Control (SWT_CTL) Register (D4/0x5020) The counter is also initialized to 0 at initial reset. EPSON 16-4 S1C17704 TECHNICAL MANUAL...

  • Page 225: Stopwatch Timer Run/Stop Control

    The SWTRUN maintains 1 for reading until the timer actually enters Stop status. Figure 16.5.2 shows the timer operation at start/stop. 256 Hz SWTRUN(RD) SWTRUN(WR) SWT_BCNT register Figure 16.5.2 Stopwatch Timer Start/Stop Operation EPSON S1C17704 TECHNICAL MANUAL 16-5...

  • Page 226: Stopwatch Timer Interrupt

    ∗ EILV2[2:0]: SWT Interrupt Level Bits in the External Interrupt Level Setup (ITC_ELV1) Register 1 (D[2:0]/0x4308) Interrupt trigger mode select bit in the ITC (fixed at 1) ∗ EITG2: SWT Interrupt Trigger Mode Select Bit in the External Interrupt Level Setup (ITC_ELV1) Register 1 (D4/0x4308) EPSON 16-6 S1C17704 TECHNICAL MANUAL...
  • Page 227 2. After an interrupt occurs, reset the SIF∗ interrupt flag of the SWT module in the interrupt handler routine (this also resets the interrupt flag in the ITC). Interrupt vector The following shows the vector number and vector address for the stopwatch timer interrupt: Vector number: 6 (0x06) Vector address: 0x8018 EPSON S1C17704 TECHNICAL MANUAL 16-7...

  • Page 228: Details Of Control Registers

    Indicates/resets interrupt occurrence status. The following describes each stopwatch timer register. These are all 8-bit registers. Note: When setting the registers, be sure to write a 0, and not a 1, for all “reserved bits.” EPSON 16-8 S1C17704 TECHNICAL MANUAL...

  • Page 229: 0X5020: Stopwatch Timer Control Register (Swt_Ctl)

    0 (R/W): Stop (default) The stopwatch timer starts counting by writing 1 to SWTRUN and stops by writing 0. In Stop state, the counter data is retained until the timer is reset or placed in a Run state. EPSON S1C17704 TECHNICAL MANUAL 16-9...

  • Page 230: 0X5021: Stopwatch Timer Bcd Counter Register (Swt_Bcnt)

    The counter value should be obtained by one of the following procedures: • Read the counter value after stopping the counter. • Read the counter value twice to determine that both read results are the same and that the read value is significant. EPSON 16-10 S1C17704 TECHNICAL MANUAL...

  • Page 231: 0X5022: Stopwatch Timer Interrupt Mask Register (Swt_Imsk)

    SIE10: 10 Hz Interrupt Enable Bit Enables/disables the 10 Hz interrupt. 1 (R/W): Enable interrupt 0 (R/W): Disable interrupt (default) SIE100: 100 Hz Interrupt Enable Bit Enables/disables the 100 Hz interrupt. 1 (R/W): Enable interrupt 0 (R/W): Disable interrupt (default) EPSON S1C17704 TECHNICAL MANUAL 16-11...

  • Page 232: 0X5023: Stopwatch Timer Interrupt Flag Register (Swt_Iflg)

    No cause of interrupt has occurred (default) 1 (W): Flag is reset 0 (W): Has no effect SIF100 is set to 1 at the falling edge of the 100 Hz signal only when SIE100 (D0/SWT_IMSK register) has been set to 1. EPSON 16-12 S1C17704 TECHNICAL MANUAL...

  • Page 233: Precautions

    To obtain the counter value, read the counter register after stopping the counter. Or read the counter value twice to determine that both read results are the same and that the read value is significant. EPSON S1C17704 TECHNICAL MANUAL 16-13...
  • Page 234 16 STOPWATCH TIMER (SWT) THIS PAGE IS BLANK. EPSON 16-14 S1C17704 TECHNICAL MANUAL...

  • Page 235: Watchdog Timer (Wdt)

    17 Watchdog Timer (WDT) 17.1 Outline of the Watchdog Timer The S1C17704 is equipped with a watchdog timer driven by OSC1 as the clock source. If the watchdog timer is not reset for more than 131072/f seconds (4 seconds when f = 32.768 kHz), an NMI or a reset signal (selectable...

  • Page 236: Operating Clock

    The OSC module does not provide a control bit for the 256 Hz clock. The 256 Hz clock is always supplied to the watchdog timer when the OSC1 oscillator is on. For control of the OSC1 oscillator, see Chapter 7, “Oscillator (OSC).” EPSON 17-2 S1C17704 TECHNICAL MANUAL...

  • Page 237: Controlling The Watchdog Timer

    To prevent an unnecessary NMI or reset signal from being generated after canceling SLEEP mode, be sure to reset the watchdog timer before executing the slp instruction. Moreover, stop the watchdog timer by setting WDTRUN[3:0] as required. EPSON S1C17704 TECHNICAL MANUAL 17-3...

  • Page 238: Details Of Control Registers

    Sets the timer mode and indicates NMI status. The following describes each watchdog timer register. These are all 8-bit registers. Note: When setting the registers, be sure to write a 0, and not a 1, for all “reserved bits.” EPSON 17-4 S1C17704 TECHNICAL MANUAL...

  • Page 239: 0X5040: Watchdog Timer Control Register (Wdt_Ctl)

    WDTRUN[3:0]: Watchdog Timer Run/Stop Control Bits Starts/stops the watchdog timer. Other than 0b1010 (R/W): Run 0b1010 (R/W): Stop (default) Reset the watchdog timer before starting, thus preventing the generation of unnecessary NMI or reset signals. EPSON S1C17704 TECHNICAL MANUAL 17-5...

  • Page 240: 0X5041: Watchdog Timer Status Register (Wdt_St)

    This bit is also set due to a counter overflow even if reset output is selected, however, the bit is cleared at initial reset and cannot be checked if it has been set to 1. EPSON 17-6 S1C17704 TECHNICAL MANUAL...

  • Page 241: Precautions

    • When the watchdog timer is used, it must be reset within 131072/f second cycle (4 seconds when f OSC1 OSC1 32.768 kHz). • Reset the watchdog timer before starting, thus preventing the generation of unnecessary NMI or reset signals. EPSON S1C17704 TECHNICAL MANUAL 17-7...
  • Page 242 17 WATCHDOG TIMER (WDT) THIS PAGE IS BLANK. EPSON 17-8 S1C17704 TECHNICAL MANUAL...

  • Page 243: Uart

    18.1 Outline of the UART The S1C17704 equipped with one channel of UART. The UART performs asynchronous data transfer from/to an external serial device in a 150 to 115200 bps transfer rate. The UART contains two-byte receive data buffer and one-byte transmit data buffer allowing full-duplex communication.

  • Page 244: Uart Pins

    P25 → SCLK (required only when an external clock is used) ∗ P25MUX: P25 Port Function Select Bit in the P2 Port Function Select (P2_PMUX) Register (D5/0x52a2) For details on switching pin function, see Section 10.2, “Selecting I/O Pin Functions (Port MUX).” EPSON 18-2 S1C17704 TECHNICAL MANUAL...

  • Page 245: Transfer Clock

    Make sure of the division ratio when setting a transfer rate. • The frequency of the external clock input from the SCLK pin must be half of PCLK or lower and the clock duty ratio must be 50%. EPSON S1C17704 TECHNICAL MANUAL 18-3...

  • Page 246: Setting Transfer Data Conditions

    CHLN = 1, PREN = 1, STPB = 0 CHLN = 1, PREN = 0, STPB = 1 CHLN = 1, PREN = 1, STPB = 1 s1: start bit, s2 & s3: stop bit, p: parity bit Figure 18.4.1 Transfer Data Format EPSON 18-4 S1C17704 TECHNICAL MANUAL...

  • Page 247: Data Transmit/Receive Control

    S1 D0 D1 D2 D3 D4 D5 D6 D7 P S2 S1 D0 D1 D7 P S2 S1 D0 D1 D7 P TDBE TRBS Interrupt S1: Start bit, S2: Stop bit, P: Parity bit, Wr: Data write to transmit data buffer Figure 18.5.1 Data Transmit Timing Chart EPSON S1C17704 TECHNICAL MANUAL 18-5...
  • Page 248 ∗ RBFI: Receive Buffer Full Interrupt Condition Setup Bit in the UART Control (UART_CTL) Register (D1/0x4104) In addition to the flags above, three receive error flags are provided. Refer to Section 18.6 for these flags and details of receive errors. EPSON 18-6 S1C17704 TECHNICAL MANUAL...
  • Page 249 When the RXEN bit is set to 0, the transmit and receive data buffers are placed in empty status (data is cleared if any remains). Furthermore, the data being transferred cannot be guaranteed if RXEN is set to 0 during transmitting/receiving. EPSON S1C17704 TECHNICAL MANUAL 18-7...

  • Page 250: Receive Errors

    When an overrun error occurs, the overrun error flag OER (D4/UART_ST register) is set to 1. Even when this error occurs, the receive operation is continued. The OER flag (D4/UART_ST register) is reset to 0 by writing 1. ∗ OER: Overrun Error Flag in the UART Status (UART_ST) Register (D4/0x4100) EPSON 18-8 S1C17704 TECHNICAL MANUAL...

  • Page 251: Uart Interrupt

    The UART interrupt handler routine should read the RDRY and RD2B flags to check if the interrupt has occurred due to a receive buffer full or another cause. When RDRY or RD2B = 1, the UART interrupt handler routine can read the received data from the receive data buffer. EPSON S1C17704 TECHNICAL MANUAL 18-9...
  • Page 252 For details on these interrupt control registers, as well as the device operation when an interrupt has occurred, see Chapter 6, “Interrupt Controller (ITC).” Interrupt vector The following shows the vector number and vector address for the UART interrupt: Vector number: 16 (0x10) Vector address: 0x8040 EPSON 18-10 S1C17704 TECHNICAL MANUAL...

  • Page 253: Irda Interface

    To use the IrDA interface function, set the IRMD bit (D0/UART_EXP register) to 1. This enables the RZI modulator/demodulator. ∗ IRMD: IrDA Mode Select Bit in the UART Expansion (UART_EXP) Register (D0/0x4105) Note: This setting must be performed before setting other UART conditions. EPSON S1C17704 TECHNICAL MANUAL 18-11...
  • Page 254 The control method to transmit/receive data in IrDA mode is the same as that of the normal interface. See previous sections for details on how to set and control the data formats, data transfers, and interrupts. EPSON 18-12 S1C17704 TECHNICAL MANUAL...

  • Page 255: Details Of Control Registers

    UART Expansion Register Sets IrDA mode. The following describes each UART register. These are all 8-bit registers. Note: When setting the registers, be sure to write a 0, and not a 1, for all “reserved bits.” EPSON S1C17704 TECHNICAL MANUAL 18-13...

  • Page 256: 0X4100: Uart Status Register (Uart_St)

    Second entry is empty (default) RD2B is set to 1 when the second data is loaded to the receive data buffer, and is reset to 0 when the first data is read out from the receive data buffer. EPSON 18-14 S1C17704 TECHNICAL MANUAL...
  • Page 257 0 (R): Not empty TDBE is reset to 0 when transmit data is written to the transmit data buffer and set to 1 when the transmit data in the buffer is transferred to the shift register. EPSON S1C17704 TECHNICAL MANUAL 18-15...

  • Page 258: 0X4101: Uart Transmit Data Register (Uart_Txd)

    The serial-converted data is output from the SOUT pin beginning with the LSB, in which the bits set to 1 are output as high-level signals and those set to 0 output as low-level signals. This register can be read as well as written. EPSON 18-16 S1C17704 TECHNICAL MANUAL...

  • Page 259: 0X4102: Uart Receive Data Register (Uart_Rxd)

    1s and the low-level signals changed to 0s. The resulting data is stored in the receive data buffer. This register is a read-only register, so no data can be written to it. (Default: 0x0) EPSON S1C17704 TECHNICAL MANUAL 18-17...

  • Page 260: 0X4103: Uart Mode Register (Uart_Mod)

    This bit is used to select the clock source between the internal clock (8-bit timer output clock) and an external clock (input from the SCLK pin). An external clock is selected by writing 1 to this bit, and an internal clock is selected by writing 0. EPSON 18-18 S1C17704 TECHNICAL MANUAL...

  • Page 261: 0X4104: Uart Control Register (Uart_Ctl)

    Before the UART can transmit/receive data, RXEN must be set to 1. When RXEN is set to 0, data transmission/reception is disabled. Always make sure RXEN = 0 before setting the transfer conditions. Writing 0 to RXEN also clears the transmit/receive data buffers. EPSON S1C17704 TECHNICAL MANUAL 18-19...

  • Page 262: X4105: Uart Expansion Register (Uart_Exp)

    Turns the IrDA interface function on and off. 1 (R/W): On 0 (R/W): Off (default) Set this bit to 1 when using the IrDA interface. When set to 0, the module functions as a standard UART without IrDA. EPSON 18-20 S1C17704 TECHNICAL MANUAL...

  • Page 263: Precautions

    Select an appropriate prescaler output clock as the IrDA receive detection clock so that it will be able to detect a minimum 1.41 µs width of an input pulse. EPSON S1C17704 TECHNICAL MANUAL 18-21...
  • Page 264 18 UART THIS PAGE IS BLANK. EPSON 18-22 S1C17704 TECHNICAL MANUAL...

  • Page 265: Spi

    19 SPI 19.1 Configuration of the SPI The S1C17704 equipped with a synchronous serial interface module (hereafter SPI). The SPI module supports both master and slave modes and performs 8-bit serial data transfer. Data transfer timing (clock phase and polarity variations) is selectable from among 4 types.

  • Page 266: Spi I/O Pins

    ∗ P22MUX: P22 Port Function Select Bit in the P2 Port Function Select (P2_PMUX) Register (D2/0x52a2) P17 → #SPISS ∗ P17MUX: P17 Port Function Select Bit in the P1 Port Function Select (P1_PMUX) Register (D7/0x52a1) For details on switching pin function, see Section 10.2, “Selecting I/O Pin Functions (Port MUX).” EPSON 19-2 S1C17704 TECHNICAL MANUAL...

  • Page 267: Spi Clock

    Note: The frequency of the clock input from the SPICLK pin must be 1/3 of PCLK or lower and the clock duty ratio must be 50%. PCLK SPICLK input Differentiated SPICLK SPI clock (internally used) Figure 19.3.2 SPI Clock in Slave Mode EPSON S1C17704 TECHNICAL MANUAL 19-3...

  • Page 268: Setting The Data Transfer Conditions

    SPICLK (CPOL = 1, CPHA = 0) SPICLK (CPOL = 0, CPHA = 1) SPICLK (CPOL = 0, CPHA = 0) SDI/SDO D7 (MSB) D0 (LSB) Fetching receive data into shift register Figure 19.4.1 Clock and Data Transfer Timing EPSON 19-4 S1C17704 TECHNICAL MANUAL...

  • Page 269: Data Transmit/Receive Control

    In slave mode, the SPBSY flag indicates the SPI slave select signal (#SPISS pin) status; it goes 1 when this SPI module is selected as a slave or goes 0 when this SPI module is deselected. EPSON S1C17704 TECHNICAL MANUAL 19-5...
  • Page 270 In master mode, the SPBSY flag that indicates the shift register status can be used as in data transmission. EPSON 19-6 S1C17704 TECHNICAL MANUAL...
  • Page 271 When the SPEN bit is set to 0, the transmit and receive data buffers are placed in empty status (data is cleared if any remains). Furthermore, the data being transferred cannot be guaranteed if SPEN is set to 0 during transmitting/receiving. EPSON S1C17704 TECHNICAL MANUAL 19-7...

  • Page 272: Spi Interrupt

    The IIFT6 flag is always set to 1 by the SPI interrupt request pulse, regardless of how the IIEN6 bit is set (even when set to 0). The interrupt level setup bits IILV6[2:0] set the interrupt level (0 to 7) of the SPI interrupt. EPSON 19-8 S1C17704 TECHNICAL MANUAL...
  • Page 273 For details on these interrupt control registers, as well as the device operation when an interrupt has occurred, see Chapter 6, “Interrupt Controller (ITC).” Interrupt vector The following shows the vector number and vector address for the SPI interrupt: Vector number: 18 (0x12) Vector address: 0x8048 EPSON S1C17704 TECHNICAL MANUAL 19-9...

  • Page 274: Details Of Control Registers

    Notes: • When setting the registers, be sure to write a 0, and not a 1, for all “reserved bits.” • Be sure to use 16-bit access instructions for reading/writing from/to the SPI registers. The SPI registers do not allow reading/writing using 32-bit and 8-bit access instructions. EPSON 19-10 S1C17704 TECHNICAL MANUAL...

  • Page 275: 0X4320: Spi Status Register (Spi_St)

    SPTBE is reset to 0 when transmit data is written to the SPI_TXD register (transmit data buffer, 0x4322) and is set to 1 when the written data is transferred to the shift register (transmit operation started). Transmit data should be written to the SPI_TXD register when this bit = 1. EPSON S1C17704 TECHNICAL MANUAL 19-11...

  • Page 276: 0X4322: Spi Transmit Data Register (Spi_Txd)

    SPI is sending data. The serial-converted data is output from the SDO pin beginning with the MSB, in which the bits set to 1 are output as high-level signals and those set to 0 output as low-level signals. EPSON 19-12 S1C17704 TECHNICAL MANUAL...

  • Page 277: 0X4324: Spi Receive Data Register (Spi_Rxd)

    The serial data input from the SDI pin is converted into parallel data beginning with the MSB, with the high-level signals changed to 1s and the low-level signals changed to 0s. The resulting data is stored in this register. SPI_RXD is a read-only register, so no data can be written to it. EPSON S1C17704 TECHNICAL MANUAL 19-13...

  • Page 278: 0X4326: Spi Control Register (Spi_Ctl)

    SPICLK (CPOL = 1, CPHA = 0) SPICLK (CPOL = 0, CPHA = 1) SPICLK (CPOL = 0, CPHA = 0) SDI/SDO D7 (MSB) D0 (LSB) Fetching receive data into shift register Figure 19.7.1 Clock and Data Transfer Timing EPSON 19-14 S1C17704 TECHNICAL MANUAL...
  • Page 279 When SPEN is set to 1, the SPI module is activated and data transfer is enabled. When SPEN is set to 0, the SPI module goes off. Note: Make sure that the SPEN bit is 0 before setting the CPHA, CPOL, and MSSL bits. EPSON S1C17704 TECHNICAL MANUAL 19-15...

  • Page 280: Precautions

    SPI registers do not allow reading/writing using 32-bit and 8-bit access instructions. • Do not access the SPI_CTL register (0x4326), while the SPBSY flag (D2/SPI_ST register) is set to 1 (during data transfer). ∗ SPBSY: Transfer Busy Flag in the SPI Status (SPI_ST) Register (D2/0x4320) EPSON 19-16 S1C17704 TECHNICAL MANUAL...

  • Page 281: Configuration Of The I C

    20 I 20.1 Configuration of the I The S1C17704 equipped with an I C bus interface module for high-speed synchronous serial communication. This C module operates as a master using the clock supplied from the 16-bit timer Ch.2 (supports single master mode only).

  • Page 282: I 2 C I/O Pins

    ∗ P14MUX: P14 Port Function Select Bit in the P1 Port Function Select (P1_PMUX) Register (D4/0x52a1) P15 → SCL ∗ P15MUX: P15 Port Function Select Bit in the P1 Port Function Select (P1_PMUX) Register (D5/0x52a1) For details on switching pin function, see Section 10.2, “Selecting I/O Pin Functions (Port MUX).” EPSON 20-2 S1C17704 TECHNICAL MANUAL...

  • Page 283: I 2 C Clock

    The I C module does not function as a slave device. The SCL input is used to check the SCL status of the I C bus but it is not used to input synchronous clock. EPSON S1C17704 TECHNICAL MANUAL 20-3...

  • Page 284: Setting Before Starting Data Transfer

    C clock (16-bit timer Ch.2 output clock) frequency must be a 1/6 of PCLK or lower to use the noise remove function. ∗ NSERM: Noise Remove On/Off Bit in the I C Control (I2C_CTL) Register (D4/0x4342) EPSON 20-4 S1C17704 TECHNICAL MANUAL...

  • Page 285: Data Transmit/Receive Control

    8-bit transmit/receive data register. So one 7-bit slave address can be sent at a time. A 10-bit address should be sent in two parts with software control. Figure 20.5.2 shows the address data format. EPSON S1C17704 TECHNICAL MANUAL 20-5...
  • Page 286 SDA line is not pulled down. The I C module regards this status as a NACK (1) returned (transmission fails). SDA (output) SDA (input) NACK SCL (output) START condition Figure 20.5.3 ACK and NACK EPSON 20-6 S1C17704 TECHNICAL MANUAL...
  • Page 287 SDA (output) SCL (output) STOP condition Figure 20.5.4 STOP Condition Set the STP bit (D1/I2C_CTL register) to 1 to generate a STOP condition. ∗ STP: Stop Control Bit in the I C Control (I2C_CTL) Register (D1/0x4342) EPSON S1C17704 TECHNICAL MANUAL 20-7...
  • Page 288 RBUSY RBRDY RTACK (ACK received) Shift register valid shift shift shift shift shift shift shift valid shift RTDT[7:0] A[6:0] + DIR D[7:0] Interrupt C Timing Chart 1 (START condition → data transmission) Figure 20.5.5 I EPSON 20-8 S1C17704 TECHNICAL MANUAL...
  • Page 289 TBUSY RBUSY RBRDY RTACK (ACK received) Shift register valid shift shift shift shift shift shift shift shift shift RTDT[7:0] A[6:0] + DIR Interrupt C Timing Chart 3 (START condition → data reception) Figure 20.5.7 I EPSON S1C17704 TECHNICAL MANUAL 20-9...
  • Page 290 TXE = 0 RXE = 0 TBUSY RBUSY RBRDY RTACK (ACK received) Shift register valid shift shift shift valid shift shift RTDT[7:0] A[6:0] + DIR D[7:0] Interrupt Figure 20.5.9 I C Timing Chart 5 (wait state) EPSON 20-10 S1C17704 TECHNICAL MANUAL...

  • Page 291: I 2 C Interrupt

    C interrupt request pulse, regardless of how the IIEN7 bit is set (even when set to 0). The interrupt level setup bits IILV7[2:0] set the interrupt level (0 to 7) of the I C interrupt. EPSON S1C17704 TECHNICAL MANUAL 20-11...
  • Page 292 For details on these interrupt control registers, as well as the device operation when an interrupt has occurred, see Chapter 6, “Interrupt Controller (ITC).” Interrupt vector The following shows the vector number and vector address for the I C interrupt: Vector number: 19 (0x13) Vector address: 0x804c EPSON 20-12 S1C17704 TECHNICAL MANUAL...

  • Page 293: Details Of Control Registers

    Notes: • When setting the registers, be sure to write a 0, and not a 1, for all “reserved bits.” • Be sure to use 16-bit access instructions for reading/writing from/to the I C registers. The I registers do not allow reading/writing using 32-bit and 8-bit access instructions. EPSON S1C17704 TECHNICAL MANUAL 20-13...

  • Page 294: 0X4340: I 2 C Enable Register (I2C_En)

    1 (R/W): Enable 0 (R/W): Disable (default) When I2CEN is set to 1, the I C module is activated and data transfer is enabled. When I2CEN is set to 0, the I C module goes off. EPSON 20-14 S1C17704 TECHNICAL MANUAL...

  • Page 295: 0X4342: I 2 C Control Register (I2C_Ctl)

    C is operating (TBUSY = 1 or RBUSY = 1). A STOP condition will be generated upon completion of data transmission/reception (including an ACK transfer). STP is automatically reset to 0 after a STOP condition has been generated. EPSON S1C17704 TECHNICAL MANUAL 20-15...
  • Page 296 1. Set the slave address to RTDT[7:0] (D[7:0]/I2C_DAT register). (First transmit data when 10-bit address is used; see Figure 20.5.2.) 2. Set TXE (D9/I2C_DAT register) to 1. 3. Set STRT (D0/I2C_CTL register) to 1. STRT is automatically reset to 0, after a START condition has been generated. EPSON 20-16 S1C17704 TECHNICAL MANUAL...

  • Page 297: 0X4344: I 2 C Data Register (I2C_Dat)

    1 (R/W): Error (NACK) 0 (R/W): ACK (default) To return ACK to the slave after data is received, set RTACK to 0 before the I C module sends the acknowledge bit. To return NACK, set RTACK to 1. EPSON S1C17704 TECHNICAL MANUAL 20-17...
  • Page 298 The serial data input from the SDA pin is converted into parallel data beginning with the MSB, with the high-level signals changed to 1s and the low-level signals changed to 0s. The resulting data is stored in this register. EPSON 20-18 S1C17704 TECHNICAL MANUAL...

  • Page 299: 0X4346: I 2 C Interrupt Control Register (I2C_Ictl)

    RTDT[7:0] (D[7:0]/I2C_DAT register) is transferred to the shift register. When TINTE is set to 0, an I C transmit buffer empty interrupt is not generated. EPSON S1C17704 TECHNICAL MANUAL 20-19...
  • Page 300 20 I THIS PAGE IS BLANK. EPSON 20-20 S1C17704 TECHNICAL MANUAL...

  • Page 301: Remote Controller (Remc)

    21 Remote Controller (REMC) 21.1 Outline of the REMC The S1C17704 is equipped with a remote controller (REMC) module for generating/receiving infrared remote control signals. The REMC module consists of a carrier generator for generating a carrier signal using a prescaler...

  • Page 302: Remc I/O Pins

    ∗ P04MUX: P04 Port Function Select Bit in the P0 Port Function Select (P0_PMUX) Register (D4/0x52a0) P05 → REMO ∗ P05MUX: P05 Port Function Select Bit in the P0 Port Function Select (P0_PMUX) Register (D5/0x52a0) For details on switching pin function, see Section 10.2, “Selecting I/O Pin Functions (Port MUX).” EPSON 21-2 S1C17704 TECHNICAL MANUAL...

  • Page 303: Carrier Generator

    The carrier signal is generated according to these settings as shown in Figure 21.3.1. Example: CGCLK[3:0] = 0x2 (PCLK•1/4), REMCH[5:0] = 2, REMCL[5:0] = 1 PCLK PSC output clock Count Carrier H carrier length L carrier length Figure 21.3.1 Carrier Signal Generation EPSON S1C17704 TECHNICAL MANUAL 21-3...

  • Page 304: Setting Clock For Data Length Counter

    PCLK•1/16 PCLK•1/2048 PCLK•1/8 PCLK•1/1024 PCLK•1/4 PCLK•1/512 PCLK•1/2 PCLK•1/256 PCLK•1/1 (Default: 0x0) The data length counter can count up to 256. Select a count clock so that the data length can be counted within this range. EPSON 21-4 S1C17704 TECHNICAL MANUAL...

  • Page 305: Controlling Data Transmission/Reception

    Write the value equivalent to the pulse width (high period or low period) of the transmit data to REMLEN[7:0] (D[7:0]/REMC_LCNT register) to set it to the data length counter. ∗ REMLEN[7:0]: Transmit/Receive Data Length Count Bits in the REMC Length Counter (REMC_LCNT) Register (D[7:0]/0x5345) EPSON S1C17704 TECHNICAL MANUAL 21-5...
  • Page 306 Note that a signal transition is regarded as noise if the signal level after the input changes is not sampled for two or more sampling clock cycles. In this case no rising edge or falling edge interrupt occurs. EPSON 21-6 S1C17704 TECHNICAL MANUAL...
  • Page 307 A data length counter underflow interrupt occurs even in data reception, use it for a terminate/error processing. (4) Terminating data reception After the last data transfer has finished, write 0 to the REMEN bit to terminate data reception. EPSON S1C17704 TECHNICAL MANUAL 21-7...

  • Page 308: Remc Interrupt

    Furthermore, the interrupt handler routine must reset (write 1 to) REMRIF in the REMC module as well as the REMC interrupt flag in the ITC, to clear the cause of interrupt. EPSON 21-8 S1C17704 TECHNICAL MANUAL...
  • Page 309 For details on these interrupt control registers, as well as the device operation when an interrupt has occurred, see Chapter 6, “Interrupt Controller (ITC).” Interrupt vector The following shows the vector number and vector address for the REMC interrupt: Vector number: 17 (0x11) Vector address: 0x8044 EPSON S1C17704 TECHNICAL MANUAL 21-9...

  • Page 310: Details Of Control Registers

    REMC Interrupt Flag Register Indicates/resets interrupt occurrence status. The following describes each REMC register. These are all 8-bit registers. Note: When setting the registers, be sure to write a 0, and not a 1, for all “reserved bits.” EPSON 21-10 S1C17704 TECHNICAL MANUAL...

  • Page 311: 0X5340: Remc Configuration Register (Remc_Cfg)

    0(R/W): Disable (default) When REMEN is set to 1, the REMC module starts data transmission or data reception according to the REMMD (D1) setting. When REMEN is set to 0, the REMC module stops operating. EPSON S1C17704 TECHNICAL MANUAL 21-11...

  • Page 312: X5341: Remc Prescaler Clock Select Register (Remc_Psc)

    Prescaler output clock Reserved PCLK•1/128 PCLK•1/16384 PCLK•1/64 PCLK•1/8192 PCLK•1/32 PCLK•1/4096 PCLK•1/16 PCLK•1/2048 PCLK•1/8 PCLK•1/1024 PCLK•1/4 PCLK•1/512 PCLK•1/2 PCLK•1/256 PCLK•1/1 (Default: 0x0) Note: When setting the clocks, make sure the REMC module is idle (REMEN/REMC_CFG register = 0). EPSON 21-12 S1C17704 TECHNICAL MANUAL...

  • Page 313: 0X5342: Remc H Carrier Length Setup Register (Remc_Carh)

    The carrier signal is generated according to these settings as shown in Figure 21.7.1. Example: CGCLK[3:0] = 0x2 (PCLK•1/4), REMCH[5:0] = 2, REMCL[5:0] = 1 PCLK PSC output clock Count Carrier H carrier length L carrier length Figure 21.7.1 Carrier Signal Generation EPSON S1C17704 TECHNICAL MANUAL 21-13...

  • Page 314: 0X5343: Remc L Carrier Length Setup Register (Remc_Carl)

    REMCL: L carrier length register data clk_in: Prescaler output clock frequency The H period length is specified with REMCH[5:0] (D[5:0]/REMC_CARH register). The carrier signal is generated according to these settings as shown in Figure 21.7.1. EPSON 21-14 S1C17704 TECHNICAL MANUAL...

  • Page 315: 0X5344: Remc Status Register (Remc_St)

    When REMEN (D0/REMC_CFG register) is set to 1, the REMC module modulates the REMDT set value with the carrier signal and outputs the modulated signal from the REMO pin during data transmission. During data reception, the signal level of the input data pulse is set to this bit. EPSON S1C17704 TECHNICAL MANUAL 21-15...

  • Page 316: 0X5345: Remc Length Counter Register (Remc_Lcnt)

    Use an input transition interrupt to set the data length counter to 0xff and read the counter value when the next interrupt caused by an input transition occurs. The input data pulse width can be obtained from the difference between 0xff and the read value. EPSON 21-16 S1C17704 TECHNICAL MANUAL...

  • Page 317: 0X5346: Remc Interrupt Mask Register (Remc_Imsk)

    Enables or disables the interrupt by detecting the rising edge of the input signal. 1 (R/W): Enable interrupt 0 (R/W): Disable interrupt (default) REMUIE: Underflow Interrupt Enable Bit Enables or disables the interrupt by a data length counter underflow. 1 (R/W): Enable interrupt 0 (R/W): Disable interrupt (default) EPSON S1C17704 TECHNICAL MANUAL 21-17...

  • Page 318: 0X5347: Remc Interrupt Flag Register (Remc_Iflg)

    No cause of interrupt has occurred (default) 1 (W): Flag is reset 0 (W): Has no effect REMUIF is set to 1 when the data length counter underflows only when REMUIE (D0/REMC_IMSK register) is set to 1. EPSON 21-18 S1C17704 TECHNICAL MANUAL...

  • Page 319: Precaution

    21 REMOTE CONTROLLER (REMC) 21.8 Precaution Before the REMC module can start operating, the prescaler must be run. EPSON S1C17704 TECHNICAL MANUAL 21-19...
  • Page 320 21 REMOTE CONTROLLER (REMC) THIS PAGE IS BLANK. EPSON 21-20 S1C17704 TECHNICAL MANUAL...

  • Page 321: Lcd Driver (Lcd)

    22 LCD Driver (LCD) 22.1 Configuration of LCD Driver The S1C17704 is equipped with an LCD driver which can drive an LCD panel with a maximum of 1,792 pixels (56 segments × 32 commons). Figure 22.1.1 shows the configuration of the LCD driver and the drive power supply.

  • Page 322: Lcd Power Supply

    22 LCD DRIVER (LCD) 22.2 LCD Power Supply The S1C17704 generates the LCD drive voltages V to V using the on-chip LCD system voltage regulator and power voltage booster. It is not necessary to supply external voltage. For details of the LCD power supply, see Chapter 4, “Power Supply.”...

  • Page 323: Lcd Clock

    When OSC1 (32.768 kHz typ.) is selected as the clock source Frame frequency = 64 Hz (typ.) When OSC3 is selected as the clock source OSC3 Frame frequency = ———— × LCKDV [Hz] OSC3 clock frequency [Hz] OSC3 LCKDV: OSC3 division ratio 1/32 to 1/512 EPSON S1C17704 TECHNICAL MANUAL 22-3...

  • Page 324: Switching Drive Duty

    The drive bias is fixed at 1/5 (using five voltages, V and V ) regardless of the drive duty selected. Figures 22.4.1 and 22.4.2 show the drive waveforms for 1/32 duty and 1/16 duty, respectively. EPSON 22-4 S1C17704 TECHNICAL MANUAL...
  • Page 325 22 LCD DRIVER (LCD) Frame interrupt Frame interrupt 1 frame – – – – COM0 COM0 COM1 COM2 SEG0 SEG1 (GND) COM0–SEG0 (GND) COM0–SEG1 Figure 22.4.1 Drive Waveform for 1/32 Duty EPSON S1C17704 TECHNICAL MANUAL 22-5...
  • Page 326 22 LCD DRIVER (LCD) Frame interrupt Frame interrupt 1 frame – – – – COM0 COM0 COM1 COM2 SEG0 SEG1 (GND) COM0–SEG0 (GND) COM0–SEG1 Figure 22.4.2 Drive Waveform for 1/16 Duty EPSON 22-6 S1C17704 TECHNICAL MANUAL...

  • Page 327: Display Memory

    22 LCD DRIVER (LCD) 22.5 Display Memory The S1C17704 has a built-in 576-byte display memory located from address 0x80000 to address 0x8055f. The memory bit allocation to the COM/SEG pins will change according to the conditions below. (1) Drive duty (1/32 or 1/16)
  • Page 328 COMREV is 1 (default), the display memory bits are allocated to the COM pins in ascending order; when COMREV is set to 0, the addresses are allocated in descending order. (See Figures 22.5.1 and 22.5.2.) ∗ COMREV: Common Output Assignment Control Bit in the LCD Display Control (LCD_DCTL) Register (D6/0x50a0) EPSON 22-8 S1C17704 TECHNICAL MANUAL...

  • Page 329: Display Control

    ∗ DSPREV: Reverse Display Control Bit in the LCD Display Control (LCD_DCTL) Register (D4/0x50a0) However, the display cannot be reversed when “All off” is selected with DSPC[1:0] (D[1:0]/LCD_DCTL register). The display can be reversed when “All on” is selected. EPSON S1C17704 TECHNICAL MANUAL 22-9...

  • Page 330: Controlling Gray Scale Display

    Gray levels that can be produced depend on the LCD panel characteristics. The gray scale display should be performed by controlling the frame frequency and the frame cycles to turn the pixel on and off according to the panel characteristics. See Section 22.7 for the frame interrupt. EPSON 22-10 S1C17704 TECHNICAL MANUAL...

  • Page 331: Lcd Interrupt

    • No other cause of interrupt having higher priority, such as NMI, has occurred. For details on these interrupt control registers, as well as the device operation when an interrupt has occurred, see Chapter 6, “Interrupt Controller (ITC).” EPSON S1C17704 TECHNICAL MANUAL 22-11...
  • Page 332 2. After an interrupt occurs, reset the LCD interrupt flag FRMIF of the LCD module in the interrupt handler routine (this also resets the interrupt flag in the ITC). Interrupt vector The following shows the vector number and vector address for the LCD interrupt: Vector number: 10 (0x0a) Vector address: 0x8028 EPSON 22-12 S1C17704 TECHNICAL MANUAL...

  • Page 333: Details Of Control Registers

    LCD Interrupt Flag Register Indicates/resets interrupt occurrence status. The following describes each LCD register. These are all 8-bit registers. Note: When setting the registers, be sure to write a 0, and not a 1, for all “reserved bits.” EPSON S1C17704 TECHNICAL MANUAL 22-13...

  • Page 334: 0X50A0: Lcd Display Control Register (Lcd_Dctl)

    Setting DSPREV to 0 reverses the display (turns black pixels white and vice versa), and setting it to 1 returns the display to normal. This operation does not affect the contents of the display memory. D[3:2] Reserved EPSON 22-14 S1C17704 TECHNICAL MANUAL...
  • Page 335 DSPC[1:0] is not reset to 0x0 (display off) on execution of a slp command. DSPC[1:0] should be reset to 0x0 (display off) via software before executing a slp command, since switching to SLEEP mode with the LCD display left on will degrade the LCD. EPSON S1C17704 TECHNICAL MANUAL 22-15...

  • Page 336: 0X50A1: Lcd Contrast Adjust Register (Lcd_Cadj)

    Table 22.8.3 LCD Contrast Adjustment LC[3:0] Contrast High (dark) ↑ ↓ Low (light) (Default: 0x0) At initial reset, LC[3:0] is set to 0x0. Initialize LC[3:0] with software to set the display to the desired contrast. EPSON 22-16 S1C17704 TECHNICAL MANUAL...

  • Page 337: X50A2: Lcd Clock Control Register (Lcd_Cctl)

    Table 22.8.4 Setting the Drive Duty LDUTY[1:0] Duty Effective COM pins Effective SEG pins Max number of pixels Reserved – – – 1/32 COM0–COM31 SEG0–SEG55 1,792 pixels 1/16 COM0–COM15 SEG0–SEG71 1,152 pixels Reserved – – – (Default: 0x2) EPSON S1C17704 TECHNICAL MANUAL 22-17...

  • Page 338: X50A3: Lcd Voltage Regulator Control Register (Lcd_Vreg)

    LCD heavy load protection mode 1 On 0 Off Control Register D3–0 – reserved – – – 0 when being read. (LCD_VREG) For details of the control bits, see “0x50a3: LCD Voltage Regulator Control Register (LCD_VREG)” in Section 4.5. EPSON 22-18 S1C17704 TECHNICAL MANUAL...

  • Page 339: 0X50A4: Lcd Power Voltage Booster Control Register (Lcd_Pwr)

    Control Register VDSEL Regulator power source select (LCD_PWR) PBON Power voltage booster control 1 On 0 Off For details of the control bits, see “0x50a4: LCD Power Voltage Booster Control Register (LCD_PWR)” in Section 4.5. EPSON S1C17704 TECHNICAL MANUAL 22-19...

  • Page 340: 0X50A5: Lcd Interrupt Mask Register (Lcd_Imsk)

    Setting FRMIE to 1 enables the LCD module to request interrupts to the ITC; setting to 0 disables the interrupt. In addition, it is necessary to set the LCD interrupt enable bits in the ITC to interrupt enabled to actually generate an interrupt. EPSON 22-20 S1C17704 TECHNICAL MANUAL...

  • Page 341: 0X50A6: Lcd Interrupt Flag Register (Lcd_Iflg)

    (this also resets the interrupt flag in the ITC). The FRMIF flag is reset by writing 1. Note: To avoid occurrence of unnecessary interrupts, be sure to reset the FRMIF flag before the LCD interrupt is enabled using FRMIE. EPSON S1C17704 TECHNICAL MANUAL 22-21...

  • Page 342: Precautions

    • To avoid occurrence of unnecessary interrupts, be sure to reset FRMIF (D0/LCD_IFLG register) before the LCD interrupt is enabled using FRMIE (D0/LCD_IMSK register). • For precautions on the LCD power supply, see Section 4.6, “Precautions.” EPSON 22-22 S1C17704 TECHNICAL MANUAL...

  • Page 343: Supply Voltage Detector (Svd)

    23.1 Outline of the SVD module The S1C17704 is equipped with a supply voltage detector (SVD) to detect supply voltage drop. The SVD module allows software to turn the circuit on and off, to set an evaluate voltage level and to read the detection results. Also it can generate an interrupt when voltage drop has been detected.

  • Page 344: Setting A Compare Voltage

    SVDC[3:0] Compare voltage 2.7 V 2.6 V 2.5 V 2.4 V 2.3 V 2.2 V 2.1 V 2.05 V 2.0 V 1.95 V 1.9 V 1.85 V 1.8 V 0x2 to 0x0 Reserved (Default: 0x0) EPSON 23-2 S1C17704 TECHNICAL MANUAL...

  • Page 345: Controlling The Svd Operation

    SVDDT (D0/SVD_RSLT register) after writing 1 to SVDEN (D0/SVD_EN register). • The SVD operation increases current consumption. Therefore, set SVDEN to 0 to disable the SVD operation if supply voltage detection is not necessary. EPSON S1C17704 TECHNICAL MANUAL 23-3...

  • Page 346: Svd Interrupt

    • No other cause of interrupt having higher priority, such as NMI, has occurred. For details on these interrupt control registers, as well as the device operation when an interrupt has occurred, see Chapter 6, “Interrupt Controller (ITC).” EPSON 23-4 S1C17704 TECHNICAL MANUAL...
  • Page 347 2. After an interrupt occurs, reset the SVDIF interrupt flag of the SVD module in the interrupt handler routine (this also resets the interrupt flag in the ITC). Interrupt vector The following shows the vector number and vector address for the SVD interrupt: Vector number: 9 (0x09) Vector address: 0x8024 EPSON S1C17704 TECHNICAL MANUAL 23-5...

  • Page 348: Details Of Control Registers

    SVD Interrupt Flag Register Indicates/resets interrupt occurrence status. The following describes each SVD register. These are all 8-bit registers. Note: When setting the registers, be sure to write a 0, and not a 1, for all “reserved bits.” EPSON 23-6 S1C17704 TECHNICAL MANUAL...

  • Page 349: 0X5100: Svd Enable Register (Svd_En)

    SVDDT (D0/SVD_RSLT register) after writing 1 to SVDEN. • The SVD operation increases current consumption. Therefore, set SVDEN to 0 to disable the SVD operation if supply voltage detection is not necessary. EPSON S1C17704 TECHNICAL MANUAL 23-7...

  • Page 350: 0X5101: Svd Compare Voltage Register (Svd_Cmp)

    The SVD module compares the voltage set with SVDC[3:0] and the supply voltage (V ) and output the results to indicate whether or not the supply voltage is equal to or higher than the compare voltage. EPSON 23-8 S1C17704 TECHNICAL MANUAL...

  • Page 351: 0X5102: Svd Detection Result Register (Svd_Rslt)

    The SVD module keeps comparing the supply voltage (V ) and the voltage level set with SVDC[3:0] (D[3:0]/SVD_CMP register) while SVDEN (D0/SVD_EN register) is set to 1. By reading SVDDT, the current supply voltage status can be monitored. EPSON S1C17704 TECHNICAL MANUAL 23-9...

  • Page 352: 0X5103: Svd Interrupt Mask Register (Svd_Imsk)

    Setting SVDIE to 1 enables the SVD module to request interrupts to the ITC; setting to 0 disables the interrupt. In addition, it is necessary to set the SVD interrupt enable bits in the ITC to interrupt enabled to actually generate an interrupt. EPSON 23-10 S1C17704 TECHNICAL MANUAL...

  • Page 353: 0X5104: Svd Interrupt Flag Register (Svd_Iflg)

    (this also resets the interrupt flag in the ITC). The SVDIF flag is reset by writing 1. Note: To avoid occurrence of unnecessary interrupts, be sure to reset the SVDIF flag before the SVD interrupt is enabled using SVDIE (D0/SVD_IMSK register). EPSON S1C17704 TECHNICAL MANUAL 23-11...

  • Page 354: Precautions

    SVD operation if supply voltage detection is not necessary. • To avoid occurrence of unnecessary interrupts, be sure to reset the SVDIF flag (D0/SVD_IFLG register) before the SVD interrupt is enabled using SVDIE (D0/SVD_IMSK register). EPSON 23-12 S1C17704 TECHNICAL MANUAL...

  • Page 355: On-Chip Debugger (Dbg)

    Work area for debugging A 64-byte work area is required for debugging. In the S1C17704, the address range from 0x000fc0 to 0x000fff in the RAM is reserved as the work area for debugging. When using the debug functions, do not access this area from the application program.

  • Page 356: Operating Status After Debugging Break Occurs

    ∗ O1DBG: OSC1 Peripheral Control (in Debug Mode) Bit in the OSC1 Peripheral Control (MISC_OSC1) Register (D0/0x5322) Note that the 8-bit OSC1 timer does not stop in debug mode even if O1DBG is set to 1. EPSON 24-2 S1C17704 TECHNICAL MANUAL...

  • Page 357: Details Of Control Registers

    Debug RAM Base Register Indicates the debug RAM base address. The following describes the registers for debugging individually. Note: When setting the registers, be sure to write a 0, and not a 1, for all “reserved bits.” EPSON S1C17704 TECHNICAL MANUAL 24-3...

  • Page 358: 0X5322: Osc1 Peripheral Control Register (Misc_Osc1)

    The following lists the OSC1 peripheral modules that operate with the OSC1 clock: • Clock timer • Watchdog timer • Stopwatch timer Note that the 8-bit OSC1 timer does not stop in debug mode even if O1DBG is set to 1. EPSON 24-4 S1C17704 TECHNICAL MANUAL...

  • Page 359: 0Xffff90: Debug Ram Base Register (Dbram)

    D23–0 DBRAM[23:0] Debug RAM base address 0xfc0 0xfc0 (DBRAM) D[31:24] Unused (fixed at 0) D[23:0] DBRAM[23:0]: Debug RAM Base Address Bits This is a read-only register that contains the start address of a work area (64 bytes) for debugging. EPSON S1C17704 TECHNICAL MANUAL 24-5...
  • Page 360 24 ON-CHIP DEBUGGER (DBG) THIS PAGE IS BLANK. EPSON 24-6 S1C17704 TECHNICAL MANUAL...

  • Page 361: Basic External Wiring Diagram

    Drain capacitor 15 pF (crystal) Capacitor between V and V 0.1 μF 30 pF (ceramic) Booster capacitor 3.3 μF Resistor for CR 30 kΩ Capacitor for power supply 0.47 μF oscillation Cres Capacitor for #RESET terminal EPSON S1C17704 TECHNICAL MANUAL 25-1...
  • Page 362 25 BASIC EXTERNAL WIRING DIAGRAM THIS PAGE IS BLANK. EPSON 25-2 S1C17704 TECHNICAL MANUAL...

  • Page 363: Electrical Characteristics

    V µF ∗1 Capacitor between CF and CG µF ∗1 The capacitors are not necessary when LCD driver is not used. In this case, leave the V to V and CA to CG pins open. EPSON S1C17704 TECHNICAL MANUAL 26-1...

  • Page 364: Dc Characteristics

    Pxx, V = 0V, f = 1MHz, Ta = 25°C Segment/Common output current SEGxx, COMxx, V - 0.1V µA SEGH SEGH SEGxx, COMxx, V = 0.1V µA SEGL SEGL ∗1 When Schmitt input is enabled EPSON 26-2 S1C17704 TECHNICAL MANUAL...

  • Page 365: Analog Circuit Characteristics

    SVDC[3:0] = 0x8 2.05 Typ. × Typ. × SVDC[3:0] = 0x9 0.91 1.09 SVDC[3:0] = 0xa SVDC[3:0] = 0xb SVDC[3:0] = 0xc SVDC[3:0] = 0xd SVDC[3:0] = 0xe SVDC[3:0] = 0xf SVD response time µs EPSON S1C17704 TECHNICAL MANUAL 26-3...

  • Page 366: Flash Memory

    ∗1 Data transfer and data verification are included and erase/program start control time is not included. ∗2 The erase/program count assumes that “erasing + programming” or “programming only” is one count and the programmed data is guaranteed to be retained for 10 years. EPSON 26-4 S1C17704 TECHNICAL MANUAL...

  • Page 367: Current Consumption

    ∗8 The values of current consumption while the CPU was operating were measured when a test program consisting of 60.5% ALU instructions, 17% branch instructions, 12% memory read instructions, and 10.5% memory write in- structions was executed continuously in the Flash memory. EPSON S1C17704 TECHNICAL MANUAL 26-5...

  • Page 368: Ac Characteristics

    = 0V, Ta = -20 to 70°C Item Symbol Min. Typ. Max. Unit SCL cycle time 2500 Start condition hold time Data output delay time Stop condition hold time ∗ f : System operating clock frequency EPSON 26-6 S1C17704 TECHNICAL MANUAL...

  • Page 369: External Clock Input Ac Characteristics

    26.6.4 System AC Characteristics #RESET Unless otherwise specified: V = 1.8 to 3.6V, V = 0V, V = 0.8V = 0.2V , Ta = -20 to 70°C Item Symbol Min. Typ. Max. Unit Reset Low pulse width µs EPSON S1C17704 TECHNICAL MANUAL 26-7...

  • Page 370: Oscillation Characteristics

    Frequency/power voltage deviation ∂f/∂V ppm/V ∂f/∂C Frequency adjustment range = constant, C = 0 to 25pF ∗1 C-002RX: manufactured by Seiko Epson OSC3 (Crystal) ∗1 Unless otherwise specified: V = 1.8 to 3.6V, V = 0V, Ta = 25°C, crystal resonator = CA-301 = 1MΩ,...

  • Page 371: Characteristic Plots (Reference Values)

    Ta = 70°C, Max. value –V = 1.8 V = 2.4 V = 3.6 V Low level output current - voltage characteristic Ta = 70°C, Min. value = 3.6 V = 2.4 V = 1.8 V EPSON S1C17704 TECHNICAL MANUAL 26-9...
  • Page 372 LCD drive voltage - supply voltage characteristic (with the power voltage booster used) When a 1 MΩ load resistor is connected between V and V . (no panel load) Ta = 25°C, Typ. value LCx = 0xf LCx = 0x0 EPSON 26-10 S1C17704 TECHNICAL MANUAL...
  • Page 373 0.95V Ta [°C] LCD drive voltage - load characteristic When a load is connected to the V pin only LCx = 0xf, Ta = 25°C, Typ. value 5.80 5.75 5.70 5.65 5.60 5.55 5.50 [μA] EPSON S1C17704 TECHNICAL MANUAL 26-11...
  • Page 374 OSC3 = OFF, VD1MD = 0, PCKEN = 0, Typ. value OSC1 Ta [°C] Run state current consumption - temperature characteristic (during operation with OSC1) <Crystal oscillation, f = 32.768 kHz> Typ. value OSC1 VD1MD = 1 VD1MD = 0 Ta [°C] EPSON 26-12 S1C17704 TECHNICAL MANUAL...
  • Page 375 Ta = 25°C, Typ. value 4000 VD1MD = 1 3500 3000 2500 2000 VD1MD = 0 1500 1000 1000 [kΩ] OSC3 oscillation frequency - resistor characteristic <CR oscillation> Ta = 25°C, Typ. value 10000 1000 1000 [kΩ] EPSON S1C17704 TECHNICAL MANUAL 26-13...
  • Page 376 10000 1000 Ta [°C] Processing power - frequency characteristic = 3.6V, VD1MD = 0, Typ. value 1600 FLCYC = 4 (1 cycle) 1400 1200 FLCYC = 0 (2 cycles) 1000 10.0  OSC3 clock frequency [MHz] EPSON 26-14 S1C17704 TECHNICAL MANUAL...

  • Page 377: Package

    27 PACKAGE 27 Package TQFP24-144-pin package (Unit: mm) ±0.4 ±0.1 INDEX +0.10 0.16 –0.05 +0.05 0.125 –0.025 0° 8° ±0.2 EPSON S1C17704 TECHNICAL MANUAL 27-1...
  • Page 378 – – – – – – 0.23 – – – 0.26 – 0.36 – – 0.08 – – – – A1 Corner 1 2 3 4 5 6 7 8 9 10 11 – – EPSON 27-2 S1C17704 TECHNICAL MANUAL...
  • Page 379 – – – – 0.23 – – – 0.26 – 0.36 – – 0.08 – – – – 1 2 3 4 5 6 7 8 9 10 11 12 13 – – A1 Corner EPSON S1C17704 TECHNICAL MANUAL 27-3...
  • Page 380 – – – – – – – – – 0.38 – 0.48 – – 0.08 – – – – 1 2 3 4 5 6 7 8 9 10 11 12 A1 Corner – – EPSON 27-4 S1C17704 TECHNICAL MANUAL...

  • Page 381: Pad Layout

    28.1 Diagram of Pad Layout (0, 0) Die No. CJ701D∗∗∗ 3.97 mm 70 × 104 µm Pad opening) Pad No. 1–36, 73–109 : Pad No. 37–72, 110–145: 104 × 70 µm Chip thickness) 400 µm EPSON S1C17704 TECHNICAL MANUAL 28-1...

  • Page 382: Pad Coordinates

    1.870 1.375 107 N.C. -1.395 1.880 144 SEG15 -1.870 -1.425 SEG52 1.400 -1.880 72 1.870 1.455 108 -1.475 1.880 145 SEG16 -1.870 -1.505 – – – – – – – – -1.555 1.880 – – – – EPSON 28-2 S1C17704 TECHNICAL MANUAL...

  • Page 383: Appendix A List Of I/O Registers

    I2C_CTL C Control Register Controls the I C operation and indicates transfer status. 0x4344 I2C_DAT C Data Register Transmit/receive data 0x4346 I2C_ICTL C Interrupt Control Register Controls the I C interrupt. 0x4348–0x435f – – Reserved EPSON S1C17704 TECHNICAL MANUAL AP-1...
  • Page 384 Controls the P1 port Schmitt trigger input. 0x5215 P1_IMSK P1 Port Interrupt Mask Register Enables/disables the P1 port interrupt. 0x5216 P1_EDGE P1 Port Interrupt Edge Select Register Selects the signal edge for generating P1 port interrupts EPSON AP-2 S1C17704 TECHNICAL MANUAL...
  • Page 385 Indicates the debug RAM base address. Note: Do not access the “Reserved” address in the table above and unused areas in the peripheral area that are not described in the table from the application program. EPSON S1C17704 TECHNICAL MANUAL AP-3...

  • Page 386: 0X4020

    Prescaler Con- 0x4020 D7–2 – reserved – – – 0 when being read. trol Register (8 bits) PRUND Prescaler run/stop in debug mode 1 Run 0 Stop (PSC_CTL) PRUN Prescaler run/stop control 1 Run 0 Stop EPSON AP-4 S1C17704 TECHNICAL MANUAL...

  • Page 387: 0X4100-0X4105

    D6–4 IRCLK[2:0] IrDA receive detection clock select IRCLK[2:0] Clock 0x0 R/W Register PCLK•1/128 (UART_EXP) PCLK•1/64 PCLK•1/32 PCLK•1/16 PCLK•1/8 PCLK•1/4 PCLK•1/2 PCLK•1/1 D3–1 – reserved – – – 0 when being read. IRMD IrDA mode select 1 On 0 Off EPSON S1C17704 TECHNICAL MANUAL AP-5...

  • Page 388: 0X4200-0X4206

    0 when being read. TRMD Count mode select 1 One shot 0 Repeat D3–2 – reserved – – – 0 when being read. PRESER Timer reset 1 Reset 0 Ignored PRUN Timer run/stop control 1 Run 0 Stop EPSON AP-6 S1C17704 TECHNICAL MANUAL...

  • Page 389: 0X4220-0X4266

    0 when being read. TRMD Count mode select 1 One shot 0 Repeat D3–2 – reserved – – – 0 when being read. PRESER Timer reset 1 Reset 0 Ignored PRUN Timer run/stop control 1 Run 0 Stop EPSON S1C17704 TECHNICAL MANUAL AP-7...
  • Page 390 0 when being read. TRMD Count mode select 1 One shot 0 Repeat D3–2 – reserved – – – 0 when being read. PRESER Timer reset 1 Reset 0 Ignored PRUN Timer run/stop control 1 Run 0 Stop EPSON AP-8 S1C17704 TECHNICAL MANUAL...

  • Page 391: 0X4300-0X4314

    EITG6 LCD interrupt trigger mode 1 Level 0 Pulse R/W Be sure to set to 1. – reserved – – – 0 when being read. D2–0 EILV6[2:0] LCD interrupt level 0 to 7 0x0 R/W EPSON S1C17704 TECHNICAL MANUAL AP-9...
  • Page 392 (16 bits) D10–8 IILV7[2:0] C interrupt level 0 to 7 0x0 R/W Setup Register 3 D7–3 – reserved – – – 0 when being read. (ITC_ILV3) D2–0 IILV6[2:0] SPI interrupt level 0 to 7 0x0 R/W EPSON AP-10 S1C17704 TECHNICAL MANUAL...

  • Page 393: Spi

    R/W These bits must be set before setting CPOL Clock polarity select 1 Active L 0 Active H SPEN to 1. MSSL Master/slave mode select 1 Master 0 Slave SPEN SPI enable 1 Enable 0 Disable EPSON S1C17704 TECHNICAL MANUAL AP-11...

  • Page 394: 0X4340-0X4346

    RTDT0 = LSB C Interrupt 0x4346 D15–2 – reserved – – – 0 when being read. Control Register (16 bits) RINTE Receive interrupt enable 1 Enable 0 Disable (I2C_ICTL) TINTE Transmit interrupt enable 1 Enable 0 Disable EPSON AP-12 S1C17704 TECHNICAL MANUAL...

  • Page 395: 0X5000-0X5003

    32 Hz interrupt flag 1 Cause of 0 Cause of R/W Reset by writing 1. Register interrupt interrupt not CTIF8 8 Hz interrupt flag (CT_IFLG) occurred occurred CTIF2 2 Hz interrupt flag CTIF1 1 Hz interrupt flag EPSON S1C17704 TECHNICAL MANUAL AP-13...

  • Page 396: 0X5020-0X5023

    (8 bits) SIF1 1 Hz interrupt flag 1 Cause of 0 Cause of R/W Reset by writing 1. Flag Register interrupt interrupt not SIF10 10 Hz interrupt flag (SWT_IFLG) occurred occurred SIF100 100 Hz interrupt flag EPSON AP-14 S1C17704 TECHNICAL MANUAL...

  • Page 397: 0X5040-0X5041

    Watchdog 0x5041 D7–2 – reserved – – – 0 when being read. Timer Status (8 bits) WDTMD Register NMI/Reset mode select 1 Reset 0 NMI (WDT_ST) WDTST NMI status 1 NMI occurred 0 Not occurred EPSON S1C17704 TECHNICAL MANUAL AP-15...

  • Page 398: 0X5060-0X5065

    0 when being read. Control Register (8 bits) D3–1 T8O1CK[2:0] T8OSC1 clock division ratio select T8O1CK[2:0] Division ratio 0x0 R/W (OSC_T8OSC1) 0x7–0x6 reserved OSC1•1/32 OSC1•1/16 OSC1•1/8 OSC1•1/4 OSC1•1/2 OSC1•1/1 T8O1CE T8OSC1 clock output enable 1 Enable 0 Disable EPSON AP-16 S1C17704 TECHNICAL MANUAL...

  • Page 399: 0X5080-0X5081

    Enable Not allowed Not allowed Disable CCLK Control 0x5081 D7–2 – reserved – – – 0 when being read. Register (8 bits) D1–0 CCLKGR[1:0] CCLK clock gear ratio select CCLKGR[1:0] Gear ratio 0x0 R/W (CLG_CCLK) EPSON S1C17704 TECHNICAL MANUAL AP-17...

  • Page 400: 0X50A0-0X50A6

    0 Disable LCD Interrupt 0x50a6 D7–1 – reserved – – – 0 when being read. Flag Register (8 bits) (LCD_IFLG) FRMIF Frame signal interrupt flag 1 Cccurred 0 Not occurred R/W Reset by writing 1. EPSON AP-18 S1C17704 TECHNICAL MANUAL...

  • Page 401: 0X50C0-0X50C4

    – – 0 when being read. Timer Interrupt (8 bits) T8OIF 8-bit OSC1 timer interrupt flag 1 Cause of 0 Cause of R/W Reset by writing 1. Flag Register interrupt interrupt not (T8OSC1_IFLG) occurred occurred EPSON S1C17704 TECHNICAL MANUAL AP-19...

  • Page 402: 0X5100-0X5104

    D7–1 – reserved – – – 0 when being read. Flag Register (8 bits) SVDIF SVD interrupt flag 1 Cause of 0 Cause of R/W Reset by writing 1. (SVD_IFLG) interrupt interrupt not occurred occurred EPSON AP-20 S1C17704 TECHNICAL MANUAL...

  • Page 403: 0X5120

    0 when being read. Register (8 bits) HVLD heavy load protection mode 1 On 0 Off (VD1_CTL) D3–1 – reserved – – – 0 when being read. VD1MD Flash erase/program mode 1 Flash (2.5 V) 0 Norm.(1.8 V) EPSON S1C17704 TECHNICAL MANUAL AP-21...

  • Page 404: 0X5200-0X52A3

    1 Enable 0 Disable Control Register (8 bits) (0xff) (P1_PU) P1 Port Schmitt 0x5214 D7–0 P1SM[7:0] P1[7:0] port Schmitt trigger input 1 Enable 0 Disable Trigger Control (8 bits) enable (Schmitt) (CMOS) (0xff) Register (P1_SM) EPSON AP-22 S1C17704 TECHNICAL MANUAL...
  • Page 405 P33 port function select 1 P33 0 DSIO Register P32MUX P32 port function select 1 P32 0 DST2 (P3_PMUX) P31MUX P31 port function select 1 P31 0 DCLK P30MUX P30 port function select 1 FOUT3 0 P30 EPSON S1C17704 TECHNICAL MANUAL AP-23...

  • Page 406: 0X5300-0X530C

    0 when being read. Interrupt (16 bits) CBIF Compare B interrupt flag 1 Cause of 0 Cause of R/W Reset by writing 1. Flag Register interrupt interrupt not CAIF Compare A interrupt flag occurred occurred (T16E_IFLG) EPSON AP-24 S1C17704 TECHNICAL MANUAL...

  • Page 407: 0X5320-0X5322

    4 cycles 3 cycles 2 cycles OSC1 Peripheral 0x5322 D7–1 – reserved – – – 0 when being read. Control Register (8 bits) O1DBG OSC1 peripheral control in debug 1 Run 0 Stop (MISC_OSC1) mode EPSON S1C17704 TECHNICAL MANUAL AP-25...

  • Page 408: 0X5340-0X5347

    Flag Register (8 bits) REMFIF Falling edge interrupt flag 1 Cause of 0 Cause of R/W Reset by writing 1. (REMC_IFLG) REMRIF interrupt interrupt not Rising edge interrupt flag occurred occurred REMUIF Underflow interrupt flag EPSON AP-26 S1C17704 TECHNICAL MANUAL...

  • Page 409: 0Xffff80-0Xffff90

    D7–0 IDIR[7:0] Processor ID 0x10 0x10 Register (8 bits) 0x10: S1C17 Core (IDIR) Debug RAM 0xffff90 D31–24 – Unused (fixed at 0) Base Register (32 bits) D23–0 DBRAM[23:0] Debug RAM base address 0xfc0 0xfc0 (DBRAM) EPSON S1C17704 TECHNICAL MANUAL AP-27...

  • Page 410: Appendix B Flash Programming

    ICD (e.g. S5U1C17001H). Use the S1C17704 DCLK (P31), DST2 (P32), and DSIO (P33) pins as the debug pins and connect them to the four-pin connector. In this case, the P31 to P33 general-purpose I/O ports cannot be used.

  • Page 411: Self-Programming By Application Program

    The S1C17704 has a self-programming function that allows the application program being executed to erase and program the Flash memory while the S1C17704 is running on the target board. For the S1C17704, an object file that includes the functional routines for self-programming is provided as the self-programming package.

  • Page 412: Appendix C Power Saving

    Current consumption depends, to a large degree, on the CPU operating mode, operating clock frequency, and the peripheral circuits to be activated. This chapter summarizes the control to save power. C.1 Power Saving by Clock Control Figure C.1.1 shows the S1C17704 clock system. SLEEP, On/Off control wakeup...

  • Page 413: System Clock

    - 16-bit timer Ch.0–2 - Interrupt controller - SPI - SVD circuit - Power control circuit - P port & port MUX (control registers and chattering filters) - PWM & capture timer - MISC register - Remote controller EPSON S1C17704 TECHNICAL MANUAL AP-31...
  • Page 414 If the IE flag in the CPU has been set to 0, the CPU does not accept the interrupt request and starts executing the instructions that follow the halt instruction. If the IE flag has been set to 1, the CPU executes the interrupt handler. EPSON AP-32 S1C17704 TECHNICAL MANUAL...

  • Page 415: Power Saving By Power Supply Control

    • When the LCD display is not necessary, turn the LCD driver off. Also the power voltage booster should be turned off. Supply voltage detector (SVD) • The SVD operation increases current consumption. Turn the SVD module off when supply voltage detection is not necessary. EPSON S1C17704 TECHNICAL MANUAL AP-33...

  • Page 416: Appendix D Precautions On Mounting

    When the OSC3 output is jittery, the operating frequency will be lowered. When the OSC1 output is noisy, operation of the timers using the OSC1 clock and the CPU core after the system clock is switched to OSC1 will be unstable. EPSON AP-34 S1C17704 TECHNICAL MANUAL...

  • Page 417: Reset Circuit

    Do not arrange a high-speed signal line especially near circuits that are sensitive to noise such as the oscillator unit. Prohibited pattern OSC1, OSC3 OSC2, OSC4 Large current signal line High-speed signal line EPSON S1C17704 TECHNICAL MANUAL AP-35...
  • Page 418 Take corrective measures by shortening the parallel distance (to several cm) or separating signal lines (2 mm or more). EPSON AP-36 S1C17704 TECHNICAL MANUAL...
  • Page 419 (experimental confirmation), (2) Electromagnetic induction noise from the tip of a soldering iron Especially when using a soldering iron, make sure that the IC GND and soldering iron GND are at the same potential before soldering. EPSON S1C17704 TECHNICAL MANUAL AP-37...

  • Page 420: Appendix E Initialize Routine

    ; 1 cycle access, under 6 MHz system clock ...(5) ld.b [%r1], %r0 ; [0x5320] <= 0x04 ; SRAMC Xld.a %r0, 0x00 ; 2 cycle access 0x01 ...(6) ld.b [%r1], %r0 ; [0x5321] <= 0x01 EPSON AP-38 S1C17704 TECHNICAL MANUAL...
  • Page 421 (7) Set the interrupt trigger mode for the peripheral modules listed below to level trigger. P0 port, P1 port, stopwatch timer, clock timer, 8-bit OSC1 timer, SVD, LCD driver, PWM & capture timer (See Chapter 6, “Interrupt Controller (ITC).”) EPSON S1C17704 TECHNICAL MANUAL AP-39...
  • Page 422 12/F, Dawning Mansion, Keji South 12th Road, Phone: +49-89-14005-0 FAX: +49-89-14005-110 Hi- Tech Park, Shenzhen Phone: +86-755-2699-3828 FAX: +86-755-2699-3838 EPSON TAIWAN TECHNOLOGY & TRADING LTD. 14F, No. 7, Song Ren Road, Taipei 110 Phone: +886-2-8786-6688 FAX: +886-2-8786-6660 EPSON SINGAPORE PTE., LTD.
  • Page 423 S1C17704 TECHNICAL MANUAL SEMICONDUCTOR OPERATIONS DIVISION EPSON Electronic Devices Website http://www.epson.jp/device/semicon_e/ Document code: 411511901 First Issue June 2008 Revised August 2008 in JAPAN...

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