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Register name
Address
Bit
HDLC interrupt
0200302
D15–8
control register
(HW)
D7
D6
D5–2
D1
D0
HDLC interrupt
0200304
D15–8
enable settings
(HW)
D7
register
D6
D5
D4
D3–0
HDLC clear
0200306
D15–8
interrupt
(HW)
D7
enable register
D6
D5
D4
D3–0
HDLC transfer
0200308
D15–8
settings
(HW)
D7
register
D6
D5–2
D1
D0
HDLC cancel
020030A
D15–8
transfer
(HW)
D7
register
D6
D5–2
D1
D0
HDLC receive
020030C
D15–8
address
(HW)
D7
register
D6
D5
D4
D3
D2
D1
D0
HDLC receive
020030E
D15–8
operation
(HW)
D7
settings
D6
registe
r
D5
D4
D3–0
HDLC receive
0200310
D15–3
queue interrupt
(HW)
D2
threshold
D1
register
D0
S1C33210 FUNCTION PART
Name
Function
–
–
ERES
HDLC error reset
RESINT
HDLC E/S interrupt reset
–
–
RRXINT
HDLC receive interrupt reset
RTXINT
HDLC transmit interrupt reset
–
–
ABRTIES
Enable Abort interrupt setting
TXUEIES
Enable TXUDR interrupt setting
HUNTIES
Enable Hunt interrupt setting
IDLDIES
Enable idle detection interrupt setting
–
–
–
–
ABRTIEC
Clear Abort interrupt enable
TXUEIEC
Clear TXUDR interrupt enable
HUNTIEC
Clear Hunt interrupt enable
IDLDIEC
Clear idle detection interrupt
enable
–
–
–
–
RXENS
HDLC enable receive setting
TXENS
HDLC enable transmit setting
–
–
RXIES
HDLC enable receive interrupt setting
TXIES
HDLC enable transmit interrupt setting
–
–
RXENC
HDLC clear receive enable
TXENC
HDLC clear transmit enable
–
–
RXIEC
HDLC clear receive interrupt enable
TXIEC
HDLC clear transmit interrupt enable
–
–
RXADD7
HDLC receive address
RXADD6
RXADD7 = MSB
RXADD5
RXADD0 = LSB
RXADD4
RXADD3
RXADD2
RXADD1
RXADD0
–
–
ADDCE
HDLC enable address compare
ADDCM
HDLC address compare mode
IDLDE
HDLC enable idle detection
SHFDE
HDLC enable short frame detection
–
–
–
–
RXFTH2
Receive queue interrupt level
RXFTH1
RXFTH0
Setting
–
1 Reset
0 Ignored
1 Reset
0 Ignored
–
1 Reset
0 Ignored
1 Reset
0 Ignored
–
1 Enable
0 Disabled
1 Enable
0 Disabled
1 Enable
0 Disabled
1 Enable
0 Disabled
–
–
1
Clear interrupt
0
Ignored
enable
1
Clear interrupt
0
Ignored
enable
1
Clear interrupt
0
Ignored
enable
1
Clear interrupt
0
Ignored
enable
–
–
1 Enable
0 Disable
1 Enable
0 Disable
–
1 Enable
0 Disabled
1 Enable
0 Disabled
–
1 Clear enable 0 Ignored
1 Clear enable 0 Ignored
–
1 Clear enable 0 Ignored
1 Clear enable 0 Ignored
–
0x00 to 0xFF
–
1 Enable
0 Disable
1 Half
0 Full
1 Enable
0 Disable
1 Enable
0 Disable
–
–
RXFTH[2:0]
1
1
1
8 (Full)
1
1
0
7
1
0
1
6
1
0
0
5
0
1
1
4 (Half)
0
1
0
3
0
0
1
2
0
0
0
1 (receive
character available)
EPSON
APPENDIX: I/O MAP
Init. R/W
Remarks
–
–
0 when being read.
0
W
0
W
–
–
0 when being read.
0
W
0
W
–
–
0 when being read.
0
R/W
Writes of "0" are ignored
0
R/W
Writes of "0" are ignored
0
R/W
Writes of "0" are ignored
0
R/W
Writes of "0" are ignored
–
–
0 when being read.
–
–
0 when being read.
0
R/W
0
R/W
0
R/W
0
R/W
–
–
0 when being read.
–
–
0 when being read.
0
R/W
Writes of "0" are ignored
0
R/W
Writes of "0" are ignored
–
–
0 when being read.
0
R/W
Writes of "0" are ignored
0
R/W
Writes of "0" are ignored
–
–
0 when being read.
0
R/W
0
R/W
–
–
0 when being read.
0
R/W
0
R/W
–
–
0 when being read.
0
R/W
0
0
0
0
0
0
0
–
–
0 when being read.
0
R/W
0
R/W
0
R/W
0
R/W
–
–
0 when being read.
–
–
0 when being read.
Level
0
R/W
0
R/W
0
R/W
B-APPENDIX-45
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