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V DMA BLOCK: HSDMA (High-Speed DMA)
Register name
Address
Bit
High-speed
0048244
DF
DMA Ch.2
(HW)
DE
low-order
DD
source address
DC
set-up register
DB
DA
Note:
D9
D) Dual address
A8
mode
D7
S) Single
D6
address
D5
mode
D4
D3
D2
D1
D0
High-speed
0048246
DF
DMA Ch.2
(HW)
DE
high-order
DD
source address
DC
set-up register
Note:
D) Dual address
DB
mode
DA
S) Single
D9
address
A8
mode
D7
D6
D5
D4
D3
D2
D1
D0
High-speed
0048248
DF
DMA Ch.2
(HW)
DE
low-order
DD
destination
DC
address set-up
DB
register
DA
D9
Note:
A8
D) Dual address
D7
mode
D6
S) Single
D5
address
D4
mode
D3
D2
D1
D0
B-V-2-24
Name
Function
S2ADRL15
D) Ch.2 source address[15:0]
S2ADRL14
S) Ch.2 memory address[15:0]
S2ADRL13
S2ADRL12
S2ADRL11
S2ADRL10
S2ADRL9
S2ADRL8
S2ADRL7
S2ADRL6
S2ADRL5
S2ADRL4
S2ADRL3
S2ADRL2
S2ADRL1
S2ADRL0
–
reserved
DATSIZE2
Ch.2 transfer data size
S2IN1
D) Ch.2 source address control
S2IN0
S) Ch.2 memory address control
S2ADRH11
D) Ch.2 source address[27:16]
S2ADRH10
S) Ch.2 memory address[27:16]
S2ADRH9
S2ADRH8
S2ADRH7
S2ADRH6
S2ADRH5
S2ADRH4
S2ADRH3
S2ADRH2
S2ADRH1
S2ADRH0
D2ADRL15
D) Ch.2 destination address[15:0]
D2ADRL14
S) Invalid
D2ADRL13
D2ADRL12
D2ADRL11
D2ADRL10
D2ADRL9
D2ADRL8
D2ADRL7
D2ADRL6
D2ADRL5
D2ADRL4
D2ADRL3
D2ADRL2
D2ADRL1
D2ADRL0
Setting
–
1 Half word
0 Byte
S2IN[1:0]
Inc/dec
1
1
Inc.(no init)
1
0
Inc.(init)
0
1
Dec.(no init)
0
0
Fixed
EPSON
Init. R/W
Remarks
X
R/W
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
–
–
0
R/W
0
R/W
0
X
R/W
X
X
X
X
X
X
X
X
X
X
X
X
R/W
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
S1C33210 FUNCTION PART
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