Epson S1C33210 Technical Manual page 550

APPENDIX: I/O MAP
Register name Address Bit
High-speed 0048258 DF
DMA Ch.3 (HW) DE
low-order DD
destination DC
address set-up DB
register DA
D9
Note:
A8
D) Dual address
D7
mode
D6
S) Single
D5
address
D4
mode
D3
D2
D1
D0
High-speed 004825A DF
DMA Ch.3 (HW) DE
high-order
destination
address set-up
register DD
DC
Note:
D) Dual address
mode
S) Single
DB
address
DA
mode
D9
A8
D7
D6
D5
D4
D3
D2
D1
D0
High-speed 004825C DF–1
DMA Ch.3 (HW)
enable register D0
High-speed 004825E DF–1
DMA Ch.3 (HW)
trigger flag D0
register
B-APPENDIX-42
Name Function
D3ADRL15 D) Ch.3 destination address[15:0]
D3ADRL14 S) Invalid
D3ADRL13
D3ADRL12
D3ADRL11
D3ADRL10
D3ADRL9
D3ADRL8
D3ADRL7
D3ADRL6
D3ADRL5
D3ADRL4
D3ADRL3
D3ADRL2
D3ADRL1
D3ADRL0
D3MOD1 Ch.3 transfer mode
D3MOD0
D3IN1 D) Ch.3 destination address
D3IN0 control
S) Invalid
D3ADRH11 D) Ch.3 destination
D3ADRH10 address[27:16]
D3ADRH9 S) Invalid
D3ADRH8
D3ADRH7
D3ADRH6
D3ADRH5
D3ADRH4
D3ADRH3
D3ADRH2
D3ADRH1
D3ADRH0
– reserved
HS3_EN Ch.3 enable
– reserved
HS3_TF Ch.3 trigger flag clear (writing)
Ch.3 trigger flag status (reading)
Setting
D3MOD[1:0] Mode
1 1 Invalid
1 0 Block
0 1 Successive
0 0 Single
D3IN[1:0] Inc/dec
1 1 Inc.(no init)
1 0 Inc.(init)
0 1 Dec.(no init)
0 0 Fixed
–
1 Enable 0 Disable
–
1 Clear 0 No operation
1 Set 0 Cleared
EPSON
Init. R/W Remarks
X R/W
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0 R/W
0
0 R/W
0
X R/W
X
X
X
X
X
X
X
X
X
X
X
– – Undefined in read.
0 R/W
– – Undefined in read.
0 R/W
S1C33210 FUNCTION PART