Epson S1C33210 Technical Manual page 403

(2) HDLC Receive Interrupts (Rx INT)
The Rx INT and Sp INT interrupt request timing depends on the receive interrupt setup setting in the HDLC
receive interrupt mode settings register (D[1:0]/0x0200312).
(a) 00 = interrupt requests on first character received
There is an Rx INT interrupt request when the receive character available (RCA) bit in the HDLC receive
control register (D1/0x0200330) first goes to "1" when the hardware receives the first byte
after a reset (hardware or software) or
after the software writes "1" to the Rx INT on next receive character command bit in the HDLC
receive control register (D0/0x0200314).
Note that this mode of operation requires a receive queue interrupt threshold setting of zero in the HDLC
receive queue interrupt threshold register (D[2:0]/0x0200310).
(b) 01 = interrupt requests at queue threshold
There is an Rx INT interrupt request when the number of characters in the receive queue exceeds the
threshold setting in the HDLC receive queue interrupt threshold register (D[2:0]/0x0200310).
(3) HDLC_SP Interrupts (Sp INT) and Queue Operation
There is an Sp INT interrupt request when the following bits in the HDLC Sp INT receive status register
(0x020032E) go to "1."
The Rx overrun bit in the HDLC Sp INT receive status register (D7/0x020032E) goes to "1" to indicate
an overrun in the receive data.
The end of frame bit in the HDLC Sp INT receive status register (D6/0x020032E) goes to "1" to indicate
detection of the closing flag pattern.
The short frame bit in the HDLC Sp INT receive status register (D0/0x020032E) goes to "1" to indicate
detection of a frame with fewer than 32 bits.
An Sp INT interrupt request produces the following effects on the queue.
If the setting specifies Rx INT and Sp INT on queue threshold and the queue is below the threshold level, the
hard ware stores the byte teiggering the interrupt request in the queue, Otherwise, the byte goes into the receive
data register.
An Sp INT interrupt request locks the receive queue so that the software can read the byte and the receive
status. Release the lock with an error reset command.
Note that the software must read the HDLC Sp INT receive status register before the receive data register
because reading the latter updates the former.
S1C33210 FUNCTION PART
III PERIPHERAL BLOCK: MONITORED MOBILE ACCESS INTERFACES
EPSON
B-III-10-17