Page 1 MF1574 - 01 CMOS 32 - BIT SINGLE CHIP MICROCOMPUTER S1C33L03 Technical Manual S1C33L03 PRODUCT PART S1C33L03 FUNCTION PART...
Page 2 No part of this material may be reproduced or duplicated in any form or by any means without the written permission of Seiko Epson. Seiko Epson reserves the right to make changes to this material without notice. Seiko Epson does not assume any...
Page 3 S1C33L03 Technical Manual This manual describes the hardware specifications of the Seiko Epson original 32-bit microcomputer S1C33L03. S1C33L03 PRODUCT PART Describes the hardware specifications of the S1C33L03 except for details of the peripheral circuits. S1C33L03 FUNCTION PART Describes details of all the peripheral circuit blocks for the S1C33 Family microcomputers.
Page 5: Table Of Contents
8.6.5 LCD Interface AC Characteristics ................A-96 8.7 Oscillation Characteristics....................A-107 8.8 PLL Characteristics ......................A-108 9 Package ..........................A-109 9.1 Plastic Package ........................A-109 10 Pad Layout .........................A-110 10.1 Pad Layout Diagram......................A-110 10.2 Pad Coordinate........................A-111 EPSON S1C33L03 TECHNICAL MANUAL...
Page 6 Appendix A <Reference> External Device Interface Timings.......... A-113 A.1 DRAM (70ns)........................A-114 A.2 DRAM (60ns)........................A-117 A.3 ROM and Burst ROM ......................A-121 A.4 SRAM (55ns) ........................A-123 A.5 SRAM (70ns) ........................A-125 A.6 8255A............................ A-127 Appendix B Pin Characteristics ................... A-128 EPSON S1C33L03 TECHNICAL MANUAL...
Page 7 Setting Device Type and Size ..................B-II-4-10 Setting SRAM Timing Conditions................. B-II-4-11 Setting Timing Conditions of Burst ROM ..............B-II-4-12 Bus Operation........................... B-II-4-13 Data Arrangement in Memory ..................B-II-4-13 Bus Operation of External Memory ................B-II-4-13 EPSON S1C33L03 TECHNICAL MANUAL...
Page 8 Power-Control Register Protection Flag ..................B-II-6-5 Operation in Standby Mode ....................... B-II-6-5 I/O Memory of Clock Generator ....................B-II-6-6 Programming Notes........................B-II-6-9 II-7 DBG (Debug Unit)......................B-II-7-1 Debug Circuit ..........................B-II-7-1 I/O Pins of Debug Circuit......................B-II-7-1 EPSON S1C33L03 TECHNICAL MANUAL...
Page 9 Switching Over the CPU Operating Clock ................B-III-6-3 Power-Control Register Protection Flag ................... B-III-6-4 Operation in Standby Mode ......................B-III-6-4 OSC1 Clock Output to External Devices .................. B-III-6-4 I/O Memory of Low-Speed (OSC1) Oscillation Circuit ............. B-III-6-5 Programming Notes........................B-III-6-8 EPSON S1C33L03 TECHNICAL MANUAL...
Page 10 I/O Control Register and I/O Modes................B-III-9-5 I/O Memory of I/O Ports....................B-III-9-6 Input Interrupt .......................... B-III-9-12 Port Input Interrupt....................... B-III-9-12 Key Input Interrupt ....................... B-III-9-14 Control Registers of the Interrupt Controller............... B-III-9-16 I/O Memory for Input Interrupts ................... B-III-9-18 Programming Notes.........................B-III-9-25 EPSON S1C33L03 TECHNICAL MANUAL...
Page 11 I/O Memory of HSDMA......................B-V-2-17 Programming Notes........................B-V-2-36 V-3 IDMA (Intelligent DMA)....................B-V-3-1 Functional Outline of IDMA ......................B-V-3-1 Programming Control Information....................B-V-3-1 IDMA Invocation .........................B-V-3-5 Operation of IDMA........................B-V-3-8 Linking............................B-V-3-12 Interrupt Function of Intelligent DMA ..................B-V-3-13 I/O Memory of Intelligent DMA....................B-V-3-14 Programming Notes........................B-V-3-17 EPSON S1C33L03 TECHNICAL MANUAL...
Page 12 Look-up Tables ......................B-VII-2-11 Frame Rates ......................B-VII-2-19 Other Settings ......................B-VII-2-20 Display Control ........................B-VII-2-21 Controlling LCD Power Up/Down................B-VII-2-21 Reading/Writing Display Data ................... B-VII-2-22 Setting the Display Start Address ................B-VII-2-22 Split-Screen Display ....................B-VII-2-23 EPSON viii S1C33L03 TECHNICAL MANUAL...
Page 13 Portrait Mode ......................B-VII-2-25 Power Save........................ B-VII-2-29 Controlling the GPIO Pins ..................B-VII-2-30 I/O Memory of LCD Controller....................B-VII-2-31 Programming Notes....................... B-VII-2-42 Precautions on Using ICD33....................B-VII-2-42 Examples of LCD Controller Setting Program..............B-VII-2-43 APPENDIX I/O MAP EPSON S1C33L03 TECHNICAL MANUAL...
Page 15: S1C33L03 Product Part
S1C33L03 PRODUCT PART...
Page 17: Outline
1 OUTLINE 1 Outline The S1C33L03 is a Seiko Epson original 32-bit microcomputer with a built-in LCD controller. It features high speed, low power and low-voltage operation and is most suitable for portable equipment that needs display function, such as information terminals, E-mail terminals, electronic dictionaries.
Page 18 Note: The values of power consumption during execution were measured when a test program that consisted of 55% load instructions, 23% arithmetic operation instructions, 1% mac instruction, 12% branch instructions and 9% ext instruction was being continuously executed. Supply form QFP20-144pin plastic package, or chip. EPSON S1C33L03 PRODUCT PART...
Page 19: Block Diagram
FPDAT[7:4] High-speed #DMAACKx(P32, P33, P04, P06) FPDAT[3:0]/GPO[6:3] DMA (4 ch.) #DMAENDx(P15, P16, P05, P07) FPFRAME LCD Controller FPLINE FPSHIFT DRDY(MOD/FPSHIFT2) LCDPWR P00–07 P10–16 K50–54 I/O Port Input Port P20–27 K60–67 P30–35 Figure 1.2.1 S1C33L03 Block Diagram EPSON S1C33L03 PRODUCT PART...
Page 20: Pin Description
N.C. A12/SDA11 #CE3 K67/AD7 #CE8/#RAS1/#CE14/#RAS3/#SDCE1 A13/SDA12 K66/AD6 #CE7/#RAS0/#CE13/#RAS2/#SDCE0 A14/SDBA0 #CE10EX/#CE9&10EX K65/AD5 A15/SDBA1 #CE6/#CE7&8 K64/AD4 OSC2 #CE4/#CE11/#CE11&12 K63/AD3 OSC1 #X2SPD K62/AD2 #RESET P03/#SRDY0 K61/AD1 P35/#BUSACK/GPIO1 P02/#SCLK0 K60/AD0 P34/#BUSREQ/#CE6/GPIO0 P01/SOUT0 P33/#DMAACK1/SIN3/SDA10 P00/SIN0 Figure 1.3.1 Pin Layout Diagram (QFP20-144pin) EPSON S1C33L03 PRODUCT PART...
Page 21: Pin Functions
Area 11 chip enable when CEFUNC[1:0](D[A:9]/0x48130) = "01" #CE11&12 * When CEFUNC[1:0] = "1x", this pin outputs #CE11+#CE12 signal. #CE3 – Area 3 chip enable – Read signal #EMEMRD – Read signal for internal ROM emulation memory EPSON S1C33L03 PRODUCT PART...
Page 22 Area read signal output for GA when CFEX3(D3/0x402DF) = "1" GPIO2: LCDC general-purpose I/O when LCDCEN(D5/0x39FFE3) = "1" and BREQEN(D2/0x39FFFD) = "0" EA10MD1 Pull-up Area 10 boot mode selection EA10MD1 EA10MD0 Mode EA10MD0 – External ROM mode Internal ROM mode EPSON S1C33L03 PRODUCT PART...
Page 23 I/O port when CFP07(D7/0x402D0) = "0" and CFEX7(D7/0x402DF) = "0" #SRDY1 (default) #DMAEND3 #SRDY1: Serial I/F Ch. 1 ready signal output when CFP07(D7/0x402D0) = "1" and CFEX5(D5/0x402DF) = "0" #DMAEND3: HSDMA Ch. 3 end-of-transfer signal output when CFEX7(D7/0x402DF) = "1" EPSON S1C33L03 PRODUCT PART...
Page 24 16-bit timer 0 event counter input when CFP10(D0/0x402D4) = "1", T8UF0 IOC10(D0/0x402D6) = "0" and CFEX1(D1/0x402DF) = "0" DST0 T8UF0: 8-bit timer 0 output when CFP10(D0/0x402D4) = "1", IOC10(D0/0x402D6) = "1" and CFEX1(D1/0x402DF) = "0" DST0: DST0 signal output when CFEX1(D1/0x402DF) = "1" (default) EPSON S1C33L03 PRODUCT PART...
Page 25 CFP24(D4/0x402D8) = "0" – P25: I/O port when CFP25(D5/0x402D8) = "0" (default) TM3: 16-bit timer 3 output when CFP25(D5/0x402D8) = "1" #SCLK2 #SCLK2: Serial I/F Ch. 2 clock input/output when SSCLK2(D2/0x402DB) = "1" and CFP25(D5/0x402D8) = "0" EPSON S1C33L03 PRODUCT PART...
Page 26 – P35: I/O port when CFP35(D5/0x402DC) = "0" (default) #BUSACK #BUSACK: Bus acknowledge output when CFP35(D5/0x402DC) = "1" and GPIO1 CFP34(D4/0x402DC) = "1" GPIO1: LCDC general-purpose I/O when LCDCEN(D5/0x39FFE3) = "1" and BREQEN(D2/0x39FFFD) = "0" EPSON A-10 S1C33L03 PRODUCT PART...
Page 27 1: CPU clock = bus clock 1, 0: CPU clock = bus clock #NMI Pull-up NMI request input pin #RESET Pull-up Initial reset input pin Note: "#" in the pin names indicates that the signal is low active. EPSON S1C33L03 PRODUCT PART A-11...
Page 28: Power Supply
10 V pins. Be sure to supply the operating voltage to all the pins. Do not open any of them. The operating clock frequency range (OSC3) is 5 MHz to 50 MHz with this voltage. EPSON A-12 S1C33L03 PRODUCT PART...
Page 29: Power Supply For Analog Circuits (Av Dde
Noise on the analog power lines decrease the A/D converting precision, so use a stabilized power supply and make the board pattern with consideration given to that. EPSON S1C33L03 PRODUCT PART A-13...
Page 30: Internal Memory
The S1C33L03 does not have a built-in ROM. The boot address is fixed at 0x0C00000, and so external ROM/Flash should be used in Area 10. For setting up Area 10, refer to the "BCU (Bus Control Unit)" in "S1C33L03 FUNCTION PART" in this manual. EPSON A-14 S1C33L03 PRODUCT PART...
Page 31: Ram
The S1C33L03 has a built-in 8KB RAM. The RAM is allocated to Area 0, address 0x0000000 to address 0x0001FFF. The internal RAM is a 32-bit sized device and data can be read/written in 1 cycle regardless of data size (byte, half- word or word). EPSON S1C33L03 PRODUCT PART A-15...
Page 32: Peripheral Circuits
2, 4, 16 or 256-level (1, 2, 4 or 8 bit-per-pixel) color display Resolution examples: 640 480 pixels with 1bpp color depth 640 240 pixels with 2bpp color depth 320 240 pixels with 4bpp color depth 240 160 pixels with 8bpp color depth EPSON A-16 S1C33L03 PRODUCT PART...
Page 33: I/O Memory Map
0, 1: Initial values that are set at initial reset. (However, the registers for the bus and input/output ports are not initialized at hot start.) Not initialized at initial reset. –: Not set in the circuit. EPSON S1C33L03 PRODUCT PART A-17...
Page 34 1 On 0 Off P8TS02 8-bit timer 0 P8TS0[2:0] Division ratio : selected by P8TS01 clock division ratio selection /256 Prescaler clock select P8TS00 /128 register (0x40181) 8-bit timer 0 can generate the DRAM refresh clock. EPSON A-18 S1C33L03 PRODUCT PART...
Page 35 Clock timer 0040154 D7–6 – reserved – – – 0 when being read. second TCMD5 Clock timer second counter data 0 to 59 seconds register TCMD4 TCMD5 = MSB TCMD3 TCMD0 = LSB TCMD2 TCMD1 TCMD0 EPSON S1C33L03 PRODUCT PART A-19...
Page 36 D7–5 – reserved – – – 0 when being read. TCCN4 Clock timer day comparison data 0 to 31 days Compared with comparison TCCN3 TCCN4 = MSB TCND[4:0]. register TCCN2 TCCN0 = LSB TCCN1 TCCN0 EPSON A-20 S1C33L03 PRODUCT PART...
Page 37 RLD20 = LSB RLD24 RLD23 RLD22 RLD21 RLD20 8-bit timer 2 004016A PTD27 8-bit timer 2 counter data 0 to 255 counter data PTD26 PTD27 = MSB register PTD25 PTD20 = LSB PTD24 PTD23 PTD22 PTD21 PTD20 EPSON S1C33L03 PRODUCT PART A-21...
Page 38 RLD50 = LSB RLD54 RLD53 RLD52 RLD51 RLD50 8-bit timer 5 004017A PTD57 8-bit timer 5 counter data 0 to 255 counter data PTD56 PTD57 = MSB register PTD55 PTD50 = LSB PTD54 PTD53 PTD52 PTD51 PTD50 EPSON A-22 S1C33L03 PRODUCT PART...
Page 39 Watchdog 0040171 D7–2 – – – – – 0 when being read. timer enable Watchdog timer enable 1 NMI enabled 0 NMI disabled register – – – – – 0 when being read. EPSON S1C33L03 PRODUCT PART A-23...
Page 40 Writing 10010110 (0x96) protect register CLGP6 removes the write protection of CLGP5 the power control register CLGP4 (0x40180) and the clock option CLGP3 register (0x40190). CLGP2 Writing another value set the CLGP1 write protection. CLGP0 EPSON A-24 S1C33L03 PRODUCT PART...
Page 41 1 Inverted 0 Direct Valid only in IRRL0 Ch.0 IrDA I/F input logic inversion 1 Inverted 0 Direct asynchronous mode. IRMD01 Ch.0 interface mode selection IRMD0[1:0] I/F mode IRMD00 reserved IrDA 1.0 reserved General I/F EPSON S1C33L03 PRODUCT PART A-25...
Page 42 OER2 Ch.2 overrun error flag 1 Error 0 Normal Reset by writing 0. TDBE2 Ch.2 transmit data buffer empty 1 Empty 0 Buffer full RDBF2 Ch.2 receive data buffer full 1 Buffer full 0 Empty EPSON A-26 S1C33L03 PRODUCT PART...
Page 43 1 Inverted 0 Direct Valid only in IRRL3 Ch.3 IrDA I/F input logic inversion 1 Inverted 0 Direct asynchronous mode. IRMD31 Ch.3 interface mode selection IRMD3[1:0] I/F mode IRMD30 reserved IrDA 1.0 reserved General I/F EPSON S1C33L03 PRODUCT PART A-27...
Page 44 Reset by writing 0. A/D sampling 0040245 D7–2 – – – – – 0 when being read. register Input signal sampling time setup ST[1:0] Sampring time Use with 9 clocks. 9 clocks 7 clocks 5 clocks 3 clocks EPSON A-28 S1C33L03 PRODUCT PART...
Page 45 0 when being read. interrupt P16T52 16-bit timer 5 interrupt level 0 to 7 priority register P16T51 P16T50 – reserved – – – 0 when being read. P16T42 16-bit timer 4 interrupt level 0 to 7 P16T41 P16T40 EPSON S1C33L03 PRODUCT PART A-29...
Page 46 0 when being read. interrupt PP7L2 Port input 7 interrupt level 0 to 7 priority register PP7L1 PP7L0 – reserved – – – 0 when being read. PP6L2 Port input 6 interrupt level 0 to 7 PP6L1 PP6L0 EPSON A-30 S1C33L03 PRODUCT PART...
Page 47 – – – 0 when being read. clock timer, Port input 7 1 Enabled 0 Disabled A/D interrupt Port input 6 enable register Port input 5 Port input 4 ECTM Clock timer EADE A/D converter EPSON S1C33L03 PRODUCT PART A-31...
Page 48 0 when being read. clock timer, A/D Port input 7 1 Factor is 0 No factor is interrupt factor Port input 6 generated generated flag register Port input 5 Port input 4 FCTM Clock timer FADE A/D converter EPSON A-32 S1C33L03 PRODUCT PART...
Page 49 DEP4 Port input 4 register – reserved – – – 0 when being read. DEADE A/D converter 1 IDMA 0 IDMA DESTX1 SIF Ch.1 transmit buffer empty enabled disabled DESRX1 SIF Ch.1 receive buffer full EPSON S1C33L03 PRODUCT PART A-33...
Page 50 IDMA enable register set method 1 Set only 0 RD/WR register selection IDMAONLY IDMA request register set method 1 Set only 0 RD/WR selection RSTONLY Interrupt factor flag reset method 1 Reset only 0 RD/WR selection EPSON A-34 S1C33L03 PRODUCT PART...
Page 51 K65 input port data – K64D K64 input port data – K63D K63 input port data – K62D K62 input port data – K61D K61 input port data – K60D K60 input port data – EPSON S1C33L03 PRODUCT PART A-35...
Page 52 0 TM16 Ch.4 RXD Full comp.B SIO2TS1 SIO Ch.2 transmit buffer empty 1 SIO Ch.2 0 TM16 Ch.5 TXD Emp. comp.A SIO2RS1 SIO Ch.2 receive buffer full 1 SIO Ch.2 0 TM16 Ch.5 RXD Full comp.B EPSON A-36 S1C33L03 PRODUCT PART...
Page 53 P16 I/O port data 1 High 0 Low P15D P15 I/O port data P14D P14 I/O port data P13D P13 I/O port data P12D P12 I/O port data P11D P11 I/O port data P10D P10 I/O port data EPSON S1C33L03 PRODUCT PART A-37...
Page 54 P34 I/O control indicates the values IOC33 P33 I/O control of the I/O control IOC32 P32 I/O control signals of the ports IOC31 P31 I/O control when it is read. (See IOC30 P30 I/O control detailed explanation.) EPSON A-38 S1C33L03 PRODUCT PART...
Page 55 1 8 bits 0 16 bits A14DF1 Areas 14–13 A14DF[1:0] Number of cycles A14DF0 output disable delay time – reserved – – – 0 when being read. A14WT2 Areas 14–13 wait control A14WT[2:0] Wait cycles A14WT1 A14WT0 EPSON S1C33L03 PRODUCT PART A-39...
Page 56 1 8 bits 0 16 bits A8DF1 Areas 8–7 A8DF[1:0] Number of cycles A8DF0 output disable delay time – reserved – – – 0 when being read. A8WT2 Areas 8–7 wait control A8WT[2:0] Wait cycles A8WT1 A8WT0 EPSON A-40 S1C33L03 PRODUCT PART...
Page 57 Writing 1 not allowed. SBUSST External interface method selection 1 #BSL 0 A0 SEMAS External bus master setup 1 Existing 0 Nonexistent SEPD External power-down control 1 Enabled 0 Disabled SWAITE #WAIT enable 1 Enabled 0 Disabled EPSON S1C33L03 PRODUCT PART A-41...
Page 58 Fixed at 0 0 when being read. order register (HW) TTBR32 Writing 1 not allowed. TTBR31 TTBR30 TTBR2B Trap table base address [27:16] 0x0C0 TTBR2A TTBR29 TTBR28 TTBR27 TTBR26 TTBR25 TTBR24 TTBR23 TTBR22 TTBR21 TTBR20 EPSON A-42 S1C33L03 PRODUCT PART...
Page 59 A1X1MD Area 1 access-speed 1 2 cycles 0 4 cycles x2 speed mode only – reserved – – 0 when being read. BCLKSEL1 BCLK output clock selection BCLKSEL[1:0] BCLK BCLKSEL0 PLL_CLK OSC3_CLK BCU_CLK CPU_CLK EPSON S1C33L03 PRODUCT PART A-43...
Page 60 1 External clock 0 Internal clock PTM0 16-bit timer 0 clock output control 1 On 0 Off PRESET0 16-bit timer 0 reset 1 Reset 0 Invalid 0 when being read. PRUN0 16-bit timer 0 Run/Stop control 1 Run 0 Stop EPSON A-44 S1C33L03 PRODUCT PART...
Page 61 1 External clock 0 Internal clock PTM1 16-bit timer 1 clock output control 1 On 0 Off PRESET1 16-bit timer 1 reset 1 Reset 0 Invalid 0 when being read. PRUN1 16-bit timer 1 Run/Stop control 1 Run 0 Stop EPSON S1C33L03 PRODUCT PART A-45...
Page 62 1 External clock 0 Internal clock PTM2 16-bit timer 2 clock output control 1 On 0 Off PRESET2 16-bit timer 2 reset 1 Reset 0 Invalid 0 when being read. PRUN2 16-bit timer 2 Run/Stop control 1 Run 0 Stop EPSON A-46 S1C33L03 PRODUCT PART...
Page 63 1 External clock 0 Internal clock PTM3 16-bit timer 3 clock output control 1 On 0 Off PRESET3 16-bit timer 3 reset 1 Reset 0 Invalid 0 when being read. PRUN3 16-bit timer 3 Run/Stop control 1 Run 0 Stop EPSON S1C33L03 PRODUCT PART A-47...
Page 64 1 External clock 0 Internal clock PTM4 16-bit timer 4 clock output control 1 On 0 Off PRESET4 16-bit timer 4 reset 1 Reset 0 Invalid 0 when being read. PRUN4 16-bit timer 4 Run/Stop control 1 Run 0 Stop EPSON A-48 S1C33L03 PRODUCT PART...
Page 65 1 External clock 0 Internal clock PTM5 16-bit timer 5 clock output control 1 On 0 Off PRESET5 16-bit timer 5 reset 1 Reset 0 Invalid 0 when being read. PRUN5 16-bit timer 5 Run/Stop control 1 Run 0 Stop EPSON S1C33L03 PRODUCT PART A-49...
Page 66 0048204 DSTART IDMA start 1 IDMA start 0 Stop register D6–0 DCHN IDMA channel number 0 to 127 IDMA enable 0048205 D7–1 – reserved – – – register IDMAEN IDMA enable 1 Enabled 0 Disabled EPSON A-50 S1C33L03 PRODUCT PART...
Page 67 Inc.(init) Dec.(no init) Note: Fixed D) Dual address S0ADRH11 D) Ch.0 source address[27:16] mode S0ADRH10 S) Ch.0 memory address[27:16] S) Single S0ADRH9 address S0ADRH8 mode S0ADRH7 S0ADRH6 S0ADRH5 S0ADRH4 S0ADRH3 S0ADRH2 S0ADRH1 S0ADRH0 EPSON S1C33L03 PRODUCT PART A-51...
Page 68 DF–1 – reserved – – – Undefined in read. DMA Ch.0 (HW) trigger flag HS0_TF Ch.0 trigger flag clear (writing) 1 Clear 0 No operation register Ch.0 trigger flag status (reading) 1 Set 0 Cleared EPSON A-52 S1C33L03 PRODUCT PART...
Page 69 Inc.(init) Dec.(no init) Note: Fixed D) Dual address S1ADRH11 D) Ch.1 source address[27:16] mode S1ADRH10 S) Ch.1 memory address[27:16] S) Single S1ADRH9 address S1ADRH8 mode S1ADRH7 S1ADRH6 S1ADRH5 S1ADRH4 S1ADRH3 S1ADRH2 S1ADRH1 S1ADRH0 EPSON S1C33L03 PRODUCT PART A-53...
Page 70 DF–1 – reserved – – – Undefined in read. DMA Ch.1 (HW) trigger flag HS1_TF Ch.1 trigger flag clear (writing) 1 Clear 0 No operation register Ch.1 trigger flag status (reading) 1 Set 0 Cleared EPSON A-54 S1C33L03 PRODUCT PART...
Page 71 Inc.(init) Dec.(no init) Note: Fixed D) Dual address S2ADRH11 D) Ch.2 source address[27:16] mode S2ADRH10 S) Ch.2 memory address[27:16] S) Single S2ADRH9 address S2ADRH8 mode S2ADRH7 S2ADRH6 S2ADRH5 S2ADRH4 S2ADRH3 S2ADRH2 S2ADRH1 S2ADRH0 EPSON S1C33L03 PRODUCT PART A-55...
Page 72 DF–1 – reserved – – – Undefined in read. DMA Ch.2 (HW) trigger flag HS2_TF Ch.2 trigger flag clear (writing) 1 Clear 0 No operation register Ch.2 trigger flag status (reading) 1 Set 0 Cleared EPSON A-56 S1C33L03 PRODUCT PART...
Page 73 Inc.(init) Dec.(no init) Note: Fixed D) Dual address S3ADRH11 D) Ch.3 source address[27:16] mode S3ADRH10 S) Ch.3 memory address[27:16] S) Single S3ADRH9 address S3ADRH8 mode S3ADRH7 S3ADRH6 S3ADRH5 S3ADRH4 S3ADRH3 S3ADRH2 S3ADRH1 S3ADRH0 EPSON S1C33L03 PRODUCT PART A-57...
Page 74 DF–1 – reserved – – – Undefined in read. DMA Ch.3 (HW) trigger flag HS3_TF Ch.3 trigger flag clear (writing) 1 Clear 0 No operation register Ch.3 trigger flag status (reading) 1 Set 0 Cleared EPSON A-58 S1C33L03 PRODUCT PART...
Page 75 SDRTRAS2 SDRAM t spec SDRTRAS[2:0] Number of clocks timing set-up SDRTRAS1 register 1 SDRTRAS0 D4–3 SDRTRP1 SDRAM t spec SDRTRP[1:0] Number of clocks SDRTRP0 D2–0 SDRTRC2 SDRAM t spec SDRTRC[2:0] Number of clocks SDRTRC1 SDRTRC0 EPSON S1C33L03 PRODUCT PART A-59...
Page 76 039FFCA SDRMRS SDRAM mode register set flag 1 Not finished 0 Done status register SDRSRM SDRAM current refresh mode 1 Auto refresh 0 Self refresh D5–0 – reserved – – – 0 when being read. EPSON A-60 S1C33L03 PRODUCT PART...
Page 77 V resolution (lines) - 1 register 1 LDVSIZE8 (high-order 2 bits) Horizontal 039FFE7 D7–5 – reserved – – – 0 when being read. non-display HNDP4 Horizontal non-display period Non-display period (pixels) period register HNDP3 HNDP2 HNDP1 HNDP0 EPSON S1C33L03 PRODUCT PART A-61...
Page 78 Memory address offset address offset MADOFS6 register MADOFS5 MADOFS4 MADOFS3 MADOFS2 MADOFS1 MADOFS0 Screen 1 039FFF2 S1VSIZE7 Screen 1 vertical size vertical size S1VSIZE6 (low-order 8 bits) register 0 S1VSIZE5 S1VSIZE4 S1VSIZE3 S1VSIZE2 S1VSIZE1 S1VSIZE0 EPSON A-62 S1C33L03 PRODUCT PART...
Page 79 P: 1/8, M: 1/4 P: 1/4, M: 1/2 P: 1/2, M: 1/1 P: 1/2, M: 1/1 Line byte 039FFFC PMODLBC7 Line byte count count register PMODLBC6 for portrait PMODLBC5 mode PMODLBC4 PMODLBC3 PMODLBC2 PMODLBC1 PMODLBC0 EPSON S1C33L03 PRODUCT PART A-63...
Page 80 (number of wait cycles for SRAM) VRAMWT0 EDMAEN External DMA enable 1 Enabled 0 Disabled BREQEN External bus-request enable 1 Enabled 0 Disabled LCDCST A0/BSL select 1 BSL 0 A0 LCDCEC Big/little endian select 1 Big endian 0 Little endian EPSON A-64 S1C33L03 PRODUCT PART...
Page 81: Power-Down Control
Even during operation using the high-speed (OSC3) oscillation clock, power reduction can also be achieved through the use of a system clock derived from the OSC3 clock by dividing it (1/1, 1/2, 1/4, or 1/8). EPSON S1C33L03 PRODUCT PART A-65...
Page 82 8-bit timer 5 clock control P8TON5(D7)/8-bit timer 4/5 clock control register(0x40145) 8-bit timer 5 Run/Stop PTRUN5(D0)/8-bit timer 5 control register(0x40178) STOP STOP A/D converter clock control PSONAD(D3)/A/D clock control register(0x4014F) A/D conversion enable ADE(D2)/A/D enable register(0x40244) STOP STOP EPSON A-66 S1C33L03 PRODUCT PART...
Page 83 This may cause damage of the LCD panel if the clock supply to the LCD controller is stopped at the same time. Therefore, do not stop the clock supply for 1 frame cycles or more after setting the LCD controller to power save mode. EPSON S1C33L03 PRODUCT PART A-67...
Page 84: Basic External Wiring Diagram
33 MHz (Max.) Gate capacitor 10 pF Drain capacitor 10 pF Feedback resistor Resistor 4.7 k Capacitor 100 pF Capacitor 5 pF Note: The above table is simply an example, and is not guaranteed to work. EPSON A-68 S1C33L03 PRODUCT PART...
Page 85: Precautions On Mounting
• Sudden power supply variation due to noise may cause malfunction. Consider the following points to prevent this: (1) The power supply should be connected to the V and AV pins with patterns as short and large as possible. In particular, the power supply for AV affects A/D conversion precision. EPSON S1C33205 PRODUCT PART A-69...
Page 86 Do not arrange a high-speed signal line especially near circuits that are sensitive to noise such as the oscillation unit and analog input unit. Prohibited pattern K60 (AD0) OSC4 OSC3 Large current signal line High-speed signal line Large current signal line High-speed signal line EPSON A-70 S1C33205 PRODUCT PART...
Page 87: Electrical Characteristics
High-level output current 1 pin Total of all pins Low-level output current 1 pin Total of all pins Analog power voltage -0.3 to +7.0 Analog input voltage -0.3 to AV +0.3 Storage temperature -65 to +150 °C EPSON S1C33L03 PRODUCT PART A-71...
Page 88: Recommended Operating Conditions
– 32.768 – OSC1 Operating temperature °C Input rise time (normal input) – – Input fall time (normal input) – – Input rise time (schmitt input) – – Input fall time (schmitt input) – – EPSON A-72 S1C33L03 PRODUCT PART...
Page 89: Dc Characteristics
Other than DSIO DSIO Pull-down resistor (ICEMD) Input pin capacitance – – f=1MHz, V Output pin capacitance – – f=1MHz, V I/O pin capacitance – – f=1MHz, V Note: See Appendix B for pin characteristics. EPSON S1C33L03 PRODUCT PART A-73...
Page 90 Other than DSIO DSIO Pull-down resistor (ICEMD) Input pin capacitance – – f=1MHz, V Output pin capacitance – – f=1MHz, V I/O pin capacitance – – f=1MHz, V Note: See Appendix B for pin characteristics. EPSON A-74 S1C33L03 PRODUCT PART...
Page 91: Current Consumption
1: The values of current consumption while the CPU is operating were measured when a test program that consists of 55% load instructions, 23% arithmetic operation instructions, 1% mac instruction, 12% branch instructions and 9% ext instruction is being executed in the built-in ROM continuously. 2: The LCD controller is included. EPSON S1C33L03 PRODUCT PART A-75...
Page 92: A/D Converter Characteristics
V[000]h = Ideal voltage at zero-scale point (=0.5LSB) 1LSB = V'[000]h = Actual voltage at zero-scale point V[3FF]h = Ideal voltage at full-scale point (=1022.5LSB) V'[3FF]h - V'[000]h 1LSB' = V'[3FF]h = Actual voltage at full-scale point EPSON A-76 S1C33L03 PRODUCT PART...
Page 93 [LSB] 1LSB' Actual conversion characteristic Ideal conversion characteristic V'[000]h Analog input Differential linearity error Ideal conversion characteristic Actual conversion characteristic V'[N]h V'[N]h - V'[N-1]h Differential linearity error E - 1 [LSB] 1LSB' V'[N-1]h Analog input EPSON S1C33L03 PRODUCT PART A-77...
Page 94: Ac Characteristics
High level = 1/2 V Low level = 1/2 V Input signal waveform: Rise time (10% 90% V ) 5 ns Fall time (90% 10% V ) 5 ns Output load capacitance: C = 50 pF EPSON A-78 S1C33L03 PRODUCT PART...
Page 95: C33 Block Ac Characteristic Tables
Item Symbol Min. Max. Unit BCLK clock output duty 3) 2.0 V single power source (Unless otherwise specified: V =2.0V 0.2V, V =0V, Ta=-40°C to +85°C) Item Symbol Min. Max. Unit BCLK clock output duty EPSON S1C33L03 PRODUCT PART A-79...
Page 96 Write data delay time (2) WDD2 Write data hold time note 1) This applies to the #BSH and #BSL timings. 2) This applies to the #GAAS and #GARD timings. 3) This applies to the #GAAS timing. EPSON A-80 S1C33L03 PRODUCT PART...
Page 97 Write signal pulse width (1+WC)-10 3) 2.0 V single power source (Unless otherwise specified: V =2.0V 0.2V, V =0V, Ta=-40°C to +85°C) Item Symbol Min. Max. Unit Write signal delay time (2) WRD2 Write signal pulse width (1+WC)-20 EPSON S1C33L03 PRODUCT PART A-81...
Page 98 #CAS signal delay time (2) CASD2 #CAS signal pulse width (0.5+WC)-20 CASW Read signal delay time (3) RDD3 Read signal pulse width (2) (2+WC)-20 RDW2 Write signal delay time (3) WRD3 Write signal pulse width (2) (2+WC)-20 WRW2 EPSON A-82 S1C33L03 PRODUCT PART...
Page 99 (Unless otherwise specified: V =2.0V 0.2V, V =0V, Ta=-40°C to +85°C) Item Symbol Min. Max. Unit Column address access time (1.5+WC)-60 ACCE #RAS access time (2+WC)-60 RACE #CAS access time (1+WC)-60 CACE Read data setup time RDS2 EPSON S1C33L03 PRODUCT PART A-83...
Page 100 #SDWE signal delay time (2) T+11 (WEDx2)p Read data setup time (14) (RDSx2) Read data hold time (RDHx2) Write data delay time (WDDx2) Write data hold time T+11 (WDHx2) Note: "T" indicates one cycle time of the CPU clock. EPSON A-84 S1C33L03 PRODUCT PART...
Page 101 =0V, Ta=-40°C to +85°C) Item Symbol Min. Max. Unit #BUSREQ signal setup time BRQS #BUSREQ signal hold time BRQH #BUSACK signal output delay time BAKD High-impedance output delay time Output high-impedance delay time #NMI pulse width NMIW EPSON S1C33L03 PRODUCT PART A-85...
Page 102 =2.0V 0.2V, V =0V, Ta=-40°C to +85°C) Item Symbol Min. Max. Unit Input data setup time INPS Input data hold time INPH Output data delay time OUTD K-port interrupt SLEEP, HALT2 mode KINW input pulse width Others EPSON A-86 S1C33L03 PRODUCT PART...
Page 103: C33 Block Ac Characteristic Timing Charts
8.6.4 C33 Block AC Characteristic Timing Charts Clock (1) When an external clock is input (in x1 speed mode): OSC3 C3ED (High-speed clock) BCLK (Clock output) (2) When the high-speed oscillation circuit is used for the operating clock: BCLK (Clock output) EPSON S1C33L03 PRODUCT PART A-87...
Page 104 SRAM read cycle (when a wait cycle is inserted) (wait cycle) (last cycle) BCLK A[23:0] #CEx (C1 only) RDD1 RDD2 CEAC1 ACC1 RDAC1 D[15:0] #WAIT is measured with respect to the first signal change (negation) from among the #RD, #CEx and A[23:0] signals. EPSON A-88 S1C33L03 PRODUCT PART...
Page 105 A[23:0] #CEx WRD1 WRD2 WDD1 D[15:0] #WAIT SRAM write cycle (when wait cycles are inserted) (wait cycle) (wait cycle) (last cycle) Wait cycle follows Last cycle follows BCLK A[23:0] #CEx WRD1 WRD2 WDD1 D[15:0] #WAIT EPSON S1C33L03 PRODUCT PART A-89...
Page 106 #HCAS/ #LCAS RDD1 RDD3 RDW2 CACF ACCF RACF ACCF D[15:0] WRD1 WRD3 WRW2 WDD1 WDD2 WDD2 D[15:0] is measured with respect to the first signal change (negation) of either the #RD or the A[23:0] signals. EPSON A-90 S1C33L03 PRODUCT PART...
Page 107 RDD1 RDD3 RDW2 ACCE CACE RACE ACCE D[15:0] WRD1 WRD3 WRW2 WDD1 WDD2 WDD2 D[15:0] is measured with respect to the first signal change from among the #RD (negation), #RASx (negation) and #CAS (fall) signals. EPSON S1C33L03 PRODUCT PART A-91...
Page 108 (1) #X2SPD = high (CPU clock : SDRAM clock = 1 : 1) OSC3 (High-speed clock) BCLK (SDRAM clock output) (2) #X2SPD = low (CPU clock : SDRAM clock = 2 : 1) BCLK (SDRAM clock output) EPSON A-92 S1C33L03 PRODUCT PART...
Page 109 Read: CAS latency = 2, burst length = 2 Write: single write SDRAM mode-register-set cycle Mode register set BCLK SDCKE A[23:0] valid SDA10 valid CED1 CED2 #SDCEx RASD1 RASD2 #SDRAS CASD1 CASD2 #SDCAS WED1 WED2 #SDWE D[15:0] HDQM/ LDQM EPSON S1C33L03 PRODUCT PART A-93...
Page 110 Enter self refresh mode Exit self refresh mode BCLK CKE1 CKE2 SDCKE A[23:0] SDA10 CED1 CED2 #SDCEx RASD1 #SDRAS CASD1 #SDCAS WED1 #SDWE D[15:0] HDQM/ LDQM A precharge cycle is necessary before entering the self refresh mode. EPSON A-94 S1C33L03 PRODUCT PART...
Page 111 A[23:0], #RD, #WRL, #WRH, #HCAS, #LCAS, #CE[17:4], D[15:0] Input, output and I/O port timing BCLK INPS INPH Kxx, Pxx (input: data read Valid input from the port) OUTD Pxx, Rxx (output) KINW (K-port interrupt input) EPSON S1C33L03 PRODUCT PART A-95...
Page 112: Lcd Interface Ac Characteristics
Power Save active to LCDPWR inactive Frame Power Save active to FPLINE, FPFRAME, FPSHIFT, FPDAT, DRDY Frame inactive LPWREN = "1" to LCDPWR active Frame (when FP signals are active) LPWREN = "0" to LCDPWR inactive Frame EPSON A-96 S1C33L03 PRODUCT PART...
Page 113 VNDP = Vertical Non-Display Period = VNDP[5:0] (lines) VNDP[5:0] (D[5:0]/0x39FFEA) = Horizontal Display Period = (LDHSIZE[5:0] + 1) 16 (Ts) LDHSIZE[5:0] (D[5:0]/0x39FFE4) HNDP = Horizontal Non-Display Period = (HNDP[4:0] + 4) 8 (Ts) HNDP[4:0] (D[4:0]/0x39FFE7) EPSON S1C33L03 PRODUCT PART A-97...
Page 114 = pixel clock period - 9 (Ts) 1min 3min = (LDHSIZE[5:0] + 1) 16 + (HNDP[4:0] + 4) 8 (Ts) 3min = HNDP[4:0] 8 + 2 (Ts) 6min = HNDP[4:0] 8 + 11 (Ts) 7min EPSON A-98 S1C33L03 PRODUCT PART...
Page 115 VNDP = Vertical Non-Display Period = VNDP[5:0] (lines) VNDP[5:0] (D[5:0]/0x39FFEA) = Horizontal Display Period = (LDHSIZE[5:0] + 1) 16 (Ts) LDHSIZE[5:0] (D[5:0]/0x39FFE4) HNDP = Horizontal Non-Display Period = (HNDP[4:0] + 4) 8 (Ts) HNDP[4:0] (D[4:0]/0x39FFE7) EPSON S1C33L03 PRODUCT PART A-99...
Page 116 = pixel clock period - 9 (Ts) 1min 3min = (LDHSIZE[5:0] + 1) 16 + (HNDP[4:0] + 4) 8 (Ts) 3min = HNDP[4:0] 8 + 4 (Ts) 6min = HNDP[4:0] 8 + 13 (Ts) 7min EPSON A-100 S1C33L03 PRODUCT PART...
Page 117 VNDP = Vertical Non-Display Period = VNDP[5:0] (lines) VNDP[5:0] (D[5:0]/0x39FFEA) = Horizontal Display Period = (LDHSIZE[5:0] + 1) 16 (Ts) LDHSIZE[5:0] (D[5:0]/0x39FFE4) HNDP = Horizontal Non-Display Period = (HNDP[4:0] + 4) 8 (Ts) HNDP[4:0] (D[4:0]/0x39FFE7) EPSON S1C33L03 PRODUCT PART A-101...
Page 118 = pixel clock period - 9 (Ts) 1min 3min = (LDHSIZE[5:0] + 1) 16 + (HNDP[4:0] + 4) 8 (Ts) 3min = HNDP[4:0] 8 + 1.5 (Ts) 6min = HNDP[4:0] 8 + 10.5 (Ts) 7min EPSON A-102 S1C33L03 PRODUCT PART...
Page 119 VNDP = Vertical Non-Display Period = VNDP[5:0] (lines) VNDP[5:0] (D[5:0]/0x39FFEA) = Horizontal Display Period = (LDHSIZE[5:0] + 1) 16 (Ts) LDHSIZE[5:0] (D[5:0]/0x39FFE4) HNDP = Horizontal Non-Display Period = (HNDP[4:0] + 4) 8 (Ts) HNDP[4:0] (D[4:0]/0x39FFE7) EPSON S1C33L03 PRODUCT PART A-103...
Page 120 3min = HNDP[4:0] 8 + t + 1 (Ts) 6amin = HNDP[4:0] 8 + t + 1 (Ts) 6bmin = HNDP[4:0] 8 + 11 (Ts) 7amin = HNDP[4:0] 8 + 11 - t (Ts) 7bmin EPSON A-104 S1C33L03 PRODUCT PART...
Page 121 VNDP = Vertical Non-Display Period = VNDP[5:0] (lines) VNDP[5:0] (D[5:0]/0x39FFEA) = Horizontal Display Period = (LDHSIZE[5:0] + 1) 16 (Ts) LDHSIZE[5:0] (D[5:0]/0x39FFE4) HNDP = Horizontal Non-Display Period = (HNDP[4:0] + 4) 8 (Ts) HNDP[4:0] (D[4:0]/0x39FFE7) EPSON S1C33L03 PRODUCT PART A-105...
Page 122 = pixel clock period - 9 (Ts) 1min 3min = (LDHSIZE[5:0] + 1) 16 + (HNDP[4:0] + 4) 8 + 1 (Ts) 3min = HNDP[4:0] 8 + 1 (Ts) 6min = HNDP[4:0] 8 + 10 (Ts) 7min EPSON A-106 S1C33L03 PRODUCT PART...
Page 123: Oscillation Characteristics
Operating temperature =2.7V to 3.6V °C =1.9V to 2.2V °C =1.8V to 2.2V °C #1 Q11C02RX: Crystal resonator made by Seiko Epson #2 "C =15pF" includes board capacitance. (Unless otherwise specified: V =3.3V, V =0V, crystal=Q11C02RX 32.768kHz, =20M , C =15pF , Ta=25°C)
Page 124: Pll Characteristics
Symbol Condition Min. Typ. Max. Unit Jitter (peak jitter) Lockup time #1 Q3204DC: Crystal oscillator made by Seiko Epson (Unless otherwise specified: V =2.0V 0.2V, V =0V, crystal oscillator=Q3204DC =4.7k , C =100pF, C =5pF, Ta=-40°C to +85°C) Item Symbol Condition Min.
Page 125: Package
This thermal resistance is a value under the condition that the measured device is hanging in the air and has no air-cooling. Thermal resistance greatly varies according to the mounting condition on the board and air- cooling condition. EPSON S1C33L03 PRODUCT PART A-109...
Page 126: Pad Layout
10 PAD LAYOUT 10 Pad Layout 10.1 Pad Layout Diagram Die No. (0, 0) 5.97 mm EPSON A-110 S1C33L03 PRODUCT PART...
Page 127: Pad Coordinate
-1870.0 P16/EXCL5/#DMAEND1/SOUT3 770.0 2549.5 K52/#ADTRG 2843.5 -1760.0 P15/EXCL4/#DMAEND0/#SCLK3/LDQM 660.0 2549.5 K51/#DMAREQ1 2843.5 -1650.0 A0/#BSL 550.0 2549.5 K50/#DMAREQ0 2843.5 -1540.0 A1/SDA0 440.0 2549.5 #WRH/#BSH 2843.5 -1430.0 A2/SDA1 330.0 2549.5 #WRL/#WR/#WE 2843.5 -1320.0 100 A3/SDA2 220.0 2549.5 EPSON S1C33L03 PRODUCT PART A-111...
Page 128 1760.0 156 P03/#SRDY0 -2843.5 -1540.0 127 PLLS1 -2843.5 1650.0 157 P02/#SCLK0 -2843.5 -1650.0 128 PLLS0 -2843.5 1540.0 158 N.C. -2843.5 -1760.0 129 V -2843.5 1430.0 159 P01/SOUT0 -2843.5 -1870.0 130 PLLC -2843.5 1320.0 160 P00/SIN0 -2843.5 -1980.0 EPSON A-112 S1C33L03 PRODUCT PART...
Page 129: Appendix A External Device Interface Timings
Conditions such as the output delay time of the device, delay due to wiring and load capacitance, and input setup time are not considered. • The described contents are reference data and cannot be guaranteed to work. EPSON S1C33L03 PRODUCT PART A-113...
Page 130: Dram (70Ns
Fast-page mode #CAS precharge time – Access time after #CAS precharge <Refresh cycle> – #CAS setup time – #CAS hold time – #RAS precharge #CAS hold time 10000 #RAS pulse width (only in refresh cycle) EPSON A-114 S1C33L03 PRODUCT PART...
Page 131 COL #1 COL #2 #RAS #CAS D[15:0](RD) RD data RD data D[15:0](WR) WR data WR data DRAM: 70ns, CPU: 33MHz, CAS-before-RAS refresh cycle RPC delay Fixed Refresh RAS pulse width RAS precharge BCLK #RAS #CAS EPSON S1C33L03 PRODUCT PART A-115...
Page 132 COL #1 COL #2 #RAS #CAS D[15:0](RD) RD data RD data D[15:0](WR) WR data WR data DRAM: 70ns, CPU: 25/20MHz, CAS-before-RAS refresh cycle RPC delay Fixed Refresh RAS pulse width RAS precharge BCLK #RAS #CAS EPSON A-116 S1C33L03 PRODUCT PART...
Page 133: Dram (60Ns
Fast-page mode #CAS precharge time – Access time after #CAS precharge <Refresh cycle> – #CAS setup time – #CAS hold time – #RAS precharge #CAS hold time 10000 #RAS pulse width (only in refresh cycle) EPSON S1C33L03 PRODUCT PART A-117...
Page 134 COL #1 COL #2 #RAS #CAS D[15:0](RD) RD data RD data D[15:0](WR) WR data WR data DRAM: 60ns, CPU: 33MHz, CAS-before-RAS refresh cycle RPC delay Fixed Refresh RAS pulse width RAS precharge BCLK #RAS #CAS EPSON A-118 S1C33L03 PRODUCT PART...
Page 135 COL #1 COL #2 #RAS #CAS D[15:0](RD) RD data RD data D[15:0](WR) WR data WR data DRAM: 60ns, CPU: 25MHz, CAS-before-RAS refresh cycle RPC delay Fixed Refresh RAS pulse width RAS precharge BCLK #RAS #CAS EPSON S1C33L03 PRODUCT PART A-119...
Page 136 COL #1 COL #2 #RAS #CAS D[15:0](RD) RD data RD data D[15:0](WR) WR data WR data DRAM: 60ns, CPU: 20MHz, CAS-before-RAS refresh cycle RPC delay Fixed Refresh RAS pulse width RAS precharge BCLK #RAS #CAS EPSON A-120 S1C33L03 PRODUCT PART...
Page 137: Rom And Burst Rom
ROM: 100ns, CPU: 33MHz, normal read BCLK A[23:0] #CE9, 10 D[15:0] RD data ROM: 100ns, CPU: 33MHz, burst read BCLK Normal read cycle Burst read cycle A[23:0] #CE9, 10 RD data RD data RD data RD data D[15:0] EPSON S1C33L03 PRODUCT PART A-121...
Page 138 ROM: 100ns, CPU: 20MHz, normal read BCLK A[23:0] #CE9, 10 D[15:0] RD data ROM: 100ns, CPU: 20MHz, burst read BCLK Normal read cycle Burst read cycle A[23:0] #CE9, 10 RD data RD data RD data RD data D[15:0] EPSON A-122 S1C33L03 PRODUCT PART...
Page 139: Sram (55Ns
Write pulse width – Input data setup time – Input data hold time SRAM: 55ns, CPU: 33/25MHz, read cycle BCLK A[23:0] #CEx RD data D[15:0] SRAM: 55ns, CPU: 33/25MHz, write cycle BCLK A[23:0] #CEx D[15:0] WR data EPSON S1C33L03 PRODUCT PART A-123...
Page 140 APPENDIX A <REFERENCE> EXTERNAL DEVICE INTERFACE TIMINGS SRAM: 55ns, CPU: 20MHz, read cycle BCLK A[23:0] #CEx RD data D[15:0] SRAM: 55ns, CPU: 20MHz, write cycle BCLK A[23:0] #CEx D[15:0] WR data EPSON A-124 S1C33L03 PRODUCT PART...
Page 141: Sram (70Ns
Write pulse width – Input data setup time – Input data hold time SRAM: 70ns, CPU: 33MHz, read cycle BCLK A[23:0] #CEx RD data D[15:0] SRAM: 70ns, CPU: 33MHz, write cycle BCLK A[23:0] #CEx D[15:0] WR data EPSON S1C33L03 PRODUCT PART A-125...
Page 142 APPENDIX A <REFERENCE> EXTERNAL DEVICE INTERFACE TIMINGS SRAM: 70ns, CPU: 25/20MHz, read cycle BCLK A[23:0] #CEx RD data D[15:0] SRAM: 70ns, CPU: 25/20MHz, write cycle BCLK A[23:0] #CEx D[15:0] WR data EPSON A-126 S1C33L03 PRODUCT PART...
Page 143: 8255A
3 If the data hold time that can be set is not sufficient for the device, secure it by connecting a bus repeater to the external data bus D[15:0] or by inserting a latch at the output side of the external system interface. EPSON S1C33L03 PRODUCT PART...
Page 144: Appendix B Pin Characteristics
Pull-up K50/#DMAREQ0 XHIBHP2 CMOS/LVTTL SCHMITT Pull-up #WRH/#BSH XHBC1T note 3 Type1 #WRL/#WR/#WE XHBC1T note 3 Type1 XHBC1T note 3 Type1 XHBC1T CMOS/LVTTL Type1 XHBC1T CMOS/LVTTL Type1 XHBC1T CMOS/LVTTL Type1 XHBC1T CMOS/LVTTL Type1 XHBC1T CMOS/LVTTL Type1 EPSON A-128 S1C33L03 PRODUCT PART...
Page 145 A7/SDA6 XHBC1T note 3 Type1 A8/SDA7 XHBC1T note 3 Type1 A9/SDA8 XHBC1T note 3 Type1 A10/SDA9 XHBC1T note 3 Type1 XHBC1T note 3 Type1 A12/SDA11 XHBC1T note 3 Type1 100 A13/SDA12 XHBC1T note 3 Type1 EPSON S1C33L03 PRODUCT PART A-129...
Page 146 The following table lists output current characteristics. Output current (I 5.0 V 3.3 V 2.0 V Type1 3 mA 2 mA 0.6 mA Type2 – 6 mA 2 mA Type3 12 mA 12 mA 4 mA EPSON A-130 S1C33L03 PRODUCT PART...
Page 147 S1C33L03 FUNCTION PART...
Page 149: Ioutline
S1C33L03 FUNCTION PART I OUTLINE...
Page 151: Introduction
I OUTLINE: INTRODUCTION I-1 INTRODUCTION The Function Part gives a detailed description of the various function blocks built into the Seiko Epson original 32-bit microcomputer S1C33L03. The S1C33L03 employs a RISC type CPU, and has a powerful instruction set capable of compilation into compact code, despite the small CPU core size.
Page 152 I OUTLINE: INTRODUCTION THIS PAGE IS BLANK. EPSON B-I-1-2 S1C33L03 FUNCTION PART...
Page 153: Block Diagram
C33 Core Block C33_ADC C33_PERI Pads (A/D converter) (Prescaler, 8-bit timer, 16-bit timer, Clock timer, Serial interface, Ports) C33 Analog Block C33 Peripheral Block Figure 2.1 Block Configuration Note: Internal ROM is not provided in the S1C33L03. EPSON S1C33L03 FUNCTION PART B-I-2-1...
Page 154 The LCD Controller Block provides LCD control signals for a 4- or 8-bit color/monochrome LCD panel. C33 Memory Block The S1C33L03 contains an 8KB of SRAM as the internal memory. For details of the blocks, refer to the respective section in this manual. EPSON B-I-2-2 S1C33L03 FUNCTION PART...
Page 155: List Of Pins
Write (low byte) signal when SBUSST(D3/0x4812E) = "0" (default) #WR: Write signal when SBUSST(D3/0x4812E) = "1" #WE: DRAM write signal #WRH – #WRH: Write (high byte) signal when SBUSST(D3/0x4812E) = "0" (default) #BSH #BSH: Bus strobe (high byte) signal when SBUSST(D3/0x4812E) = "1" EPSON S1C33L03 FUNCTION PART B-I-3-1...
Page 156 Area read signal output for GA when CFEX3(D3/0x402DF) = "1" GPIO2: LCDC general-purpose I/O when LCDCEN(D5/0x39FFE3) = "1" and BREQEN(D2/0x39FFFD) = "0" EA10MD1 Pull-up Area 10 boot mode selection EA10MD1 EA10MD0 Mode EA10MD0 – External ROM mode Internal ROM mode EPSON B-I-3-2 S1C33L03 FUNCTION PART...
Page 157 I/O port when CFP07(D7/0x402D0) = "0" and CFEX7(D7/0x402DF) = "0" #SRDY1 (default) #DMAEND3 #SRDY1: Serial I/F Ch. 1 ready signal output when CFP07(D7/0x402D0) = "1" and CFEX5(D5/0x402DF) = "0" #DMAEND3: HSDMA Ch. 3 end-of-transfer signal output when CFEX7(D7/0x402DF) = "1" EPSON S1C33L03 FUNCTION PART B-I-3-3...
Page 158 16-bit timer 0 event counter input when CFP10(D0/0x402D4) = "1", T8UF0 IOC10(D0/0x402D6) = "0" and CFEX1(D1/0x402DF) = "0" DST0 T8UF0: 8-bit timer 0 output when CFP10(D0/0x402D4) = "1", IOC10(D0/0x402D6) = "1" and CFEX1(D1/0x402DF) = "0" DST0: DST0 signal output when CFEX1(D1/0x402DF) = "1" (default) EPSON B-I-3-4 S1C33L03 FUNCTION PART...
Page 159 CFP24(D4/0x402D8) = "0" – P25: I/O port when CFP25(D5/0x402D8) = "0" (default) TM3: 16-bit timer 3 output when CFP25(D5/0x402D8) = "1" #SCLK2 #SCLK2: Serial I/F Ch. 2 clock input/output when SSCLK2(D2/0x402DB) = "1" and CFP25(D5/0x402D8) = "0" EPSON S1C33L03 FUNCTION PART B-I-3-5...
Page 160 – P35: I/O port when CFP35(D5/0x402DC) = "0" (default) #BUSACK #BUSACK: Bus acknowledge output when CFP35(D5/0x402DC) = "1" and GPIO1 CFP34(D4/0x402DC) = "1" GPIO1: LCDC general-purpose I/O when LCDCEN(D5/0x39FFE3) = "1" and BREQEN(D2/0x39FFFD) = "0" EPSON B-I-3-6 S1C33L03 FUNCTION PART...
Page 161 1: CPU clock = bus clock 1, 0: CPU clock = bus clock #NMI Pull-up NMI request input pin #RESET Pull-up Initial reset input pin Note: "#" in the pin names indicates that the signal is low active. EPSON S1C33L03 FUNCTION PART B-I-3-7...
Page 162 I OUTLINE: LIST OF PINS THIS PAGE IS BLANK. EPSON B-I-3-8 S1C33L03 FUNCTION PART...
Page 163: Core Block
S1C33L03 FUNCTION PART II CORE BLOCK...
Page 165: Introduction
C33 Core Block C33_ADC C33_PERI Pads (A/D converter) (Prescaler, 8-bit timer, 16-bit timer, Clock timer, Serial interface, Ports) C33 Analog Block C33 Peripheral Block Figure 1.1 Core Block Note: Internal ROM is not provided in the S1C33L03. EPSON S1C33L03 FUNCTION PART B-II-1-1...
Page 166 II CORE BLOCK: INTRODUCTION THIS PAGE IS BLANK. EPSON B-II-1-2 S1C33L03 FUNCTION PART...
Page 167: Cpu And Operating Mode
User Logic Block. Refer to the "S1C33000 Core CPU Manual" for details of the S1C33000. B-II EPSON S1C33L03 FUNCTION PART B-II-2-1...
Page 168: Standby Mode
Note that SLEEP mode cannot be canceled with an interrupt factor except for reset and NMI if the PSR is set into interrupt disabled status. EPSON B-II-2-2 S1C33L03 FUNCTION PART...
Page 169: Notes On Standby Mode
In the debug mode, the OSC3 clock is used as the CPU operating clock. Therefore, do not stop the high-speed (OSC3) oscillation circuit when using the debugging functions. Furthermore, only the CPU and BCU operate in the debug mode, and other internal peripheral circuits (except the oscillation circuit) stop operating. EPSON S1C33L03 FUNCTION PART B-II-2-3...
Page 170: Trap Table
– – 50(Base+C8) 16-bit programmable timer 5 Timer 5 comparison B 51(Base+CC) Timer 5 comparison A 52(Base+D0) 8-bit programmable timer Timer 0 underflow 53(Base+D4) Timer 1 underflow 54(Base+D8) Timer 2 underflow 55(Base+DC) Timer 3 underflow EPSON B-II-2-4 S1C33L03 FUNCTION PART...
Page 171 Edge (rising or falling) or level (High or Low) 71(Base+11C) Port input interrupt 7 Edge (rising or falling) or level (High or Low) Base = Set value in the TTBR register (0x48134 to 0x48137); 0xC00000 by default. B-II EPSON S1C33L03 FUNCTION PART B-II-2-5...
Page 172 II CORE BLOCK: CPU AND OPERATING MODE THIS PAGE IS BLANK. EPSON B-II-2-6 S1C33L03 FUNCTION PART...
Page 173: Initial Reset
#NMI must be set to high longer than #NMI must be set to low longer than the reset pulse width. the reset pulse width. (1) Cold start (2) Hot start Figure 3.1 Setup of #RESET and #NMI Pins EPSON S1C33L03 FUNCTION PART B-II-3-1...
Page 174: Power-On Reset
To reset the chip when the high-speed (OSC3) oscillation circuit is in off status, the pulse width must be extended until the oscillation stabilizes similarly to the power-on reset. Be aware that a short reset pulse may cause an operation error. EPSON B-II-3-2 S1C33L03 FUNCTION PART...
Page 175: Boot Address
(cold start or hot start). Therefore, it is necessary to set up the peripheral circuit conditions. Refer to the I/O maps or explanation of each peripheral circuit section for initial settings of the peripheral circuits. EPSON S1C33L03 FUNCTION PART B-II-3-3...
Page 176 II CORE BLOCK: INITIAL RESET THIS PAGE IS BLANK. EPSON B-II-3-4 S1C33L03 FUNCTION PART...
Page 177: Bcu (Bus Control Unit)
/ Serial I/F Ch. 3 clock input/output / SDRAM data (low byte) input/output mask signal output #X2SPD CPU - BCLK clock ratio 1: CPU clock = Bus clock, 0: CPU clock = Bus clock x 2 EA10MD[1:0] Area 10 boot mode selection 11: External ROM, 10: Internal ROM EPSON S1C33L03 FUNCTION PART B-II-4-1...
Page 178 The user logic can also be used as input ports with these signals. The internal bus signals are available when an internal access area is set using the BCU register. The bus conditions can be programmed using the BCU registers similar to the external bus. EPSON B-II-4-2 S1C33L03 FUNCTION PART...
Page 179: Combination Of System Bus Control Signals
1 In the #BSL system, the A0 and #WRH pin functions change according to the endian selected (little endian or big endian). When using DRAM, the #CE output pins in areas 7–8 (areas 13–14) function as the #RAS1–2 (#RAS3–4) pins. EPSON S1C33L03 FUNCTION PART B-II-4-3...
Page 180: Memory Area
Note: Addresses 0x39FFC0–0x39FFCD in Area 6 are reserved as the internal memory area for the control I/O memory of the SDRAM controller. Pay attention to this area since it must be accessed when controlling the SDRAM self-refresh mode or other SDRAM functions. EPSON B-II-4-4 S1C33L03 FUNCTION PART...
Page 181: External Memory Map And Chip Enable
Area 4 (#CE4) 0x01FFFFF 0x03FFFFF External I/O (16-bit device) SRAM type SRAM type 0x0380000 External memory 1 (1MB) 8 or 16 bits 0x037FFFF External I/O (8-bit device) 0x0100000 0x0300000 CEFUNC = "00" CEFUNC = "01" EPSON S1C33L03 FUNCTION PART B-II-4-5...
Page 182 The P30 and P34 terminals are set for the general I/O ports at initial reset. The P30 and P34 terminals are shared with the #WAIT input and the #BUSREQ input, respectively. Therefore, when using the #WAIT and #BUSREQ signals, these terminals cannot be used for #CE4+#CE5 and #CE6 outputs. EPSON B-II-4-6 S1C33L03 FUNCTION PART...
Page 183: Using Internal Memory On External Memory Area
CFEX3 (D3)/Port function extension register (0x402DF) = "1" These signals are common used to all the above areas, so when two or more areas are selected to output the exclusive signal, OR condition is applied. EPSON S1C33L03 FUNCTION PART B-II-4-7...
Page 184: Area 10
A10IR[2:0] (D[E:C)/Areas 10–9 set-up register (0x48126). Table 4.7 Area 10 Internal ROM Size A10IR2 A10IR1 A10IR0 ROM size 16 KB 32 KB 64 KB 128 KB 256 KB 512 KB 1 MB 2 MB (default) EPSON B-II-4-8 S1C33L03 FUNCTION PART...
Page 185: Area 3
Area 3 is reserved for S1C33 middleware. To use this area, external emulation memory is used. When external emulation memory is used, A3EEN (DB/0x48130) must be set to "1". Table 4.8 Area 3 Mode Selection A3EEN Area 3 mode Emulation mode Unused EPSON S1C33L03 FUNCTION PART B-II-4-9...
Page 186: Setting External Bus Conditions
Note: The BCU supports 16-bit burst ROM. Therefore, when connecting burst ROM to area 10 or area 9, do not set the device size to 8 bits (A10SZ = "1"). For differences in bus operation due to the device size and access data size, refer to "Bus Operation of External Memory". EPSON B-II-4-10 S1C33L03 FUNCTION PART...
Page 187: Setting Sram Timing Conditions
If the number of wait cycles set is 2 or more, the bus cycle is actually extended. In this case, the bus write cycle consists of [number of wait cycles + 1], as in the case of read cycles (providing that there is no external wait). EPSON S1C33L03 FUNCTION PART B-II-4-11...
Page 188: Setting Timing Conditions Of Burst Rom
RBST8 (DD) / Bus control register (0x4812E) is used for this selection. The eight-consecutive-burst mode is selected by writing "1" to RBST8 and the four-consecutive-burst mode is selected by setting the bit to "0". At cold start, the four-consecutive-burst mode is set by default. EPSON B-II-4-12 S1C33L03 FUNCTION PART...
Page 189: Bus Operation
(1) For data reads, the operation is as shown in the figure below. (2) For little-endian data writes, read A0 as #BSC, and #WRH as #BSH. (3) For big-endian data writes, read A0 as #BSL, and #WRL as #BSH. EPSON S1C33L03 FUNCTION PART B-II-4-13...
Page 190 Destination (general-purpose register) Bus operation Sign or Zero extension Byte 1 Byte 0 Data bus #WRH #WRL Byte 1 Byte 0 A[1:0]= 0 Source (16-bit device) Figure 4.8 Half-word Data Reading from a 16-bit Device EPSON B-II-4-14 S1C33L03 FUNCTION PART...
Page 191 Byte 1 Byte 0 Data bus #WRH #WRL Byte 3 Ignored Byte 2 Ignored A[1:0]=00 A[1:0]=01 A[1:0]=10 A[1:0]=11 Byte 1 Ignored Source (8-bit device) Byte 0 Ignored Figure 4.12 Word Data Reading from an 8-bit Device EPSON S1C33L03 FUNCTION PART B-II-4-15...
Page 192 Source (8-bit device) Big-endian Destination (general-purpose register) Bus operation Sign or Zero extension Byte 0 Data bus #WRH #WRL Byte 0 Ignored A[1:0]= Source (8-bit device) Figure 4.16 Byte Data Reading from an 8-bit Device EPSON B-II-4-16 S1C33L03 FUNCTION PART...
Page 193: Bus Clock
SD_CLK (SDRCLK = "1") SD_CLK (SDRCLK = "0") SDCKE Self refresh 1 Access to the internal RAM 2 Access to the external memory (other than SDRAM) 3 Access to the SDRAM Figure 4.17 Clock System EPSON S1C33L03 FUNCTION PART B-II-4-17...
Page 194: Bus Speed Mode
SDRAM control register (0x39FFC1). Table 4.14 Selection of BCLK Output Clock SDRENA BCLKSEL1 BCLKSEL0 Output clock PLL_CLK (PLL output clock) OSC3_CLK (OSC3 oscillation clock) BCU_CLK (BCU operating clock) CPU_CLK (CPU operating clock) – – SD_CLK (SDRAM clock) EPSON B-II-4-18 S1C33L03 FUNCTION PART...
Page 195: Bus Cycles In External System Interface
(high level), the read cycle is terminated. Note: Insertion of wait cycles via the #WAIT pin is possible only when the device for bus conditions is set for SRAM, and SWAITE (D0) / Bus control register (0x4812E) is enabled for waiting. EPSON S1C33L03 FUNCTION PART B-II-4-19...
Page 196: Bus Timing
With an output disable cycle, there is normally a gap between one read cycle and the next. Note, however, that this output disable cycle is not inserted in the case of consecutive reads in a memory area for which the same chip enable signal is output. EPSON B-II-4-20 S1C33L03 FUNCTION PART...
Page 197: Sram Write Cycles
Figure 4.23 Byte Write Cycle with No Wait (A0 system, little endian) BCLK addr A[23:0] #CExx #BSH #BSL #WRL Undefined Valid D[15:8] Valid Undefined D[7:0] Figure 4.24 Byte Write Cycle with No Wait (#BSL system, little endian) EPSON S1C33L03 FUNCTION PART B-II-4-21...
Page 198 In this case, the bus write cycle consists of [number of wait cycles + 1], as in the case of read cycles (providing that there is no external wait). EPSON B-II-4-22 S1C33L03 FUNCTION PART...
Page 199: Burst Rom Read Cycles
If area 10 or 9 is set for burst ROM, a SRAM write cycle is executed when a write to that area is attempted. In this case, wait cycles via the #WAIT pin can be inserted. EPSON S1C33L03 FUNCTION PART...
Page 200: Dram Direct Interface
(256K bytes) 5 DRAM (4M) DRAM (4M) 8M bits (1M bytes) 6 DRAM (16M) DRAM (16M) 32M bits (4M bytes) Also, the S1C33L03 provides an SDRAM direct interface. Refer to "VI SDRAM Controller Block" for details. EPSON B-II-4-24 S1C33L03 FUNCTION PART...
Page 201: Dram Setting Conditions
If the successive RAS mode is suspended, a precharge cycle is inserted before the next bus cycle begins. Note: When using the successive RAS mode, always be sure to use #DRD for the read signal and #DWE for the low-byte write signal. EPSON S1C33L03 FUNCTION PART B-II-4-25...
Page 202 RPC2 to "0". If RPC1 is switched over when RPC2 = "1" (refresh enabled), an undesirable self-refresh cycle is generated. So be sure to clear RPC2 to "0" (refresh disabled) before selecting the refresh method. EPSON B-II-4-26 S1C33L03 FUNCTION PART...
Page 203 Use RASC to choose the number of RAS cycles when accessing DRAM. Table 4.22 Number of RAS Cycles RASC1 RASC0 Number of cycles 4 cycles 3 cycles 2 cycles 1 cycle The initial default value is 1 cycle. EPSON S1C33L03 FUNCTION PART B-II-4-27...
Page 204: Dram Read/Write Cycles
BCLK COL #1 COL #2 A[11:0] #RASx #HCAS/ #LCAS data data D[15:0] Figure 4.31 DRAM Read Cycle (EDO page mode) The read timing in EDO page-mode lags 0.5 cycles behind that in fast page mode. EPSON B-II-4-28 S1C33L03 FUNCTION PART...
Page 205 Example: RAS: 1 cycle; CAS: 2 cycles; Precharge: 1 cycle; byte-write sample (little endian) Precharge RAS cycle CAS cycle #1 CAS cycle #2 cycle BCLK A[11:0] #RASx #HCAS #LCAS Undefined write data D[15:8] write data Undefined D[7:0] Figure 4.34 DRAM Byte-Write Cycle (fast page or EDO page mode) EPSON S1C33L03 FUNCTION PART B-II-4-29...
Page 206 • relinquishing of bus control is requested by an external bus master. Note: When using the successive RAS mode, always be sure to use #DRD for the read signal and #DWE for the low-byte write signal. EPSON B-II-4-30 S1C33L03 FUNCTION PART...
Page 207: Dram Refresh Cycles
The refresh RAS pulse width is determined by the timing at which the refresh is deactivated in software and is unaffected by settings of RRA. #RAS and #HCAS/#LCAS are booted up simultaneously upon completion of a self-refresh and the precharge duration that follows is fixed at 6 cycles. EPSON S1C33L03 FUNCTION PART B-II-4-31...
Page 208: Releasing External Bus
The DMA transfer that has been kept pending is restarted when the CPU gains control of the bus ownership. EPSON B-II-4-32 S1C33L03 FUNCTION PART...
Page 209: Power-Down Control By External Device
#BUSREQ pin is released back high. Unlike in the case of ordinary releasing of the bus by #BUSREQ, the address bus and bus control signals are not placed in high-impedance state. For a DRAM refresh request that may arise in this HALT state, take one of the corrective measures described above. EPSON S1C33L03 FUNCTION PART B-II-4-33...
Page 210: I/O Memory Of Bcu
1 8 bits 0 16 bits A14DF1 Areas 14–13 A14DF[1:0] Number of cycles A14DF0 output disable delay time – reserved – – – 0 when being read. A14WT2 Areas 14–13 wait control A14WT[2:0] Wait cycles A14WT1 A14WT0 EPSON B-II-4-34 S1C33L03 FUNCTION PART...
Page 211 1 8 bits 0 16 bits A8DF1 Areas 8–7 A8DF[1:0] Number of cycles A8DF0 output disable delay time – reserved – – – 0 when being read. A8WT2 Areas 8–7 wait control A8WT[2:0] Wait cycles A8WT1 A8WT0 EPSON S1C33L03 FUNCTION PART B-II-4-35...
Page 212 Writing 1 not allowed. SBUSST External interface method selection 1 #BSL 0 A0 SEMAS External bus master setup 1 Existing 0 Nonexistent SEPD External power-down control 1 Enabled 0 Disabled SWAITE #WAIT enable 1 Enabled 0 Disabled EPSON B-II-4-36 S1C33L03 FUNCTION PART...
Page 213 A1X1MD Area 1 access-speed 1 2 cycles 0 4 cycles x2 speed mode only – reserved – – 0 when being read. BCLKSEL1 BCLK output clock selection BCLKSEL[1:0] BCLK BCLKSEL0 PLL_CLK OSC3_CLK BCU_CLK CPU_CLK EPSON S1C33L03 FUNCTION PART B-II-4-37...
Page 214 AxxWT. Wait cycles derived from the #WAIT pin also can be inserted in the cycle for writing to the burst ROM area. At cold start, these bits are set to "111" (7 cycles). At hot start, the bits retain their status before being initialized. EPSON B-II-4-38 S1C33L03 FUNCTION PART...
Page 215 ROM write cycle. For the burst ROM write cycle, the wait cycles set via the #WAIT pin can also be used. At cold start, A10BW is set to "0" (no wait cycle). At hot start, A10BW retains its status before being initialized. EPSON S1C33L03 FUNCTION PART...
Page 216 The contents set here are applied to all of areas 14, 13, 8, and 7 that are set for DRAM. At cold start, REDO is set to "0" (fast-page mode). At hot start, REDO retains its status before being initialized. EPSON B-II-4-40...
Page 217 The contents set here are applied to all of areas 14, 13, 8, and 7 that are set for DRAM. At cold start, RPC0 is set to "0" (1 cycle). At hot start, RPC0 retains its status before being initialized. EPSON S1C33L03 FUNCTION PART...
Page 218 CPU is placed in a HALT state, allowing for reduction in power consumption. At cold start, SEPD is set to "0" (disabled). At hot start, SEPD retains its status before being initialized. EPSON B-II-4-42 S1C33L03 FUNCTION PART...
Page 219 Furthermore, when CEFUNC is set to "10" or "11", four chip enable signal is expanded into two area size. At cold start, CEFUNC is set to "00". At hot start, CEFUNC retains its status before being initialized. EPSON S1C33L03 FUNCTION PART...
Page 220 The contents set here are applied to all of areas 14, 13, 8, and 7 that are set for DRAM. At cold start, RASC is set to "0" (1 cycle). At hot start, RASC retains its status before being initialized. EPSON B-II-4-44...
Page 221 If AxxAS is set to "0", the signal output is disabled. At cold start, these bits are set to "0" (disabled). At hot start, these bits retain their status before being initialized. EPSON S1C33L03 FUNCTION PART...
Page 222 4. When the CPU stops by the HALT or SLP instruction, this clock is also stopped. This clock is almost in phase with the bus clock. At initial reset, BCLKSEL is set to "00" (CPU_CLK). EPSON B-II-4-46 S1C33L03 FUNCTION PART...
Page 223 When x1 speed mode is set (#X2SPD pin = "1"), area 1 is always accessed in 2 cycles regardless of the A1X1MD value. At cold start, A1X1MD is set to "0" (4 cycles). At hot start, A1X1MD retains its status before being initialized. EPSON S1C33L03 FUNCTION PART B-II-4-47...
Page 224 II CORE BLOCK: BCU (Bus Control Unit) THIS PAGE IS BLANK. EPSON B-II-4-48 S1C33L03 FUNCTION PART...
Page 225: Itc (Interrupt Controller)
Edge (rising or falling) or level (High or Low) 46 70(Base+118) Port input interrupt 6 Edge (rising or falling) or level (High or Low) 47 71(Base+11C) Port input interrupt 7 Edge (rising or falling) or level (High or Low) EPSON S1C33L03 FUNCTION PART B-II-5-1...
Page 226 The PSR and interrupt control register will be detailed later. For details about interrupt factor generating conditions, refer to the description of each peripheral circuit in this manual. EPSON B-II-5-2 S1C33L03 FUNCTION PART...
Page 227: Interrupt Factors And Intelligent Dma
If an interrupt to be generated upon completion of IDMA is disabled at the setting of the IDMA side, no interrupt request is signaled to the CPU. Therefore, the CPU remains idle until the next interrupt request is generated. EPSON S1C33L03 FUNCTION PART B-II-5-3...
Page 228: Trap Table
However, since an occurrence of NMI or the like between writes of the low-order and high-order half-words would cause a malfunction, it is recommended that the register be written in words. EPSON B-II-5-4 S1C33L03 FUNCTION PART...
Page 229: Control Of Maskable Interrupts
IL is rewritten. The IL is restored to its previous status when the interrupt processing routine is terminated by the reti instruction. EPSON S1C33L03 FUNCTION PART B-II-5-5...
Page 230: Interrupt Factor Flag And Interrupt Enable Register
For details about interrupt factor generating conditions, refer to the description of each peripheral circuit in this manual. EPSON B-II-5-6 S1C33L03 FUNCTION PART...
Page 231 These signals remain asserted until the interrupt factor flag is reset to "0" or the corresponding bit of the interrupt enable register is set to "0" (interrupts are disabled) or until some other interrupt factor of higher priority occurs. They are not cleared if the CPU simply accepts the interrupt request. EPSON S1C33L03 FUNCTION PART B-II-5-7...
Page 232: Interrupt Priority Register And Interrupt Levels
However, if the interrupt level of the IL is set below the current level and the IE is set to enable interrupts before resetting the interrupt factor flag after an interrupt has occurred, the same interrupt may occur again. EPSON B-II-5-8 S1C33L03 FUNCTION PART...
Page 233: Idma Invocation
An IDMA invocation request is accepted even when the interrupt enable register and PSR of the CPU is set to disable interrupts. It is also necessary that the control information for the IDMA channel has been set. EPSON S1C33L03 FUNCTION PART...
Page 234 Reset B signal (reset IDMA request bit) Reset C signal (reset IDMA enable bit) IDMA request bit "1" IDMA enable bit Figure 5.3 Sequence when DINTEN = "0" For details on IDMA, refer to "IDMA (Intelligent DMA)". EPSON B-II-5-10 S1C33L03 FUNCTION PART...
Page 235: Hsdma Invocation
Before HSDMA can be invoked by the occurrence of an interrupt factor, it is necessary that DMA be enabled on the HSDMA side by setting the control register for HSDMA transfer. For details about HSDMA, refer to "HSDMA (High-Speed DMA)". EPSON S1C33L03 FUNCTION PART B-II-5-11...
Page 236: I/O Memory Of Interrupt Controller
0 when being read. interrupt P16T32 16-bit timer 3 interrupt level 0 to 7 priority register P16T31 P16T30 – reserved – – – 0 when being read. P16T22 16-bit timer 2 interrupt level 0 to 7 P16T21 P16T20 EPSON B-II-5-12 S1C33L03 FUNCTION PART...
Page 237 – reserved – – – 0 when being read. E16TC2 16-bit timer 2 comparison A 1 Enabled 0 Disabled E16TU2 16-bit timer 2 comparison B D1–0 – reserved – – – 0 when being read. EPSON S1C33L03 FUNCTION PART B-II-5-13...
Page 238 0 No factor is flag register FSRX1 SIF Ch.1 receive buffer full generated generated FSERR1 SIF Ch.1 receive error FSTX0 SIF Ch.0 transmit buffer empty FSRX0 SIF Ch.0 receive buffer full FSERR0 SIF Ch.0 receive error EPSON B-II-5-14 S1C33L03 FUNCTION PART...
Page 239 DEP4 Port input 4 register – reserved – – – 0 when being read. DEADE A/D converter 1 IDMA 0 IDMA DESTX1 SIF Ch.1 transmit buffer empty enabled disabled DESRX1 SIF Ch.1 receive buffer full EPSON S1C33L03 FUNCTION PART B-II-5-15...
Page 240 IDMA enable register set method 1 Set only 0 RD/WR register selection IDMAONLY IDMA request register set method 1 Set only 0 RD/WR selection RSTONLY Interrupt factor flag reset method 1 Reset only 0 RD/WR selection EPSON B-II-5-16 S1C33L03 FUNCTION PART...
Page 241 Fixed at 0 0 when being read. order register (HW) TTBR32 Writing 1 not allowed. TTBR31 TTBR30 TTBR2B Trap table base address [27:16] 0x0C0 TTBR2A TTBR29 TTBR28 TTBR27 TTBR26 TTBR25 TTBR24 TTBR23 TTBR22 TTBR21 TTBR20 EPSON S1C33L03 FUNCTION PART B-II-5-17...
Page 242 For the interrupt factors used to request IDMA invocation or clear the standby mode, the corresponding interrupt enable register bit must be set for interrupt enable. When initially reset, this register is set to "0" (interrupt disabled). EPSON B-II-5-18 S1C33L03 FUNCTION PART...
Page 243 DMA transfer, the IDMA request register is reset to "0" and an interrupt request for the interrupt factor that enabled IDMA invoking is generated. After an initial reset, this register is set to "0" (Interrupt is requested). EPSON S1C33L03 FUNCTION PART B-II-5-19...
Page 244 IDMA request bit can be reset by the hardware between the read and the write, so be careful when using this method. After an initial reset, IDMAONLY is set to "1" (set-only method). EPSON B-II-5-20 S1C33L03 FUNCTION PART...
Page 245 Write "1": SIO Ch.3 receive error Write "0": FP2 input Read: Valid Set to "1" to use the SIO Ch.3 receive error interrupt. Set to "0" to use the FP2 input interrupt. At power-on, this bit is set to "0". EPSON S1C33L03 FUNCTION PART B-II-5-21...
Page 246 Write "1": 8-bit timer 5 underflow Write "0": FP7 input Read: Valid Set to "1" to use the 8-bit timer 5 underflow interrupt. Set to "0" to use the FP7 input interrupt. At power-on, this bit is set to "0". EPSON B-II-5-22 S1C33L03 FUNCTION PART...
Page 247 Write "0": TM16 Ch.3 compare B Read: Valid Set to "1" to use the SIO Ch.2 receive error interrupt. Set to "0" to use the TM16 Ch.3 compare B interrupt. At power-on, this bit is set to "0". EPSON S1C33L03 FUNCTION PART B-II-5-23...
Page 248 Before writing to the TTBR register, set TBRP to "0x59" to remove the write protection. Then when data is written to the most significant byte (0x48137) of the TTBR, the register once again becomes write-protected. After an initial reset, TBRP is set to "0x0" (write protected). EPSON B-II-5-24 S1C33L03 FUNCTION PART...
Page 249: Programming Notes
(5) To prevent another interrupt from being generated for the same factor again after generation of an interrupt, be sure to reset the interrupt factor flag before enabling interrupts and setting the PSR again or executing the reti instruction. EPSON S1C33L03 FUNCTION PART B-II-5-25...
Page 250 II CORE BLOCK: ITC (Interrupt Controller) THIS PAGE IS BLANK. EPSON B-II-5-26 S1C33L03 FUNCTION PART...
Page 251: Clg (Clock Generator)
CPU and turn off the high-speed (OSC3) oscillation circuit in order to reduce current consumption. In addition, when SLEEP mode is set, the high-speed (OSC3) oscillation circuit is turned off, greatly reducing current consumption (no internal units except for the clock timer need to be operated). EPSON S1C33L03 FUNCTION PART B-II-6-1...
Page 252: I/O Pins Of Clock Generator
Note: When using the PLL, the oscillation frequency range changes according to the PLL setting. See Table 6.2. For details on oscillation characteristics and the external clock input characteristics, refer to "Electrical Characteristics". EPSON B-II-6-2 S1C33L03 FUNCTION PART...
Page 253: Pll
(for 3.3-V crystal resonator, this time is 10 ms max.). To prevent the device from operating erratically, do not use the clock until its oscillation has stabilized. The high-speed (OSC3) oscillation circuit turns off when the CPU is set in SLEEP mode. EPSON S1C33L03 FUNCTION PART B-II-6-3...
Page 254: Setting And Switching Over The Cpu Operating Clock
3. Switch over the CPU operating clock (by writing "1" to CLKCHG). Note: The operating clock switchover by CLKCHG is effective only when both oscillation circuits are on and the power-control register protection flag is set to "0b10010110". EPSON B-II-6-4 S1C33L03 FUNCTION PART...
Page 255: Power-Control Register Protection Flag
Note: The function for waiting until the high-speed (OSC3) oscillation is stabilized by 8T1ON is effective only when SLEEP mode is exited. Writing to 8T1ON is effective only when the power-control register protection flag is set to "0b10010110". EPSON S1C33L03 FUNCTION PART B-II-6-5...
Page 256: I/O Memory Of Clock Generator
Writing to SOSC3 is allowed only when CLGP[7:0] is set to "0b10010110". Note also that if the CPU is operating using the OSC3 clock, writing "0" to SOSC3 is ignored and the oscillation is not turned off. At initial reset, SOSC3 is set to "1" (OSC3 oscillation turned on). EPSON B-II-6-6 S1C33L03 FUNCTION PART...
Page 257 Writing to HLT2OP is allowed only when CLGP[7:0] is set to "0b10010110". At initial reset, HLT2OP is set to "0" (basic mode). The following shows the operating status in HALT mode (basic mode and HALT2 mode) and SLEEP mode. EPSON S1C33L03 FUNCTION PART B-II-6-7...
Page 258 This clearing of write protection is effective for only one writing, so the bits are cleared to "0b00000000" by one writing. Therefore, CLGP[7:0] must be set each time the protected address is written to. At initial reset, CLGP is set to "0b00000000" (write-protected). EPSON B-II-6-8 S1C33L03 FUNCTION PART...
Page 259: Programming Notes
Therefore, a restart is effected when the input level from a port is active by level. Consequently, the system design should assume that a restart by means of port input from the SLEEP state or HALT2 state is performed by level. EPSON S1C33L03 FUNCTION PART B-II-6-9...
Page 260 If the peripheral circuit clock frequency is equal to or higher than the base clock frequency, the peripheral circuit does not operate normally. EPSON B-II-6-10 S1C33L03 FUNCTION PART...
Page 261: Dbg (Debug Unit)
S1C33 Family) can be connected to these pins. Leave these pins open if the S5U1C33000H is not connected. For connecting the S5U1C33000H, refer to the "S5U1C33000H Manual (S1C33 Family In-Circuit Debugger)". Furthermore, the pin status is fixed as shown in the above table after a user reset. EPSON S1C33L03 FUNCTION PART B-II-7-1...
Page 262 II CORE BLOCK: DBG (Debug Unit) THIS PAGE IS BLANK. EPSON B-II-7-2 S1C33L03 FUNCTION PART...
Page 263: Peripheral Block
S1C33L03 FUNCTION PART III PERIPHERAL BLOCK...
Page 265: Introduction
C33_ADC C33_PERI Pads Intro (A/D converter) (Prescaler, 8-bit timer, 16-bit timer, Clock timer, Serial interface, Ports) C33 Analog Block C33 Peripheral Block Figure 1.1 Peripheral Block Note: Internal ROM is not provided in the S1C33L03. EPSON S1C33L03 FUNCTION PART B-III-1-1...
Page 266 III PERIPHERAL BLOCK: INTRODUCTION THIS PAGE IS BLANK. EPSON B-III-1-2 S1C33L03 FUNCTION PART...
Page 267: Prescaler
(DRAM refresh), A/D converter, serial interface, and ports) that use the prescaler input clock (the source clock for prescaler) can be turned off, stop the prescaler by writing "0" to PSCON. This helps to reduce current consumption. EPSON S1C33L03 FUNCTION PART B-III-2-1...
Page 268: Selecting Division Ratio And Output Control For Prescaler
The clock output is controlled by the P8TONx bit even if P8TPCKx is set to "1". When P8TPCKx is "0", the divided clock that is selected by P8TSx[2:0] will be output to the 8-bit timer x. At initial reset, P8TPCKx is set to "0" and P8TSx[2:0] becomes effective. EPSON B-III-2-2 S1C33L03 FUNCTION PART...
Page 269: I/O Memory Of Prescaler
P16TON2 16-bit timer 2 clock control 1 On 0 Off register P16TS22 16-bit timer 2 P16TS2[2:0] Division ratio : selected by P16TS21 clock division ratio selection /4096 Prescaler clock select P16TS20 /1024 register (0x40181) /256 EPSON S1C33L03 FUNCTION PART B-III-2-3...
Page 270 1 On 0 Off P8TS02 8-bit timer 0 P8TS0[2:0] Division ratio : selected by P8TS01 clock division ratio selection /256 Prescaler clock select P8TS00 /128 register (0x40181) 8-bit timer 0 can generate the DRAM refresh clock. EPSON B-III-2-4 S1C33L03 FUNCTION PART...
Page 271 (e.g., 16-bit programmable timers, 8-bit programmable timers, A/D converter, serial interface, and ports). Therefore, do not turn off the prescaler when these peripheral circuits are used. At initial reset, PSCON is set to "1" (On). EPSON S1C33L03 FUNCTION PART B-III-2-5...
Page 272 The desired division ratio can be selected from among the eight ratios shown on the I/O map. Note that the division ratio differs for each peripheral circuit. These bits can also be read out. At initial reset, all of these bits are set to "0b000" (highest frequency available). EPSON B-III-2-6 S1C33L03 FUNCTION PART...
Page 273 The clock output is controlled by the P8TONx bit even if P8TPCKx is set to "1". When "0" is written, the divided clock that is selected by P8TSx[2:0] will be output to the 8-bit timer x. At initial reset, P8TPCKx is set to "0" (divided clock). EPSON S1C33L03 FUNCTION PART B-III-2-7...
Page 274: Programming Notes
(B) stops. When some these circuits of the above (A) need to be used, turn off all other unnecessary circuits and stop the clock supply from the prescaler to those circuits. EPSON B-III-2-8...
Page 275: 8-Bit Programmable Timers
8-bit programmable timer. At cold start, the register is set to input mode. At hot start, the register retains its status from prior to the reset. EPSON S1C33L03 FUNCTION PART...
Page 276: Uses Of 8-Bit Programmable Timers
CPU can be started up by that underflow signal. To use this function, write "0" to the oscillation circuit control bit 8T1ON (D2) / Clock option register (0x40190) to enable the oscillation stabilization waiting function. EPSON B-III-3-2 S1C33L03 FUNCTION PART...
Page 277 5 by dividing it by 2 is supplied to the serial interface as its operating clock. This enables the transfer rate of the serial interface to be programmed. To use this function, write "0" to the serial interface control bit SSCK3 (D2) / Serial I/F Ch.3 control register (0x401F8) to select the internal clock. EPSON S1C33L03 FUNCTION PART B-III-3-3...
Page 278: Control And Operation Of 8-Bit Programmable Timer
"Prescaler".) • Do not use a clock that is faster than the CPU operating clock as the 8-bit programmable timer. • When setting an input clock, make sure the 8-bit programmable timer is turned off. EPSON B-III-3-4 S1C33L03 FUNCTION PART...
Page 279 When the terminal count is reached and the counter underflows, the initial value is reloaded from the reload data register into the counter. EPSON S1C33L03 FUNCTION PART B-III-3-5...
Page 280 Timer 3 data: PTD3[7:0] (D[7:0]) / 8-bit timer 3 counter data register (0x4016E) Timer 4 data: PTD4[7:0] (D[7:0]) / 8-bit timer 4 counter data register (0x40176) Timer 5 data: PTD5[7:0] (D[7:0]) / 8-bit timer 5 counter data register (0x4017A) EPSON B-III-3-6 S1C33L03 FUNCTION PART...
Page 281: Control Of Clock Output
3) The timer output is left as "0" when the timer output is turned on after setting the input clock and timer initial value. 4) When an underflow occurs after starting the timer, the port outputs a pulse with the same width as the 8-bit timer input clock pulse (prescaler's output). EPSON S1C33L03 FUNCTION PART B-III-3-7...
Page 282: 8-Bit Programmable Timer Interrupts And Dma
The registers can also be set so as not to generate an interrupt, with only a DMA transfer performed. For details on IDMA transfers and interrupt control upon completion of IDMA transfer, refer to "IDMA (Intelligent DMA)". EPSON B-III-3-8 S1C33L03 FUNCTION PART...
Page 283 Timer 0 underflow interrupt: 0x0C000D0 Timer 1 underflow interrupt: 0x0C000D4 Timer 2 underflow interrupt: 0x0C000D8 Timer 3 underflow interrupt: 0x0C000DC The base address of the trap table can be changed using the TTBR register (0x48134 to 0x48137). B-III EPSON S1C33L03 FUNCTION PART B-III-3-9...
Page 284: I/O Memory Of 8-Bit Programmable Timers
RLD20 = LSB RLD24 RLD23 RLD22 RLD21 RLD20 8-bit timer 2 004016A PTD27 8-bit timer 2 counter data 0 to 255 counter data PTD26 PTD27 = MSB register PTD25 PTD20 = LSB PTD24 PTD23 PTD22 PTD21 PTD20 EPSON B-III-3-10 S1C33L03 FUNCTION PART...
Page 285 I/F Ch.0 PSIO02 Serial interface Ch.0 0 to 7 interrupt PSIO01 interrupt level priority register PSIO00 – reserved – – – 0 when being read. P8TM2 8-bit timer 0–3 interrupt level 0 to 7 P8TM1 P8TM0 EPSON S1C33L03 FUNCTION PART B-III-3-11...
Page 286 0 P21, etc. CFEX1 P10, P11, P13 port extended 1 DST0 0 P10, etc. function DST1 P11, etc. DPC0 P13, etc. CFEX0 P12, P14 port extended function 1 DST2 0 P12, etc. DCLK P14, etc. EPSON B-III-3-12 S1C33L03 FUNCTION PART...
Page 287 There are two cases in which the reload data is loaded into the counter: when data is preset after "1" is written to PSETx, or when data is automatically reloaded upon counter underflow. At initial reset, RLD is not initialized. EPSON S1C33L03 FUNCTION PART B-III-3-13...
Page 288 While in a STOP state, the counter retains its count until it is preset with reload data or placed in a RUN state. When the state is changed from STOP to RUN, the counter can restart counting beginning with the retained count. At initial reset, PTRUNx is set to "0" (STOP). EPSON B-III-3-14 S1C33L03 FUNCTION PART...
Page 289 When written using the reset-only method (default) Write "1": Interrupt factor flag is reset Write "0": Invalid When written using the read/write method Write "1": Interrupt flag is set Write "0": Interrupt flag is reset EPSON S1C33L03 FUNCTION PART B-III-3-15...
Page 290 If the bit is set to "0", normal interrupt processing is performed and IDMA is not invoked. For details on IDMA, refer to "IDMA (Intelligent DMA)". At initial reset, R8TUx is set to "0" (interrupt request). EPSON B-III-3-16 S1C33L03 FUNCTION PART...
Page 291: Programming Notes
(6) To prevent another interrupt from being generated again by the same factor after an interrupt has occurred, be sure to reset the interrupt factor flag (F8TUx) before setting the PSR again or executing the reti instruction. EPSON S1C33L03 FUNCTION PART...
Page 292 III PERIPHERAL BLOCK: 8-BIT PROGRAMMABLE TIMERS THIS PAGE IS BLANK. EPSON B-III-3-18 S1C33L03 FUNCTION PART...
Page 293: 16-Bit Programmable Timers
When the counter value matches to the content of each comparison data register, the comparator outputs a signal that controls the interrupt and the output signal. Thus the registers allow interrupt generating intervals and the timer's output clock frequency and duty ratio to be programmed. EPSON S1C33L03 FUNCTION PART B-III-4-1...
Page 294: I/O Pins Of 16-Bit Programmable Timers
Therefore, it is necessary to set the I/O port's I/O control bit IOC1x to "0" in advance. At cold start, these pins are set in input mode. At hot start, they retain their status from prior to the reset. EPSON B-III-4-2 S1C33L03 FUNCTION PART...
Page 295: Uses Of 16-Bit Programmable Timers
To use this function, write "1" to the watchdog timer control bit EWD (D1) / Watchdog timer enable register (0x40171) to enable the NMI. For details on how to control the watchdog timer, refer to "Watchdog Timer". 16TM EPSON S1C33L03 FUNCTION PART B-III-4-3...
Page 296: Control And Operation Of 16-Bit Programmable Timer
Notes: • When the internal clock is used, the 16-bit programmable timer operates only when the prescaler is operating (refer to "Prescaler"). • When setting an input clock, make sure the 16-bit programmable timer is turned off. EPSON B-III-4-4 S1C33L03 FUNCTION PART...
Page 297 This comparison match signal controls the clock output (TMx signal) to external devices, in addition to generating an interrupt. The comparison data B is also used to reset the counter. EPSON S1C33L03 FUNCTION PART B-III-4-5...
Page 298 Timer 3 counter data: TC3[15:0] (D[F:0]) / 16-bit timer 3 counter data register (0x4819C) Timer 4 counter data: TC4[15:0] (D[F:0]) / 16-bit timer 4 counter data register (0x481A4) Timer 5 counter data: TC5[15:0] (D[F:0]) / 16-bit timer 5 counter data register (0x481AC) EPSON B-III-4-6 S1C33L03 FUNCTION PART...
Page 299: Controlling Clock Output
1 2 3 4 5 0 1 2 3 4 5 0 1 2 3 4 5 0 1 Comparison match A signal Comparison match B signal PTMx TMx output (when OUTINVx = "0") TMx output (when OUTINVx = "1") Figure 4.3 Waveform of 16-Bit Programmable Timer Output EPSON S1C33L03 FUNCTION PART B-III-4-7...
Page 300 A = 0 and B = 1. In this case, the timer output clock cycle is the input clock 1/2. 3) When the comparison data registers are set as A > B, no comparison A signal is generated. In this case, the output signal is fixed at the off level. EPSON B-III-4-8 S1C33L03 FUNCTION PART...
Page 301: 16-Bit Programmable Timer Interrupts And Dma
Timer 2 comparison A: 0x0C Timer 3 comparison B: 0x0D Timer 3 comparison A: 0x0E Timer 4 comparison B: 0x0F Timer 4 comparison A: 0x10 Timer 5 comparison B: 0x11 Timer 5 comparison A: 0x12 EPSON S1C33L03 FUNCTION PART B-III-4-9...
Page 302 Transfer conditions, etc. must also be set on the HSDMA side. If a 16-bit timer is selected as the HSDMA trigger, the HSDMA channel is invoked through generation of the interrupt factor. For details on HSDMA transfer, refer to "HSDMA (High-Speed DMA)". EPSON B-III-4-10 S1C33L03 FUNCTION PART...
Page 303 Serial interface Ch.2 and Ch.3 share interrupt signals with the 16-bit timers. A register setting determined which is used. The initial setting is for use of the 16-bit timers. Refer to Section III-8, "Serial Interface", for details of the settings. B-III 16TM EPSON S1C33L03 FUNCTION PART B-III-4-11...
Page 304: I/O Memory Of 16-Bit Programmable Timers
0 when being read. F16TC4 16-bit timer 4 comparison A 1 Factor is 0 No factor is F16TU4 16-bit timer 4 comparison B generated generated D1–0 – reserved – – – 0 when being read. EPSON B-III-4-12 S1C33L03 FUNCTION PART...
Page 305 IOC14 P14 I/O control of the I/O control IOC13 P13 I/O control signals of the ports IOC12 P12 I/O control when it is read. (See IOC11 P11 I/O control detailed explanation.) IOC10 P10 I/O control EPSON S1C33L03 FUNCTION PART B-III-4-13...
Page 306 1 External clock 0 Internal clock PTM0 16-bit timer 0 clock output control 1 On 0 Off PRESET0 16-bit timer 0 reset 1 Reset 0 Invalid 0 when being read. PRUN0 16-bit timer 0 Run/Stop control 1 Run 0 Stop EPSON B-III-4-14 S1C33L03 FUNCTION PART...
Page 307 16-bit timer 2 comparison data A 0 to 65535 comparison (HW) CR2A14 CR2A15 = MSB data A set-up CR2A13 CR2A0 = LSB register CR2A12 CR2A11 CR2A10 CR2A9 CR2A8 CR2A7 CR2A6 CR2A5 CR2A4 CR2A3 CR2A2 CR2A1 CR2A0 EPSON S1C33L03 FUNCTION PART B-III-4-15...
Page 308 16-bit timer 3 comparison data B 0 to 65535 comparison (HW) CR3B14 CR3B15 = MSB data B set-up CR3B13 CR3B0 = LSB register CR3B12 CR3B11 CR3B10 CR3B9 CR3B8 CR3B7 CR3B6 CR3B5 CR3B4 CR3B3 CR3B2 CR3B1 CR3B0 EPSON B-III-4-16 S1C33L03 FUNCTION PART...
Page 309 00481A4 TC415 16-bit timer 4 counter data 0 to 65535 counter data (HW) TC414 TC415 = MSB register TC413 TC40 = LSB TC412 TC411 TC410 TC49 TC48 TC47 TC46 TC45 TC44 TC43 TC42 TC41 TC40 EPSON S1C33L03 FUNCTION PART B-III-4-17...
Page 310 1 External clock 0 Internal clock PTM5 16-bit timer 5 clock output control 1 On 0 Off PRESET5 16-bit timer 5 reset 1 Reset 0 Invalid 0 when being read. PRUN5 16-bit timer 5 Run/Stop control 1 Run 0 Stop EPSON B-III-4-18 S1C33L03 FUNCTION PART...
Page 311 IOC register. At cold start, IOC1x is set to "0" (input mode). At hot start, the bit retains its state from prior to the initial reset. EPSON S1C33L03 FUNCTION PART B-III-4-19...
Page 312 By writing "1" to OUTINVx, an active-low signal (off level = high) is generated for the TMx output. When OUTINVx is set to "0", an active-high signal (off level = low) is generated. At initial reset, OUTINVx is set to "0" (active high). EPSON B-III-4-20 S1C33L03 FUNCTION PART...
Page 313 Write "0": Invalid Read: Always "0" The counter of timer x is reset by writing "1" to PRESETx. Writing "0" results in No Operation. Since PRESETx is a write-only bit, its content when read is always "0". EPSON S1C33L03 FUNCTION PART B-III-4-21...
Page 314 The data set in this register is compared with each corresponding counter data. When the contents match, a comparison B interrupt is generated and the output signal falls (OUTINVx = "0") or rises (OUTINVx = "1"). Furthermore, the counter is reset to "0". At initial reset, CRxB is not initialized. EPSON B-III-4-22 S1C33L03 FUNCTION PART...
Page 315 When written using the reset-only method (default) Write "1": Interrupt factor flag is reset Write "0": Invalid When written using the read/write method Write "1": Interrupt flag is set Write "0": Interrupt flag is reset EPSON S1C33L03 FUNCTION PART B-III-4-23...
Page 316 When the register is set to "0", normal interrupt processing is performed and IDMA is not invoked. For details on IDMA, refer to "IDMA (Intelligent DMA)". At initial reset, these bits are set to "0" (interrupt request). EPSON B-III-4-24 S1C33L03 FUNCTION PART...
Page 317: Programming Notes
TMx signal falls with the comparison A signal, a high level pulse will be generated if "0" is written to PTMx before setting the port to low. It can be prevented by writing "0" to PTMx after setting the port to low. EPSON S1C33L03 FUNCTION PART B-III-4-25...
Page 318 III PERIPHERAL BLOCK: 16-BIT PROGRAMMABLE TIMERS THIS PAGE IS BLANK. EPSON B-III-4-26 S1C33L03 FUNCTION PART...
Page 319: Watchdog Timer
For the 16-bit programmable timer 0, set an appropriate comparison B value to make it start operating. If the watchdog timer function is not to be used, set EWD to "0" and do not change it. EPSON S1C33L03 FUNCTION PART...
Page 320: Operation In Standby Modes
In SLEEP mode, the prescaler is turned off. Therefore, the watchdog timer also stops operating. To prevent generation of an unwanted NMI after clearing SLEEP mode, reset the 16-bit programmable timer 0 before executing the slp instruction. In addition, disable generation of the NMI by EWD as necessary. EPSON B-III-5-2 S1C33L03 FUNCTION PART...
Page 321: I/O Memory Of Watchdog Timer
(2) Even when EWD is set to "0", the 16-bit programmable timer 0 does not stop counting. Therefore, if the NMI has been temporarily disabled, be sure to reset the 16-bit programmable timer 0 before setting EWD back to "1". EPSON S1C33L03 FUNCTION PART B-III-5-3...
Page 322 III PERIPHERAL BLOCK: WATCHDOG TIMER THIS PAGE IS BLANK. EPSON B-III-5-4 S1C33L03 FUNCTION PART...
Page 323: Low-Speed (Osc1) Oscillation Circuit
Low-speed (OSC1) oscillation input pin Crystal oscillation or external clock input OSC2 Low-speed (OSC1) oscillation output pin Crystal oscillation (open when external clock is used) P14/FOSC1/DCLK I/O I/O port / Low-speed (OSC1) oscillation clock output / DCLK signal output EPSON S1C33L03 FUNCTION PART B-III-6-1...
Page 324: Oscillator Types
The oscillation frequency is 32.768 kHz (Typ.). Use a crystal resonator or external clock that oscillates at this frequency. No other frequency can be used for clock applications. For details on oscillation characteristics and the external clock input characteristics, refer to "Electrical Characteristics". EPSON B-III-6-2 S1C33L03 FUNCTION PART...
Page 325: Controlling Oscillation
3. Switch over the CPU operating clock (by writing "1" to CLKCHG). Note: The operating clock switchover by CLKCHG is effective only when both oscillation circuits are on and the power-control register protection flag is set to "0b10010110". EPSON S1C33L03 FUNCTION PART B-III-6-3...
Page 326: Power-Control Register Protection Flag
To start clock output, write "1" to PF1ON (D0) / Clock option register (0x40190). The clock output is stopped by writing "0". At initial reset, PF1ON is set to "0" (output disabled). PF1ON register FOSC1(P14) pin output Figure 6.3 OSC1 Clock Output EPSON B-III-6-4 S1C33L03 FUNCTION PART...
Page 327: I/O Memory Of Low-Speed (Osc1) Oscillation Circuit
0 P21, etc. CFEX1 P10, P11, P13 port extended 1 DST0 0 P10, etc. function DST1 P11, etc. DPC0 P13, etc. CFEX0 P12, P14 port extended function 1 DST2 0 P12, etc. DCLK P14, etc. EPSON S1C33L03 FUNCTION PART B-III-6-5...
Page 328 When "1" is written to HLT2OP, the CPU will enter HALT2 mode when the HALT instruction is executed. When "0" is written, the CPU will enter basic mode. Writing to HLT2OP is allowed only when CLGP[7:0] is set to "0b10010110". At initial reset, HLT2OP is set to "0" (basic mode). EPSON B-III-6-6 S1C33L03 FUNCTION PART...
Page 329 This clearing of write protection is effective for only one writing, so the bits are cleared to "0b00000000" by one writing. Therefore, CLGP[7:0] must be set each time the protected address is written to. At initial reset, CLGP is set to "0b00000000" (write-protected). EPSON S1C33L03 FUNCTION PART B-III-6-7...
Page 330: Programming Notes
This helps reduce current consumption. (6) When the P14/FOSC1/DCLK pin is used as the FOSC1 output pin, set IOC14 (D4/0x402D6) to "1" (output) in addition to the CFP14 (D4/0x402D4) and CFEX0 (D0/0x402DF) settings. EPSON B-III-6-8 S1C33L03 FUNCTION PART...
Page 331: Clock Timer
B-III Interrupt/alarm Interrupt request Comparator Comparator Comparator select circuit (to interrupt controller) Alarm generation control circuit 6-bit minute 5-bit hour 5-bit day comparison comparison comparison data data data Figure 7.1 Structure of Clock Timer EPSON S1C33L03 FUNCTION PART B-III-7-1...
Page 332: Control And Operation Of The Clock Timer
When using the clock timer as an RTC, be sure to set these counter values before starting operating of the clock timer. For the day counter, set a number of days starting from the reference day (e.g., January 1, 1990). EPSON B-III-7-2...
Page 333 0xFF and then overflows before reading the next seconds counter, the value of the seconds counter is its count plus the one second that has elapsed since the 8-bit binary counter was read. To prevent this problem, try reading out each counter several times and make sure data has not been modified. EPSON S1C33L03 FUNCTION PART B-III-7-3...
Page 334: Interrupt Function
(D1) / Port input 4–7, clock timer, A/D interrupt factor flag register (0x40287) also is set to "1". At this time, if the interrupt conditions set by the interrupt control registers are met, an interrupt to the CPU is generated. EPSON B-III-7-4...
Page 335 Note that the clock timer interrupt factor does not have a function to invoke an intelligent DMA. Trap vectors The trap vector addresses for the clock-timer interrupt by default are set to 0x0C00104. The trap table base address can be changed using the TTBR registers (0x48134 to 0x48137). EPSON S1C33L03 FUNCTION PART B-III-7-5...
Page 336: Examples Of Use Of Clock Timer
TCIF and alarm factor generation flag TCAF. If TCAF is set to 1, the interrupt has been caused by an alarm. If you select an interrupt factor (other than a 1-day factor) along with the hour-specified alarm, the selected interrupt factor occurs at the same time as the alarm factor. EPSON B-III-7-6 S1C33L03 FUNCTION PART...
Page 337: I/O Memory Of Clock Timer
TCND1 TCND0 Clock timer 0040158 TCND15 Clock timer day counter data 0 to 65535 days day (high- TCND14 (high-order 8 bits) (high-order 8 bits) order) register TCND13 TCND15 = MSB TCND12 TCND11 TCND10 TCND9 TCND8 EPSON S1C33L03 FUNCTION PART B-III-7-7...
Page 338 Writing "0" to TCRST results in No Operation. Since this TCRST is a write-only bit, its value when read is always "0". The clock timer is not reset by an initial reset. EPSON B-III-7-8 S1C33L03 FUNCTION PART...
Page 339 When the clock timer interrupt is enabled, an interrupt is generated cyclically at each falling edge of the selected signal. If you the interrupt caused by these factors is not be used set TCISE to "111". TCISE is not initialized at initial reset. EPSON S1C33L03 FUNCTION PART B-III-7-9...
Page 340 This bit does not affect generation of an alarm even if it is set to "1" or "0". PCTM2–PCTM0: Clock timer interrupt level (D[2:0]) / Clock timer interrupt priority register (0x4026B) Sets the priority level of the clock timer interrupt between 0 and 7. At initial reset, PCTM becomes indeterminate. EPSON B-III-7-10 S1C33L03 FUNCTION PART...
Page 341 Note also that the value to be written to reset the flag is "1" when the reset-only method (RSTONLY = "1") is used, and "0" when the read/write method (RSTONLY = "0") is used. The FCTM flag becomes indeterminate at initial reset, so be sure to reset it in the software. EPSON S1C33L03 FUNCTION PART B-III-7-11...
Page 342: Programming Notes
(7) To prevent regeneration of interrupts with the same factor after an interrupt has occurred, be sure to reset the interrupt factor flag (FCTM) before setting the PSR again or executing the reti instruction. EPSON B-III-7-12 S1C33L03 FUNCTION PART...
Page 343: Serial Interface
0, 1, 2, or 3 to indicate the channel number, enabling discrimination between channels 0 to 3. In this manual, however, channel numbers 0 to 3 are replaced with "x" unless discrimination is necessary, because explanations are common to all four channels. EPSON S1C33L03 FUNCTION PART B-III-8-1...
Page 344: I/O Pins Of Serial Interface
P0x (function select bit Pxx, CFPxx = "0"). When using the serial interface, make function select bit settings for the pins used, according to the channel and transfer mode to be used. At hot start, the pins retain their status from prior to the reset. EPSON B-III-8-2 S1C33L03 FUNCTION PART...
Page 345: Setting Transfer Mode
0x401E4, Ch.1: 0x401E9, Ch.2: 0x401F4, Ch.3: 0x401F9) is provided. Since these bits become indeterminate at initial reset, be sure to initialize them by writing "00" when using as the normal interface or "10" when using as the IrDA interface. EPSON S1C33L03 FUNCTION PART B-III-8-3...
Page 346: Clock-Synchronized Interface
Start bit: None Stop bit: None Parity bit: None #SCLKx Data D0 D1 D2 D3 D4 D5 D6 D7 Figure 8.3 Clock-Synchronized Transfer Data Format Serial data is transmitted and received starting with the LSB. EPSON B-III-8-4 S1C33L03 FUNCTION PART...
Page 347: Setting Clock-Synchronized Interface
To ensure that the duty ratio of the clock to be fed to the serial interface is 50%, the 8-bit programmable timer further divides the underflow signal frequency by 2 internally. This 1/2 frequency division is factored into Eq. EPSON S1C33L03 FUNCTION PART...
Page 348 This mode operates using the clock that is output by the external master. This clock is input from the #SCLK pin. Therefore, there is no need to control the prescaler or 8-bit programmable timer. Initialize SSCKx by writing "1" (#SCLKx). EPSON B-III-8-6 S1C33L03 FUNCTION PART...
Page 349: Control And Operation Of Clock-Synchronized Transfer
When data is transmitted successively in clock-synchronized master mode, TENDx maintains "1" until all data is transmitted (Figure 8.4). In slave mode, TENDx goes "0" every time 1-byte data is transmitted (Figure 8.5). Following explains transmit operation in both the master and slave modes. EPSON S1C33L03 FUNCTION PART B-III-8-7...
Page 350 At the same time, the LSB of the data transferred to the shift register is output from the SOUTx pin. The #SRDYx signal is returned to a high level at this point. EPSON B-III-8-8 S1C33L03 FUNCTION PART...
Page 351 Ch.2 receive data: RXD2[7:0] (D[7:0]) / Serial I/F Ch.2 receive data register (0x401F1) Ch.3 receive data: RXD3[7:0] (D[7:0]) / Serial I/F Ch.3 receive data register (0x401F6) The receive data can be read out from this register. EPSON S1C33L03 FUNCTION PART B-III-8-9...
Page 352 An overrun error occurs because the receive operation has completed when RDBFx = "1". 3rd data is read. Send the busy signal to the master device to stop the clock. Figure 8.7 Receive Timing Chart in Clock-Synchronized Slave Mode EPSON B-III-8-10 S1C33L03 FUNCTION PART...
Page 353 (5) Terminating receive operation Upon completion of a data receive operation, write "0" to the receive-enable bit RXENx to disable receive operations. EPSON S1C33L03 FUNCTION PART B-III-8-11...
Page 354: Asynchronous Interface
(Stop bit: 2 bits, parity: non) (Stop bit: 2 bits, parity: used) s1: start bit, s2 & s3: stop bit, p: parity bit Figure 8.9 Data Format for Asynchronous Transfer Serial data is transmitted and received, starting with the LSB. EPSON B-III-8-12 S1C33L03 FUNCTION PART...
Page 355: Setting Asynchronous Interface
Therefore, before the internal clock can be used, the following conditions must be met: 1. The prescaler is outputting a clock to the 8-bit programmable timer 2 (or 3). 2. The 8-bit programmable timer 2 (or 3) is outputting a clock. EPSON S1C33L03 FUNCTION PART B-III-8-13...
Page 356 Any desired clock frequency can be set. The clock input from the #SCLKx pin is internally divided by 16 or 8 in the serial interface, in order to create a sampling clock (refer to "Sampling clock"). This division ratio must also be considered when setting the transfer rate. EPSON B-III-8-14 S1C33L03 FUNCTION PART...
Page 357 Figure 8.11 Sampling Clock for Asynchronous Transmit Operation (when 1/16 division is selected) When transmitting data, a sampling clock of a 50% duty cycle is generated from TCLK by dividing it by 16 (or 8), and each bit of data is output synchronously with this clock. EPSON S1C33L03 FUNCTION PART B-III-8-15...
Page 358: Control And Operation Of Asynchronous Transfer
This bit is reset to "0" by writing data to the transmit data register, and set back to "1" (buffer empty) when the data is transferred to the shift register. The transfer begins when the serial interface starts sending the start bit. EPSON B-III-8-16 S1C33L03 FUNCTION PART...
Page 359 For details on how to control interrupts and IDMA requests, refer to "Serial Interface Interrupts and DMA". (3) Terminating transmit operations When data transmission is completed, write "0" to the transmit-enable bit TXENx to disable transmit operations. EPSON S1C33L03 FUNCTION PART B-III-8-17...
Page 360 4. When the stop bit is sampled, the data in the shift register is transferred to the receive data register, enabling the data to be read out. The parity is checked when data is transferred to the receive data register (if EPRx = "1"). EPSON B-III-8-18 S1C33L03 FUNCTION PART...
Page 361 However, the content of the received data for which a framing error is flagged cannot be guaranteed, even if no framing error is found in the following data received. The FERx flag is reset to "0" by writing "0". EPSON S1C33L03 FUNCTION PART B-III-8-19...
Page 362 The OERx flag is reset to "0" by writing "0". (4) Terminating receive operation When a data receive operation is completed, write "0" to the receive-enable bit RXENx to disable receive operations. EPSON B-III-8-20 S1C33L03 FUNCTION PART...
Page 363: Irda Interface
RXENx are both set to "0"), as a change in settings during operation could cause a malfunction. In addition, be sure to set the transfer mode in (3) and the following items before selecting the IrDA interface function in (2). EPSON S1C33L03 FUNCTION PART B-III-8-21...
Page 364 PPM modulator input (SINx) PPM modulator output (I/F input) Figure 8.15 IRRLx and IRTLx Settings Note: The IRRLx and IRTLx bits become indeterminate at initial reset, so be sure to initialize them in the software. EPSON B-III-8-22 S1C33L03 FUNCTION PART...
Page 365: Control And Operation Of Irda Interface
PPM modulator output (I/F input) B-III 16 TCLK Figure 8.17 Demodulation by PPM Circuit Note: When using the IrDA interface, set the internal division ratio of the serial interface 1/16 (DIVMDx = "1"), rather than 1/8 (DIVMDx = "0"). EPSON S1C33L03 FUNCTION PART B-III-8-23...
Page 366: Serial Interface Interrupts And Dma
Interrupts caused by an interrupt factor can be disabled by leaving the interrupt enable register bit for that factor set to "0". The interrupt factor flag is set to "1" whenever interrupt conditions are met, regardless of the setting of the interrupt enable register (even if it is set to "0"). EPSON B-III-8-24 S1C33L03 FUNCTION PART...
Page 367 IDMA side must also be set in advance. Table 8.11 Control Bits for IDMA Transfer Channel Interrupt factor IDMA request bit IDMA enable bit Ch.0 Receive-buffer full RSRX0(D6/0x40292) DESRX0(D6/0x40296) Transmit-buffer empty RSTX0(D7/0x40292) DESTX0(D7/0x40296) Ch.1 Receive-buffer full RSRX1(D0/0x40293) DESRX1(D0/0x40297) Transmit-buffer empty RSTX1(D1/0x40293) DESTX1(D1/0x40297) EPSON S1C33L03 FUNCTION PART B-III-8-25...
Page 368 "1011". Transfer conditions, etc. must also be set on the HSDMA side. The HSDMA channel is invoked through generation of the interrupt factor. For details on HSDMA transfer, refer to "HSDMA (High-Speed DMA)". EPSON B-III-8-26 S1C33L03 FUNCTION PART...
Page 369 Ch.2 and Ch.3 do not have dedicated interrupt signals. Either a port input interrupt or 16-bit timer interrupt is selected, and interrupt handling is performed accordingly. For details, refer to the "Trap Vector" subsection in the "16-Bit Programmable Timers" or "Input/Output Ports" section. EPSON S1C33L03 FUNCTION PART B-III-8-27...
Page 370: I/O Memory Of Serial Interface
RXD17 Serial I/F Ch.1 receive data 0x0 to 0xFF(0x7F) 7-bit asynchronous receive data RXD16 RXD17(16) = MSB mode does not use register RXD15 RXD10 = LSB RXD17 (fixed at 0). RXD14 RXD13 RXD12 RXD11 RXD10 EPSON B-III-8-28 S1C33L03 FUNCTION PART...
Page 371 1 Inverted 0 Direct Valid only in IRRL2 Ch.2 IrDA I/F input logic inversion 1 Inverted 0 Direct asynchronous mode. IRMD21 Ch.2 interface mode selection IRMD2[1:0] I/F mode IRMD20 reserved IrDA 1.0 reserved General I/F EPSON S1C33L03 FUNCTION PART B-III-8-29...
Page 372 SIF Ch.1 transmit buffer empty 1 Enabled 0 Disabled enable register ESRX1 SIF Ch.1 receive buffer full ESERR1 SIF Ch.1 receive error ESTX0 SIF Ch.0 transmit buffer empty ESRX0 SIF Ch.0 receive buffer full ESERR0 SIF Ch.0 receive error EPSON B-III-8-30 S1C33L03 FUNCTION PART...
Page 373 0 TM16 Ch.4 RXD Full comp.B SIO2TS1 SIO Ch.2 transmit buffer empty 1 SIO Ch.2 0 TM16 Ch.5 TXD Emp. comp.A SIO2RS1 SIO Ch.2 receive buffer full 1 SIO Ch.2 0 TM16 Ch.5 RXD Full comp.B EPSON S1C33L03 FUNCTION PART B-III-8-31...
Page 374 To use the pin as SIN3, set SSIN3 (D0 / 0x402D7) to "1" and CFP33 (D3 / 0x402DC) to "0". To use the pin as P33 or #DMAACK1, set this bit to "0". At power-on, this bit is set to "0". EPSON B-III-8-32 S1C33L03 FUNCTION PART...
Page 375 To use the pin as SOUT2, set SSOUT2 (D1 / 0x402DB) to "1" and CFP26 (D6 / 0x402D8) to "0". To use the pin as P26 or TM4, set this bit to "0". At power-on, this bit is set to "0". EPSON S1C33L03 FUNCTION PART B-III-8-33...
Page 376 The serial-converted data is output from the SOUT pin beginning with the LSB, in which the bits set to "1" are output as high-level signals and those set to "0" output as low-level signals. This register can be read as well as written. At initial reset, the content of TXDx becomes indeterminate. EPSON B-III-8-34 S1C33L03 FUNCTION PART...
Page 377 "1". A framing error occurs when data with a stop bit = "0" is received in the asynchronous mode. The FERx flag is reset by writing "0". At initial reset, as well as when RXENx and TXENx both are set to "0", the FERx flag is set to "0" (no error). EPSON S1C33L03 FUNCTION PART B-III-8-35...
Page 378 TDBEx is set to "0" when transmit data is written to the transmit data register, and is set to "1" when this data is transferred to the shift register (transmit operation started). Transmit data is written to the transmit data register when this bit = "1". At initial reset, TDBEx is set to "1" (buffer empty). EPSON B-III-8-36 S1C33L03 FUNCTION PART...
Page 379 When RXENx for a channel is set to "1", the channel is enabled for receive operations. When RXENx is set to "0", the channel is disabled for receive operations. Always make sure the RXENx = "0" before setting the transfer mode and other conditions. At initial reset, RXENx is set to "0" (receive disabled). EPSON S1C33L03 FUNCTION PART B-III-8-37...
Page 380 STPBx is only valid in an asynchronous transfer. Two stop bits are selected by writing "1" to STPBx , and one stop bit is selected by writing "0". The start bit is fixed at 1 bit. Settings of STPBx are ignored during the performance of a clock-synchronized transfer. At initial reset, STPBx becomes indeterminate. EPSON B-III-8-38 S1C33L03 FUNCTION PART...
Page 381 "1", the sampling clock is generated from the input clock of the serial interface (output by an 8-bit programmable timer or input from #SCLKx) by dividing it by 8. When DIVMDx is set to "0", the input clock is divided by 16. At initial reset, DIVMDx becomes indeterminate. EPSON S1C33L03 FUNCTION PART B-III-8-39...
Page 382 Ch.1 interrupt level (D[2:0]) / Serial I/F Ch.1, A/D interrupt priority register (0x4026A) Sets the priority level of the serial-interface interrupt. The interrupt priority level can be set for each channel in the range of 0 to 7. At initial reset, PSIOx becomes indeterminate. EPSON B-III-8-40 S1C33L03 FUNCTION PART...
Page 383 Note also that the value to be written to reset the flag is "1" when the reset-only method (RSTONLY = "1") is used, and "0" when the read/write method (RSTONLY = "0") is used. At initial reset, all of these flags become indeterminate, so be sure to reset them in the software. EPSON S1C33L03 FUNCTION PART B-III-8-41...
Page 384 Write "1": SIO Ch.2 receive error Write "0": FP0 input Read: Valid Set to "1" to use the SIO Ch.2 receive error interrupt. Set to "0" to use the FP0 input interrupt. At power-on, this bit is set to "0". EPSON B-III-8-42 S1C33L03 FUNCTION PART...
Page 385 Write "1": 8-bit timer 4 underflow Write "0": FP5 input Read: Valid Set to "1" to use the 8-bit timer 4 underflow interrupt. Set to "0" to use the FP5 input interrupt. At power-on, this bit is set to "0". EPSON S1C33L03 FUNCTION PART B-III-8-43...
Page 386 Write "0": TM16 Ch.4 compare B Read: Valid Set to "1" to use the SIO Ch.3 receive-buffer full interrupt. Set to "0" to use the TM16 Ch.4 compare B interrupt. At power-on, this bit is set to "0". EPSON B-III-8-44 S1C33L03 FUNCTION PART...
Page 387 Write "0": TM16 Ch.2 compare A Read: Valid Set to "1" to use the 8-bit timer 5 underflow interrupt. Set to "0" to use the TM16 Ch.2 compare A interrupt. At power-on, this bit is set to "0". EPSON S1C33L03 FUNCTION PART B-III-8-45...
Page 388: Programming Notes
(11) When performing data transfer in the clock-synchronized mode, the division ratio of the prescaler and the reload data for the 8-bit programmable timer should be set so that the baud-rate is 1/4 of the system clock frequency or lower. (12) The serial interface operates only when the prescaler is operating. EPSON B-III-8-46 S1C33L03 FUNCTION PART...
Page 389: Input/Output Ports
Therefore, if these ports are not used, when the input level is fixed externally, it should be fixed at V or AV The K50 port is provided with a pull-up resistance that pulls the port up to AV EPSON S1C33L03 FUNCTION PART B-III-9-1...
Page 390: Input-Port Pins
V power supply to the AV power supply. 3) To fix the input level externally when the port is not used, the input pin should be connected to V or AV EPSON B-III-9-2 S1C33L03 FUNCTION PART...
Page 391: I/O Memory Of Input Ports
(V ) respectively. Since this register is a read-only register, writing to the register is ignored. When the ports set for A/D converter input are read, the value obtained is always "0". EPSON S1C33L03 FUNCTION PART B-III-9-3...
Page 392: I/O Ports (P Ports)
#DMAEND1/ / #DMAEND1 output (O) / Serial IF Ch.3 data SOUT3 output (I): Input mode, (O): Output mode, (Ex): Extended function : A 3-V system I/O voltage can only be used for the P10–P14 pins. EPSON B-III-9-4 S1C33L03 FUNCTION PART...
Page 393: I/O Control Register And I/O Modes
At hot start, the pins retain their state from prior to the reset. Note: If pins P10–P14, P15–P16, P30 and P34 are set for use with peripheral circuits, their pin functions vary depending on the input/output direction control by the IOC1x register. EPSON S1C33L03 FUNCTION PART B-III-9-5...
Page 394: I/O Memory Of I/O Ports
IOC14 P14 I/O control of the I/O control IOC13 P13 I/O control signals of the ports IOC12 P12 I/O control when it is read. (See IOC11 P11 I/O control detailed explanation.) IOC10 P10 I/O control EPSON B-III-9-6 S1C33L03 FUNCTION PART...
Page 395 P34 I/O control indicates the values IOC33 P33 I/O control of the I/O control IOC32 P32 I/O control signals of the ports IOC31 P31 I/O control when it is read. (See IOC30 P30 I/O control detailed explanation.) EPSON S1C33L03 FUNCTION PART B-III-9-7...
Page 396 "1" is read out as input data; if the pin voltage is low (V level), "0" is read out as input data. At cold start, all data bits are set to "0". At hot start, they retain their state from prior to the initial reset. EPSON B-III-9-8 S1C33L03 FUNCTION PART...
Page 397 To use the pin as #SCLK3, set SSCLK3 (D2 / 0x402D7) to "1" and CFP15 (D5 / 0x402D4) to "0". To use the pin as P15, EXCL4, or #DMAEND0, set this bit to "0". At power-on, this bit is set to "0". EPSON S1C33L03 FUNCTION PART B-III-9-9...
Page 398 To use the pin as #SRDY2, set SSRDY2 (D3 / 0x402DB) to "1" and CFP24 (D4 / 0x402D8) to "0". To use the pin as P24 or TM2, set this bit to "0". At power-on, this bit is set to "0". EPSON B-III-9-10 S1C33L03 FUNCTION PART...
Page 399 At cold start, CFEX0 and CFEX1 are set to "1" (function-extended pin) and other bits are set to "0" (I/O- port/peripheral-circuit pin). At hot start, CFEX retains its state from prior to the initial reset. B-III EPSON S1C33L03 FUNCTION PART B-III-9-11...
Page 400: Input Interrupt
SPT3[1:0] (D[7:6])/Port input interrupt select register 1 (0x402C6) FPT2 SPT2[1:0] (D[5:4])/Port input interrupt select register 1 (0x402C6) FPT1 SPT1[1:0] (D[3:2])/Port input interrupt select register 1 (0x402C6) FPT0 SPT0[1:0] (D[1:0])/Port input interrupt select register 1 (0x402C6) EPSON B-III-9-12 S1C33L03 FUNCTION PART...
Page 401 When the input signal goes to the selected status, the interrupt factor flag FP is set to "1" and, if other interrupt conditions set by the interrupt controller are met, an interrupt is generated. B-III EPSON S1C33L03 FUNCTION PART B-III-9-13...
Page 402: Key Input Interrupt
SPPK1 Input comparison register SCPK1 Address Input mask register SMPK1 Address K60, K64, P04, P24 K61, K65, P05, P25 K62, K66, P06, P26 K63, K67, P07, P27 Figure 9.4 Configuration of Key Input Interrupt Circuit EPSON B-III-9-14 S1C33L03 FUNCTION PART...
Page 403 K50, interrupt will be generated when non- conformity occurs between the contents of the four bits K51–K54 and the four bits input comparison register SCPK0[4:1]. Figure 9.5 FPK0 Interrupt Generation Example (when K5[4:0] is selected by SPPK[1:0]) EPSON S1C33L03 FUNCTION PART B-III-9-15...
Page 404: Control Registers Of The Interrupt Controller
For IDMA to be invoked, the IDMA request and IDMA enable bits shown in Table 9.9 must be set to "1" in advance. Transfer conditions, etc. must also be set on the IDMA side in advance. EPSON B-III-9-16 S1C33L03 FUNCTION PART...
Page 405 0x0C00054 FPT4 input interrupt: 0x0C00110 FPT5 input interrupt: 0x0C00114 B-III FPT6 input interrupt: 0x0C00118 FPT7 input interrupt: 0x0C0011C The base address of the trap table can be changed using the TTBR register (0x48134 to 0x48137). EPSON S1C33L03 FUNCTION PART B-III-9-17...
Page 406: I/O Memory For Input Interrupts
0 when being read. port input 0–3 Key input 1 1 Factor is 0 No factor is interrupt factor Key input 0 generated generated flag register Port input 3 Port input 2 Port input 1 Port input 0 EPSON B-III-9-18 S1C33L03 FUNCTION PART...
Page 407 1 Edge 0 Level interrupt SEPT6 FPT6 edge/level selection edge/level SEPT5 FPT5 edge/level selection select register SEPT4 FPT4 edge/level selection SEPT3 FPT3 edge/level selection SEPT2 FPT2 edge/level selection SEPT1 FPT1 edge/level selection SEPT0 FPT0 edge/level selection EPSON S1C33L03 FUNCTION PART B-III-9-19...
Page 408 Table 9.11 Selecting Pins for Port Input Interrupts Interrupt SPT settings system FPT7 FPT6 FPT5 FPT4 FPT3 FPT2 FPT1 FPT0 At cold start, SPT is set to "00". At hot start, SPT retains its state from prior to the initial reset. EPSON B-III-9-20 S1C33L03 FUNCTION PART...
Page 409 (except for the inputs disabled from interrupt by the SMPK register). At cold start, SCPK is set to "0" (rising edge). At hot start, SCPK retains its state from prior to the initial reset. EPSON S1C33L03 FUNCTION PART B-III-9-21...
Page 410 EP and EK are interrupt enable bits corresponding to the port-input interrupt and the key-input interrupt, respectively. Interrupts for input systems set to "1" are enabled, and interrupts for input systems set to "0" are disabled. At initial reset, these bits are set to "0" (interrupt disabled). EPSON B-III-9-22 S1C33L03 FUNCTION PART...
Page 411 Note also that the value to be written to reset the flag is "1" when the reset-only method (RSTONLY = "1") is used, and "0" when the read/write method (RSTONLY = "0") is used. At initial reset, all the flags become indeterminate, so be sure to reset them in the software. EPSON S1C33L03 FUNCTION PART B-III-9-23...
Page 412 If DEP is set to "1", the IDMA request by the interrupt factor is enabled. If the register bit is set to "0", the IDMA request is disabled. After an initial reset, DEP is set to "0" (IDMA disabled). EPSON B-III-9-24 S1C33L03 FUNCTION PART...
Page 413: Programming Notes
Therefore, a restart is effected when the input level from a port is active by level. Consequently, the system design should assume that a restart by means of port input from the SLEEP state or HALT2 state is performed by level. B-III EPSON S1C33L03 FUNCTION PART B-III-9-25...
Page 414 III PERIPHERAL BLOCK: INPUT/OUTPUT PORTS THIS PAGE IS BLANK. EPSON B-III-9-26 S1C33L03 FUNCTION PART...
Page 415: Analog Block
S1C33L03 FUNCTION PART IV ANALOG BLOCK...
Page 417: Introduction
C33_PERI Pads (A/D converter) (Prescaler, 8-bit timer, 16-bit timer, Clock timer, Serial interface, Ports) C33 Analog Block C33 Peripheral Block Figure 1.1 Analog Block Note: Internal ROM is not provided in the S1C33L03. B-IV Intro EPSON S1C33L03 FUNCTION PART B-IV-1-1...
Page 418 IV ANALOG BLOCK: INTRODUCTION THIS PAGE IS BLANK. EPSON B-IV-1-2 S1C33L03 FUNCTION PART...
Page 419: A/D Converter
Successive Analog Analog Data approximation input block register block decoder Control circuit #ADTRG Interrupt 8-bit timer 0 control circuit 16-bit timer 0 B-IV Clock Interrupt request Prescaler generator Figure 2.1 Structure of A/D Converter EPSON S1C33L03 FUNCTION PART B-IV-2-1...
Page 420: I/O Pins Of A/D Converter
At cold start, the #ADTRG and AD[7:0] pins all are set for input ports Kxx (function select bit CFKxx = "0"). When using these pins for the A/D converter, write "1" to the function select bit CFKxx. At hot start, these pins retain their state from prior to the reset. EPSON B-IV-2-2 S1C33L03 FUNCTION PART...
Page 421: Setting A/D Converter
To enable A/D conversions in multiple channels to be performed successively through one convert operation, specify the conversion start and conversion end channels. Conversion start channel: CS[2:0] (D[2:0]) / A/D channel register (0x40243) Conversion end channel: CE[2:0] (D[5:3]) / A/D channel register (0x40243) EPSON S1C33L03 FUNCTION PART B-IV-2-3...
Page 422 For details on how to set a timer, refer to the explanation of each programmable timer in this manual. 3. Software trigger Writing "1" to ADST (D1) / A/D enable register (0x40244) in the software serves as a trigger to start A/D conversion. EPSON B-IV-2-4 S1C33L03 FUNCTION PART...
Page 423: Control And Operation Of A/D Conversion
When a trigger is input while ADE = "1", A/D conversion is started. If a software trigger has been selected, A/D conversion is started by writing "1" to ADST (D1) / A/D enable register (0x40244). Only the trigger selected using TS[1:0] (D[4:3]) / A/D trigger register (0x40242) are valid; no other trigger is accepted. EPSON S1C33L03 FUNCTION PART B-IV-2-5...
Page 424 Note that writing "0" to ADE cannot terminate the A/D conversion under-way (ADST = "1"). Note: Once A/D conversion ends, further A/D conversion will not be performed correctly if restarted within an interval shorter than one cycle of the A/D converter operating clock set by the prescaler. EPSON B-IV-2-6 S1C33L03 FUNCTION PART...
Page 425: A/D Converter Interrupt And Dma
HSDMA side. If the A/D interrupt factor is selected as the HSDMA trigger, the HSDMA channel is invoked through generation of the interrupt factor. For details on HSDMA transfer, refer to "HSDMA (High-Speed DMA)". EPSON S1C33L03 FUNCTION PART B-IV-2-7...
Page 426 IV ANALOG BLOCK: A/D CONVERTER Trap vector The A/D converter's interrupt trap-vector default address is set to 0x0C00100. The base address of the trap table can be changed using the TTBR register (0x48134 to 0x48137). EPSON B-IV-2-8 S1C33L03 FUNCTION PART...
Page 427: I/O Memory Of A/D Converter
Reset by writing 0. A/D sampling 0040245 D7–2 – – – – – 0 when being read. register Input signal sampling time setup ST[1:0] Sampring time Use with 9 clocks. 9 clocks 7 clocks 5 clocks 3 clocks EPSON S1C33L03 FUNCTION PART B-IV-2-9...
Page 428 If the function select bit for a pin is set to "0", the pin is set for an input port. At cold start, CFK is set to "0" (input port). At hot start, CFK retains its state from prior to the initial reset. EPSON B-IV-2-10...
Page 429 Analog inputs can be A/D-converted successively from the channel set using this bit to the channel set using CE in one operation. If only one channel is to be A/D converted, set the same channel number in both the CS and CE bits. At initial reset, CS is set to "0" (AD0). EPSON S1C33L03 FUNCTION PART B-IV-2-11...
Page 430 OWE is not set. Once OWE is set to "1", it remains set until it is reset by writing "0" in the software. At initial reset, OWE is set to "0" (normal). EPSON B-IV-2-12 S1C33L03 FUNCTION PART...
Page 431 CPU is generated for the interrupt factor that has occurred. If interrupts are enabled at the setting of IDMA, an interrupt is generated under the above conditions after the data transfer by IDMA is completed. EPSON S1C33L03 FUNCTION PART B-IV-2-13...
Page 432 If DEADE is set to "1", the IDMA request by the interrupt factor is enabled. If this bit is set to "0", the IDMA request is disabled. After an initial reset, DEADE is set to "0" (IDMA disabled). EPSON B-IV-2-14 S1C33L03 FUNCTION PART...
Page 433: Programming Notes
ADD[9:0] is overwritten when the same conversion results have already been read (when ADF is reset to B-IV "0"). This may occur when the program reads the same results twice or more for verification or other purposes. EPSON S1C33L03 FUNCTION PART B-IV-2-15...
Page 434 IV ANALOG BLOCK: A/D CONVERTER THIS PAGE IS BLANK. EPSON B-IV-2-16 S1C33L03 FUNCTION PART...
Page 435: Dma Block
S1C33L03 FUNCTION PART V DMA BLOCK...
Page 437: Introduction
C33_ADC C33_PERI Pads (A/D converter) (Prescaler, 8-bit timer, 16-bit timer, Clock timer, Serial interface, Ports) C33 Analog Block C33 Peripheral Block Figure 1.1 DMA Block Note: Internal ROM is not provided in the S1C33L03. Intro EPSON S1C33L03 FUNCTION PART B-V-1-1...
Page 438 V DMA BLOCK: INTRODUCTION THIS PAGE IS BLANK. EPSON B-V-1-2 S1C33L03 FUNCTION PART...
Page 439: Hsdma (High-Speed Dma)
In this manual, however, channel numbers 0 to 3 are designated with an "x" except where they must be distinguished, as the explanation is the same for all channels. • The single-address transfer method does not allow data transfer to/from the SDRAM. EPSON S1C33L03 FUNCTION PART B-V-2-1...
Page 440: I/O Pins Of Hsdma
If this pin is directed for input, it functions as a 16-bit programmable timer's event counter input and cannot be used to output the #DMAENDx signal. At cold start, this pin is set for input. At hot start, it retains the previous status. EPSON B-V-2-2 S1C33L03 FUNCTION PART...
Page 441: Programming Control Information
HSDMA DATSIZE2: Ch. 2 transfer data size (DE) / HSDMA Ch. 2 high-order source address set-up register (0x48246) DATSIZE3: Ch. 3 transfer data size (DE) / HSDMA Ch. 3 high-order source address set-up register (0x48256) EPSON S1C33L03 FUNCTION PART B-V-2-3...
Page 442 Ch. 1 source address [27:16] (D[B:0]) / Ch. 1 high-order source address set-up register (0x48236) S2ADRH[11:0]: Ch. 2 source address [27:16] (D[B:0]) / Ch. 2 high-order source address set-up register (0x48246) S3ADRH[11:0]: Ch. 3 source address [27:16] (D[B:0]) / Ch. 3 high-order source address set-up register (0x48256) EPSON B-V-2-4 S1C33L03 FUNCTION PART...
Page 443 The address is incremented by an amount equal to the data size set by DATSIZEx when one data transfer is completed. The address that has been incremented during transfer does not return to the initial value. HSDMA EPSON S1C33L03 FUNCTION PART B-V-2-5...
Page 444: Setting The Registers In Single-Address Mode
Ch. 2 memory address [27:16] (D[B:0]) / Ch. 2 high-order source address set-up register (0x48246) S3ADRL[15:0]: Ch. 3 memory address [15:0] (D[F:0]) / Ch. 3 low-order source address set-up register (0x48254) S3ADRH[11:0]: Ch. 3 memory address [27:16] (D[B:0]) / Ch. 3 high-order source address set-up register (0x48256) EPSON B-V-2-6 S1C33L03 FUNCTION PART...
Page 445: Enabling/Disabling Dma Transfer
Note that the control information cannot be set when HSx_EN = "1". When HSx_EN is set to "0", HSDMA requests are no longer accepted. When a DMA transfer is completed (transfer counter = 0), HSx_EN is reset to "0" to disable the following trigger inputs. HSDMA EPSON S1C33L03 FUNCTION PART B-V-2-7...
Page 446: Trigger Factor
By writing "1" to this bit, the set trigger flag can be cleared if the DMA transfer has not been started. When this bit is read, "1" indicates that the flag is set and "0" indicates that the flag is cleared. EPSON B-V-2-8...
Page 447: Operation Of Hsdma
(3) The addresses are incremented or decremented according to the SxIN/DxIN settings. (4) The transfer counter is decremented. (5) The HSDMA enable bit HSx_EN is cleared and HSDMA interrupt factor flag in ITC is set when the transfer counter reaches 0 (when DINTENx = "1"). EPSON S1C33L03 FUNCTION PART B-V-2-9...
Page 448 (5) Steps (1) to (4) are repeated until the transfer counter reaches 0. (6) The HSDMA enable bit HSx_EN is cleared and HSDMA interrupt factor flag in ITC is set when the transfer counter reaches 0 (when DINTENx = "1"). EPSON B-V-2-10 S1C33L03 FUNCTION PART...
Page 449 (5) If SxIN or DxIN is "10", the address is recycled to the initial value. (6) The transfer counter is decremented. (7) The HSDMA enable bit HSx_EN is cleared and HSDMA interrupt factor flag in ITC is set when the transfer counter reaches 0 (when DINTENx = "1"). EPSON S1C33L03 FUNCTION PART B-V-2-11...
Page 450: Operation In Single-Address Mode
When the transfer counter reaches 0, the end-of-transfer signal is output from the #DMAENDx pin indicating that a specified number of transfers has been completed. At the same time, the interrupt factor for the completion of HSDMA is generated. EPSON B-V-2-12 S1C33L03 FUNCTION PART...
Page 451: Timing Chart
Example: Page mode, RAS: 1 cycle; CAS: 2 cycles; Precharge: 1 cycle Read cycle Write cycle BCLK COL #1 COL #2 COL #1 COL #2 A[11:0] #RASx #HCAS/ #LCAS #DMAEND Figure 2.7 #DMAEND Signal Output Timing (DRAM) HSDMA EPSON S1C33L03 FUNCTION PART B-V-2-13...
Page 452 Example: Page mode, RAS: 1 cycle; CAS: 2 cycles; Precharge: 1 cycle BCLK COL #1 COL #2 A[11:0] #RASx #HCAS/ #LCAS #DMAACK #DMAEND Figure 2.10 #DMAACK/#DMAEND Signal Output Timing (DRAM) Note: The single-address transfer method does not allow data transfer to/from the SDRAM. EPSON B-V-2-14 S1C33L03 FUNCTION PART...
Page 453: Interrupt Function Of Hsdma
CPU actually accepts a HSDMA interrupt. For details about the interrupt control register and for the device operation when an interrupt occurs, refer to "ITC (Interrupt Controller)". HSDMA EPSON S1C33L03 FUNCTION PART B-V-2-15...
Page 454 Channel 0 end-of-transfer interrupt: 0x0C00058 Channel 1 end-of-transfer interrupt: 0x0C0005C Channel 2 end-of-transfer interrupt: 0x0C00060 Channel 3 end-of-transfer interrupt: 0x0C00064 Note that the trap table base address can be modified using the TTBR registers (0x48134 to 0x48137). EPSON B-V-2-16 S1C33L03 FUNCTION PART...
Page 455: I/O Memory Of Hsdma
DMA Ch. 0/1, DEHDM1 High-speed DMA Ch.1 16-bit timer 0 DEHDM0 High-speed DMA Ch.0 IDMA enable DEP3 Port input 3 register DEP2 Port input 2 DEP1 Port input 1 DEP0 Port input 0 HSDMA EPSON S1C33L03 FUNCTION PART B-V-2-17...
Page 456 1 #DMAREQ3 0 K54 CFK53 K53 function selection 1 #DMAREQ2 0 K53 CFK52 K52 function selection 1 #ADTRG 0 K52 CFK51 K51 function selection 1 #DMAREQ1 0 K51 CFK50 K50 function selection 1 #DMAREQ0 0 K50 EPSON B-V-2-18 S1C33L03 FUNCTION PART...
Page 457 TC0_L5 counter TC0_L4 Ch.0 transfer counter[15:8] register TC0_L3 (single/successive transfer mode) TC0_L2 TC0_L1 TC0_L0 BLKLEN07 Ch.0 block length BLKLEN06 (block transfer mode) BLKLEN05 BLKLEN04 Ch.0 transfer counter[7:0] BLKLEN03 (single/successive transfer mode) BLKLEN02 BLKLEN01 BLKLEN00 HSDMA EPSON S1C33L03 FUNCTION PART B-V-2-19...
Page 458 D) Ch.0 destination address[15:0] DMA Ch.0 (HW) D0ADRL14 S) Invalid low-order D0ADRL13 destination D0ADRL12 address set-up D0ADRL11 register D0ADRL10 D0ADRL9 Note: D0ADRL8 D) Dual address D0ADRL7 mode D0ADRL6 S) Single D0ADRL5 address D0ADRL4 mode D0ADRL3 D0ADRL2 D0ADRL1 D0ADRL0 EPSON B-V-2-20 S1C33L03 FUNCTION PART...
Page 459 – – Undefined in read. Note: TC1_H7 Ch.1 transfer counter[15:8] D) Dual address TC1_H6 (block transfer mode) mode TC1_H5 S) Single TC1_H4 Ch.1 transfer counter[23:16] address TC1_H3 (single/successive transfer mode) mode TC1_H2 TC1_H1 TC1_H0 HSDMA EPSON S1C33L03 FUNCTION PART B-V-2-21...
Page 460 D) Ch.1 destination address[15:0] DMA Ch.1 (HW) D1ADRL14 S) Invalid low-order D1ADRL13 destination D1ADRL12 address set-up D1ADRL11 register D1ADRL10 D1ADRL9 Note: D1ADRL8 D) Dual address D1ADRL7 mode D1ADRL6 S) Single D1ADRL5 address D1ADRL4 mode D1ADRL3 D1ADRL2 D1ADRL1 D1ADRL0 EPSON B-V-2-22 S1C33L03 FUNCTION PART...
Page 461 – – Undefined in read. Note: TC2_H7 Ch.2 transfer counter[15:8] D) Dual address TC2_H6 (block transfer mode) mode TC2_H5 S) Single TC2_H4 Ch.2 transfer counter[23:16] address TC2_H3 (single/successive transfer mode) mode TC2_H2 TC2_H1 TC2_H0 HSDMA EPSON S1C33L03 FUNCTION PART B-V-2-23...
Page 462 D) Ch.2 destination address[15:0] DMA Ch.2 (HW) D2ADRL14 S) Invalid low-order D2ADRL13 destination D2ADRL12 address set-up D2ADRL11 register D2ADRL10 D2ADRL9 Note: D2ADRL8 D) Dual address D2ADRL7 mode D2ADRL6 S) Single D2ADRL5 address D2ADRL4 mode D2ADRL3 D2ADRL2 D2ADRL1 D2ADRL0 EPSON B-V-2-24 S1C33L03 FUNCTION PART...
Page 463 – – Undefined in read. Note: TC3_H7 Ch.3 transfer counter[15:8] D) Dual address TC3_H6 (block transfer mode) mode TC3_H5 S) Single TC3_H4 Ch.3 transfer counter[23:16] address TC3_H3 (single/successive transfer mode) mode TC3_H2 TC3_H1 TC3_H0 HSDMA EPSON S1C33L03 FUNCTION PART B-V-2-25...
Page 464 D) Ch.3 destination address[15:0] DMA Ch.3 (HW) D3ADRL14 S) Invalid low-order D3ADRL13 destination D3ADRL12 address set-up D3ADRL11 register D3ADRL10 D3ADRL9 Note: D3ADRL8 D) Dual address D3ADRL7 mode D3ADRL6 S) Single D3ADRL5 address D3ADRL4 mode D3ADRL3 D3ADRL2 D3ADRL1 D3ADRL0 EPSON B-V-2-26 S1C33L03 FUNCTION PART...
Page 465 If CFP1x is set to "0", the pin is set for an I/O port. At cold start, CFP1x is set to "0" (I/O port). At hot start, CFP1x retains the previous status before an initial reset. EPSON S1C33L03 FUNCTION PART...
Page 466 When CFEXx is set to "0", the corresponding CFP bit becomes effective. At cold start, these bits are set to "0" (I/O-port/serial interface I/O pin). At hot start, these bits retain the previous status before an initial reset. EPSON B-V-2-28 S1C33L03 FUNCTION PART...
Page 467 By reading HSx_TF, the flag status can be checked. Writing "1" to HSx_TF clears the trigger flag if the DMA transfer has not been started. At initial reset, HSx_TF is set to "0". EPSON S1C33L03 FUNCTION PART B-V-2-29...
Page 468 Data transfer from an external I/O device to external memory is performed by writing "1" to DxDIR. Data transfer from external memory to an external I/O is performed by writing "0". At initial reset, DxDIR is set to "0" (memory to I/O). This bit is effective only in single-address mode. EPSON B-V-2-30 S1C33L03 FUNCTION PART...
Page 469 However, if SxIN is set to "10", the source address that has been incremented during a block transfer recycles back to the initial value when the block transfer is completed. At initial reset, SxIN is set to "00" (Fixed). EPSON S1C33L03 FUNCTION PART B-V-2-31...
Page 470 Even when the counter is 0, a DMA request is accepted and the counter is decremented to "0xFFFF" (or "0xFFFFFF"). Be sure to disable DMA transfers (HSx_EN = "0") before writing and reading to and from the counter. At initial reset, these bits are not initialized. EPSON B-V-2-32 S1C33L03 FUNCTION PART...
Page 471 PHSD3L2–PHSD3L0: Ch. 3 interrupt level (D[6:4]) / HSDMA Ch. 2/3 interrupt priority register (0x40264) Set the priority level of an end-of-DMA interrupt in the range of 0 to 7. At initial reset, these registers become indeterminate. EPSON S1C33L03 FUNCTION PART B-V-2-33...
Page 472 (RSTONLY = "1") and "0" when using the read/write method (RSTONLY = "0"). Be careful not to confuse these two cases. The FHDMx flag becomes indeterminate when initially reset, so be sure to reset the flag in the software application. EPSON B-V-2-34 S1C33L03 FUNCTION PART...
Page 473 DEHDM0 and DEHDM1 are the IDMA enable bits for HSDMA channels 0 and 1, respectively. If DEHDMx is set to "1", the IDMA request by the interrupt factor is enabled. If the bit is set to "0", the IDMA request is disabled. At initial reset, DEHDMx is set to "0" (IDMA disabled). HSDMA EPSON S1C33L03 FUNCTION PART B-V-2-35...
Page 474: Programming Notes
If a DMA trigger occurs and DMA is invoked while the CPU is stopped after HALT mode execution, erroneous operation will result. Ensure that DMA is not invoked in HALT mode. In HALT2 mode, DMA is not invoked since the DMA and BCU clocks are stopped. EPSON B-V-2-36 S1C33L03 FUNCTION PART...
Page 475: Idma (Intelligent Dma)
Note: The control information must be written only when the channel to be set does not start a DMA transfer. If a DMA transfer starts when the control information is being written to the RAM, proper transfer cannot performed. Reading the control information can always be done. IDMA EPSON S1C33L03 FUNCTION PART B-V-3-1...
Page 476 In block transfer mode, a transfer count can be specified using up to 16 bits. Set this value here. In single transfer and successive transfer modes, a transfer count can be specified using up to 24 bits. Set a 16-bit high- order value here. EPSON B-V-3-2 S1C33L03 FUNCTION PART...
Page 477 In this mode, a transfer operation invoked by one trigger is completed after transferring one block of data of the size set by BLKLEN. If a block transfer need to be performed a number of times as set by the IDMA transfer counter, an equal number of triggers are required. EPSON S1C33L03 FUNCTION PART B-V-3-3...
Page 478 Since the control information is placed in RAM, it can be rewritten. However, before rewriting the content of this information, make sure that no DMA transfer is generated in the channel whose information you are going to rewrite. EPSON B-V-3-4 S1C33L03 FUNCTION PART...
Page 479: Idma Invocation
End of A/D conversion RADE (D2/0x40293) DEADE (D2/0x40297) Ports Port input 4 RP4 (D4/0x40293) DEP4 (D4/0x40297) Port input 5 RP5 (D5/0x40293) DEP5 (D5/0x40297) Port input 6 RP4 (D6/0x40293) DEP4 (D6/0x40297) Port input 7 RP7 (D7/0x40293) DEP7 (D7/0x40297) IDMA EPSON S1C33L03 FUNCTION PART B-V-3-5...
Page 480 To generate an interrupt at the end of an IDMA transfer, the DINTEN (end-of-transfer interrupt enable) bits in the IDMA control information for the first IDMA channel to be invoked and all the channels to be linked must be set to "1". EPSON B-V-3-6 S1C33L03 FUNCTION PART...
Page 481 IDMA transfer. The IDMA transfer by the hardware trigger is not executed since the interrupt factor is reset when the DMA transfer is completed. However, an operation like this cannot be recommended. IDMA EPSON S1C33L03 FUNCTION PART B-V-3-7...
Page 482: Operation Of Idma
Not changed ("1") Not changed ("1") Transfer counter = "0", DINTEN = "1": Not changed ("1") Reset ("0") Not changed ("1") Transfer counter = "0", DINTEN = "0": Reset ("0") Not changed ("1") Reset ("0") EPSON B-V-3-8 S1C33L03 FUNCTION PART...
Page 483 Not changed ("1") Not changed ("1") Transfer counter = "0", DINTEN = "1": Not changed ("1") Reset ("0") Not changed ("1") Transfer counter = "0", DINTEN = "0": Reset ("0") Not changed ("1") Reset ("0") IDMA EPSON S1C33L03 FUNCTION PART B-V-3-9...
Page 484 Not changed ("1") Not changed ("1") Transfer counter = "0", DINTEN = "1": Not changed ("1") Reset ("0") Not changed ("1") Transfer counter = "0", DINTEN = "0": Reset ("0") Not changed ("1") Reset ("0") EPSON B-V-3-10 S1C33L03 FUNCTION PART...
Page 485 DMA transfer by the interrupt factor flag. Software trigger Data transfer Transfer counter IDMA DINTEN FIDMA (D4/0x40281) Interrupt request Figure 3.5 Operation when Invoked by Software Trigger EPSON S1C33L03 FUNCTION PART B-V-3-11...
Page 486: Linking
IDMA transfer is generated when a transfer operation in each of the linked channels is completed. The channel in which an interrupt request has been generated can be verified by reading out the transfer counter. Transfer operations in each channel are performed as described earlier. EPSON B-V-3-12 S1C33L03 FUNCTION PART...
Page 487: Interrupt Function Of Intelligent Dma
IDMA interrupt level which is set by the interrupt priority register that the CPU actually accepts an IDMA interrupt request. For details about these interrupt control registers, and for information on device operation when an interrupt occurs, refer to "ITC (Interrupt Controller)". EPSON S1C33L03 FUNCTION PART B-V-3-13...
Page 488: I/O Memory Of Intelligent Dma
0048204 DSTART IDMA start 1 IDMA start 0 Stop register D6–0 DCHN IDMA channel number 0 to 127 IDMA enable 0048205 D7–1 – reserved – – – register IDMAEN IDMA enable 1 Enabled 0 Disabled EPSON B-V-3-14 S1C33L03 FUNCTION PART...
Page 489 This bit controls the interrupt generated upon completion of IDMA transfer. The interrupt is enabled by setting this bit to "1" and disabled by setting this bit to "0". At initial reset, EIDMA is set to "0" (interrupt disable). EPSON S1C33L03 FUNCTION PART B-V-3-15...
Page 490 (RSTONLY = "1") and "0" when using the read/write method (RSTONLY = "0"). Be careful not to confuse these two cases. This flag becomes indeterminate when initially reset, so be sure to reset it in the software application. EPSON B-V-3-16 S1C33L03 FUNCTION PART...
Page 491: Programming Notes
If a DMA trigger occurs and DMA is invoked while the CPU is stopped after HALT mode execution, erroneous operation will result. Ensure that DMA is not invoked in HALT mode. In HALT2 mode, DMA is not invoked since the DMA and BCU clocks are stopped. IDMA EPSON S1C33L03 FUNCTION PART B-V-3-17...
Page 492 V DMA BLOCK: IDMA (Intelligent DMA) THIS PAGE IS BLANK. EPSON B-V-3-18 S1C33L03 FUNCTION PART...
Page 493: Sdram Controller Block
S1C33L03 FUNCTION PART VI SDRAM CONTROLLER BLOCK...
Page 495: Introduction
Pads (A/D converter) (Prescaler, 8-bit timer, 16-bit timer, Clock timer, Serial interface, Ports) C33 Analog Block C33 Peripheral Block Figure 1.1 SDRAM Controller Block Note: Internal ROM is not provided in the S1C33L03. B-VI Intro EPSON S1C33L03 FUNCTION PART B-VI-1-1...
Page 496 VI SDRAM CONTROLLER BLOCK: INTRODUCTION THIS PAGE IS BLANK. EPSON B-VI-1-2 S1C33L03 FUNCTION PART...
Page 497: Sdram Interface
Bus command registers Internal #CE7/13 SDRAM decoder Internal #CE8/14 command SDA10, SDCKE, #SDCE0/1 decoder SDRAM state Internal #WAIT #SDCAS, #SDRAS control #SDWE, HDQM, LDQM B-VI Refresh OSC3 clock counter SDRAM Figure 2.1 SDRAM Controller Block Diagram EPSON S1C33L03 FUNCTION PART B-VI-2-1...
Page 498: I/O Pins And Connection
(4M x 16 bits x 4 banks) SDA[12:11](A[13:12]) A[12:11] SDA10(P33) SDA[9:0](A[10:1]) A[9:0] SDBA[1:0](A[15:14]) BA[1:0] D[15:0] DQ[15:0] BCLK SDCKE(P20) #SDCE0/1(#CE7/8) #SDCAS(#HCAS) #CAS #SDRAS(#LCAS) #RAS #SDWE(P21) HDQM(P32) DQMU LDQM(P15) DQML Figure 2.2 Connecting a 16-bit SDRAM (32MB) EPSON B-VI-2-2 S1C33L03 FUNCTION PART...
Page 499 (4M x 8 bits x 4 banks) SDA[12:11](A[13:12]) A[12:11] SDA10(P33) SDA[9:0](A[10:1]) A[9:0] SDBA[1:0](A[15:14]) BA[1:0] D[15:8] DQ[7:0] B-VI BCLK SDCKE(P20) #SDCE0/1(#CE7/8) #SDCAS(#HCAS) #CAS SDRAM #SDRAS(#LCAS) #RAS #SDWE(P21) HDQM(P32) For big endian Figure 2.4 Connecting an 8-bit SDRAM (16MB) EPSON S1C33L03 FUNCTION PART B-VI-2-3...
Page 500 8M bytes 64M (2M x 8 bits x 4 banks) 8M bytes 16M bytes 16M (512 x 16 bits x 2 banks) 2M bytes 16M (1M x 8 bits x 2 banks) 2M bytes 4M bytes EPSON B-VI-2-4 S1C33L03 FUNCTION PART...
Page 501: Sdram Controller Configuration
When only the SDRAM is read and no other external device is accessed, set the output disable delay time of areas 7/8 to 0.5 cycles (A8DF[1:0] = "00") in order to reduce the SDRAM access time. EPSON S1C33L03 FUNCTION PART...
Page 502: Sdram Setting Conditions
SDRTRCD[1:0](D[7:6])/SDRAM timing set-up register 2 (0x39FFC5) 1 or 2 clocks 2 clocks SDRTRSC(D5)/SDRAM timing set-up register 2 (0x39FFC5) 1 to 4 clocks 4 clocks SDRTRRD[1:0](D[4:3])/SDRAM timing set-up register 2 (0x39FFC5) Always set CAS latency to 2. EPSON B-VI-2-6 S1C33L03 FUNCTION PART...
Page 503 Area 13&14 32MB Area 13 Area 14 16MB x 2 Area 7 = 0x400000–0x5FFFFF, Area 8 = 0x600000–0x7FFFFF, Area 7&8 = 0x400000–0x7FFFFF Area 13 = 0x2000000–0x2FFFFFF, Area 14 = 0x3000000–0x3FFFFFF, Area 13&14 = 0x2000000–0x3FFFFFF B-VI SDRAM EPSON S1C33L03 FUNCTION PART B-VI-2-7...
Page 504 = "01" or "10"), the MSB of the bank address (A(m+n+p) for 16 bits or A(m+n+p-1) for 8 bits) is replaced with the value shown below. • Value is "0" when accessing area 7/13 • Value is "1" when accessing area 8/14 EPSON B-VI-2-8 S1C33L03 FUNCTION PART...
Page 505 (D[6:5])/SDRAM mode set-up register (0x39FFC3) to "10" (CAS latency = 2) before accessing the SDRAM. BCLK Command ACTV READ SDCKE #SDCEx #SDRAS #SDCAS #SDWE SDBA[1:0] SDA[12:0] DQ[15:0] DATA CAS latency = 2 Figure 2.5 CAS Latency B-VI SDRAM EPSON S1C33L03 FUNCTION PART B-VI-2-9...
Page 506 When SDRBI is set to "0", the SDRAM controller issues the precharge command every time the bank to be accessed is changed. This reduces current consumption than that of the bank interleaved access, so set SDRBI to "0" if bank is hardly changed through a series of access. EPSON B-VI-2-10 S1C33L03 FUNCTION PART...
Page 507 Note: When the auto-refresh command is executed, the following command may be issued 3 or 4 CPU_CLK cycles from that point regardless of the t value set in the SDRTRC[2:0] (D[2:0])/SDRAM timing set-up register 1 (0x39FFC4). Therefore, use SDRAMs with 75 ns or less of t B-VI SDRAM EPSON S1C33L03 FUNCTION PART B-VI-2-11...
Page 508: Sdram Operation
BCLK (BCU_CLK) BCLK (SD_CLK when SDRCLK = "1") BCLK (SD_CLK when SDRCLK = "0") SDCKE Self refresh Access to Access to other Access to the the SDRAM external memory internal memory Figure 2.9 SDRAM Clock Operation EPSON B-VI-2-12 S1C33L03 FUNCTION PART...
Page 509: Power-Up And Initialization
In addition to being reset at power-on, SDRMRS is reset to "1" by writing "0" to SDRENA or writing "1" to SDRINI. This completes the SDRAM initialization sequence, allowing access to the SDRAM. B-VI SDRAM EPSON S1C33L03 FUNCTION PART B-VI-2-13...
Page 510: Sdram Commands
V = valid, X = don’t care, L = low level, H = high level Because all of these commands are output by the SDRAM controller as necessary, they do not need to be controlled by a user program, except for the commencement of initialization by SDRINI. EPSON B-VI-2-14 S1C33L03 FUNCTION PART...
Page 511: Burst Read Cycle
ACTV READ NOP READ SDCKE #SDCEx #SDRAS #SDCAS #SDWE SDBA[1:0] SDA[10] B-VI SDA[12:11, 9:0] COL1 COL2 LDQM/HDQM SDRAM DQ[15:0] D(1-1) D(1-2) D(2-1) D(2-2) CAS latency CAS latency Figure 2.11 Burst Read in the Same Page EPSON S1C33L03 FUNCTION PART B-VI-2-15...
Page 512: Single Read/Single Write
Figure 2.13 Single Read to Single Write (different page) BCLK Command ACTV READ WRIT NOP SDCKE #SDCEx #SDRAS #SDCAS #SDWE SDBA[1:0] SDA[10] ROW1 SDA[12:11, 9:0] ROW1 COLn COLm LDQM/HDQM DQ[15:0] (n+1) (n+2) CAS latency Figure 2.14 Burst Read to Single Write (same page) EPSON B-VI-2-16 S1C33L03 FUNCTION PART...
Page 513: Refresh Mode
4,096 Therefore, set any value equal to or less than 286 (0x11E) for SDRARFC. BCLK Command PALL NOP SDCKE #SDCEx #SDRAS #SDCAS #SDWE SDBA[1:0] SDA[10] SDA[12:11, 9:0] LDQM/HDQM DQ[15:0] Figure 2.15 Auto Refresh B-VI SDRAM EPSON S1C33L03 FUNCTION PART B-VI-2-17...
Page 514 "0". Therefore, it is possible to determine whether or not self-refresh is in operation by reading this status register. Furthermore, SDRAM clock output during self-refresh can be turned off in order to reduce the chip’s power consumption by setting the SDRCLK (D3)/SDRAM control register (0x39FFC1) to "0". EPSON B-VI-2-18 S1C33L03 FUNCTION PART...
Page 515: Power-Down Mode
Self refresh Hi-Z Hi-Z CKE (external device) Hi-Z SDCKE (S1C33) Hi-Z SDRAM control (S1C33) Self refresh Self refresh Hi-Z Hi-Z SDRAM control (external device) Self refresh Self refresh Figure 2.17 Bus Release Procedure B-VI SDRAM EPSON S1C33L03 FUNCTION PART B-VI-2-19...
Page 516 Note: If the SDRAM is not accessed after the bus is released, pull the SDRAM’s CKE pin down to low to keep the self-refresh mode in order to maintain the SDRAM data while the bus is released. EPSON B-VI-2-20 S1C33L03 FUNCTION PART...
Page 517: I/O Memory Of Sdram Interface
SDRAM t spec SDRTRAS[2:0] Number of clocks timing set-up SDRTRAS1 register 1 SDRTRAS0 D4–3 SDRTRP1 SDRAM t spec SDRTRP[1:0] Number of clocks SDRTRP0 D2–0 SDRTRC2 SDRAM t spec SDRTRC[2:0] Number of clocks SDRTRC1 SDRTRC0 B-VI SDRAM EPSON S1C33L03 FUNCTION PART B-VI-2-21...
Page 518 SDRAM current refresh mode 1 Auto refresh 0 Self refresh D5–0 – reserved – – – 0 when being read. Note: Do not access addresses 0x039FFCB to 0x039FFCD, because they are reserved for testing the SDRAM controller. EPSON B-VI-2-22 S1C33L03 FUNCTION PART...
Page 519 0 16 bits A5DF1 Areas 5–4 A5DF[1:0] Number of cycles A5DF0 output disable delay time – reserved – – 0 when being read. B-VI A5WT2 Areas 5–4 wait control A5WT[2:0] Wait cycles A5WT1 A5WT0 SDRAM EPSON S1C33L03 FUNCTION PART B-VI-2-23...
Page 520 A14EC Area 14, 13 endian control A12EC Area 12, 11 endian control A10EC Area 10, 9 endian control A8EC Area 8, 7 endian control A6EC Area 6 endian control A5EC Area 5, 4 endian control EPSON B-VI-2-24 S1C33L03 FUNCTION PART...
Page 521 Because the SDRAM controller controls wait cycles internally in the IC, SWAITE must be set to "1". At cold start, SWAITE is set to "0" (disabled). At hot start, SWAITE retains its status before being initialized. B-VI SDRAM EPSON S1C33L03 FUNCTION PART B-VI-2-25...
Page 522 SDRAM. At cold start, these bits are set to "0" (For a device not SDRAM). At hot start, these bits retain their status before being initialized. EPSON B-VI-2-26 S1C33L03 FUNCTION PART...
Page 523 SDRAM. The duration of this elapsed time is defined by the number of clock cycles in SDRSRFC[3:0] (D[3:0]/0x39FFC8). SDRSRF = "0" disables the self-refresh function. B-VI At cold start, SDRSRF is set to "0" (disabled). At hot start, SDRSRF retains its status before being initialized. SDRAM EPSON S1C33L03 FUNCTION PART B-VI-2-27...
Page 524 The contents set here are applied to all of areas 7, 8, 13, and 14 that are set for SDRAM. SDRRA can be read to obtain its set value. At cold start, SDRRA is set to "0" (2K). At hot start, SDRRA retain its status before being initialized. EPSON B-VI-2-28 S1C33L03 FUNCTION PART...
Page 525 Note: When the auto-refresh command is executed, the following command may be issued 3 or 4 CPU_CLK cycles from that point regardless of the t value set in the SDRTRC register. Therefore, use SDRAMs with 75 ns or less of t EPSON S1C33L03 FUNCTION PART B-VI-2-29...
Page 526 At cold start, SDRSRFC is set to "0xF" (15). At hot start, SDRSRFC retain its status before being initialized. Note: Always set this register to 2 or more. If it is set to less than 2, the SDRAM cannot exit self-refresh mode. EPSON B-VI-2-30 S1C33L03 FUNCTION PART...
Page 527 (i.e., not in the SDRAM) to confirm that the SDRAM is in self-refresh mode. At cold start, SDRSRM is set to "1" (auto refresh mode). At hot start, SDRSRM retains its status before being initialized. B-VI SDRAM EPSON S1C33L03 FUNCTION PART B-VI-2-31...
Page 528: Programming Notes
(5) If the program accesses an area out of the address range set using the address setting register (0x39FFC2), an unintended area is accessed and the stored data may be overwritten. Therefore, do not access an area out of the set range. EPSON B-VI-2-32 S1C33L03 FUNCTION PART...
Page 529: Examples Of Sdram Controller Initialization Program
25 MHz clock in x1 speed mode ld.b [%r0],%r1 ;/////////////////////////////////////////// B-VI ;;; SDRAM timing set-up register 2 xld.w %r0,0x39FFC5 xld.w %r1,0x48 ; Trcd=1,Trsc=2,Trrd=1 SDRAM ld.b [%r0],%r1 ;/////////////////////////////////////////// ;;; SDRAM auto refresh count low-order register xld.w %r0,0x39FFC6 xld.w %r1,0xff ld.b [%r0],%r1 ;/////////////////////////////////////////// EPSON S1C33L03 FUNCTION PART B-VI-2-33...
Page 530 ; set area13&14 to SDRAM area, #SDCE0(#CE13) available ld.b [%r0],%r1 ; (32MB area available) ;/////////////////////////////////////////// (note 2) ;/////////////////////////////////////////// ;;; SDRAM address configuration register xld.w %r0,0x39FFC2 xld.w %r1,0x2a ; col 512 / row 8K / bank 4 -> 256Mb[32MB] available ld.b [%r0],%r1 ;/////////////////////////////////////////// EPSON B-VI-2-34 S1C33L03 FUNCTION PART...
Page 531: Lcd Controller Block
S1C33L03 FUNCTION PART VII LCD CONTROLLER BLOCK...
Page 533: Introduction
Pads (A/D converter) (Prescaler, 8-bit timer, 16-bit timer, Clock timer, Serial interface, Ports) C33 Analog Block C33 Peripheral Block Figure 1.1 LCD Controller Block Note: Internal ROM is not provided in the S1C33L03. B-VII Intro EPSON S1C33L03 FUNCTION PART B-VII-1-1...
Page 534 VII LCD CONTROLLER BLOCK: INTRODUCTION THIS PAGE IS BLANK. EPSON B-VII-1-2 S1C33L03 FUNCTION PART...
Page 535: Lcd Controller
• The PCLK (pixel clock) and MCLK (memory clock) for the LCD controller can be selected from among four clock frequencies derived from the BCU clock by dividing the BCU clock by 1, 2, 3, or 4. • PCLK and MCLK frequencies: Maximum of 25 MHz B-VII LCDC EPSON S1C33L03 FUNCTION PART B-VII-2-1...
Page 536 VII LCD CONTROLLER BLOCK: LCD CONTROLLER Power save • DOZE mode suitable for Epson’s self-refresh-type LCD panels • The status of the LCD controller can be checked using the power-save status bit. Other • Inverse display under software control • Software power-save mode •...
Page 537: Block Diagram
The horizontal and vertical display timing is controlled in accordance with the register settings. LCD-panel interface Display on the LCD panel is controlled through frame rate modulation, output-data pattern generation, and the like. B-VII LCDC EPSON S1C33L03 FUNCTION PART B-VII-2-3...
Page 538: I/O Pins Of The Lcd Controller
LCD panel FPDAT[7:0] D[7:0] FPDAT[3:0] D[3:0] FPSHIFT FPSHIFT FPSHIFT FPSHIFT FPFRAME FPFRAME FPFRAME FPFRAME FPLINE FPLINE FPLINE FPLINE DRDY DRDY LCDPWR LCDPWR 8-bit passive LCD panel 4-bit passive LCD panel Figure 2.2 Typical LCD-Panel Connections EPSON B-VII-2-4 S1C33L03 FUNCTION PART...
Page 539: System Settings
LCD controller cannot update the display. To prevent this problem, the LCD controller can disable DMA requests (#DMAREQx) or bus release requests (#BUSREQ) from outside the chip while it remains enabled (LCDCEN (D5)/LCDC mode register 2 = "1"). B-VII LCDC EPSON S1C33L03 FUNCTION PART B-VII-2-5...
Page 540: Lcd Controller Setting Procedure
4 wait states inserted (1st and 2nd writes in a sequence), and blue data should be written with 7 wait states inserted (last write in a sequence). be inserted A6WT[2:0] (D[A:8])/areas 6–4 setup register (0x4812A) to set the number of wait states to when area 6 is accessed. EPSON B-VII-2-6 S1C33L03 FUNCTION PART...
Page 541: Clock
LCDC clock (PCLK, MCLK) CPU_CLK 1/1 or 1/2 Figure 2.3 LCDC Clocks Table 2.3 Selection of LCDC Clocks LCLKSEL2 LCLKSEL1 LCLKSEL0 LCDC clock Turned off Turned off Turned off Reserved (not allowed) BCU_CLK BCU_CLK/2 BCU_CLK/3 BCU_CLK/4 B-VII LCDC EPSON S1C33L03 FUNCTION PART B-VII-2-7...
Page 542: Setting The Lcd Panel
Set the value shown below in LDVSIZE[9:0] (D[9:0])/vertical panel size register (0x39FFE6, 0x39FFE5). LDVSIZE[9:0] = Vertical resolution (number of lines) - 1 For example, if the LCD panel has a vertical resolution of 240 lines, set 239 (= 0xEF) in LDVSIZE. EPSON B-VII-2-8 S1C33L03 FUNCTION PART...
Page 543: Display Modes
P0 P1 P2 P3 P4 P5 P6 P7 Byte 1 A4 B4 A5 B5 A6 B6 A7 B7 Byte 0 A0 B0 A1 B1 A2 B2 A3 B3 Pn = (An, Bn) Figure 2.5 Data Format in 2-bpp Mode B-VII LCDC EPSON S1C33L03 FUNCTION PART B-VII-2-9...
Page 544 P0 P1 P2 P3 P4 P5 P6 P7 Byte 2 R2 R2 G2 Byte 1 Byte 0 Pn = (Rn , Rn , Rn , Gn , Gn , Gn , Bn , Bn Figure 2.7 Data Format in 8-bpp Mode EPSON B-VII-2-10 S1C33L03 FUNCTION PART...
Page 545: Look-Up Tables
LCD panel. The LCD controller can control reversal of the display. This control is exercised on the output of the look-up tables. B-VII LCDC EPSON S1C33L03 FUNCTION PART B-VII-2-11...
Page 546 Figure 2.10 Look-up Table in 2-bpp (4-Gray-Level) Mode Table 2.7 shows an example of the basic data setting. Table 2.7 Example of Look-up-Table Settings in 2-bpp (4-Gray-Level) Mode Index R look-up table G look-up table B look-up table 4–15 EPSON B-VII-2-12 S1C33L03 FUNCTION PART...
Page 547 Figure 2.11 Look-up Table in 4-bpp (16-Gray-Level) Mode Table 2.8 shows an example of the basic data setting. Table 2.8 Example of Look-up-Table Settings in 4-bpp (16-Gray-Level) Mode Index R look-up table G look-up table B look-up table B-VII LCDC EPSON S1C33L03 FUNCTION PART B-VII-2-13...
Page 548 Figure 2.12 Look-up Table in 1-bpp (2-Color) Mode Table 2.9 shows an example of the basic data setting. Table 2.9 Example of Look-up-Table Settings in 1-bpp (2-Color) Mode Index R look-up table G look-up table B look-up table 2–15 EPSON B-VII-2-14 S1C33L03 FUNCTION PART...
Page 549 Figure 2.13 Look-up Table in 2-bpp (4-Color) Mode Table 2.10 shows an example of the basic data setting. Table 2.10 Example of Look-up-Table Settings in 2-bpp (4-Color) Mode Index R look-up table G look-up table B look-up table 4–15 B-VII LCDC EPSON S1C33L03 FUNCTION PART B-VII-2-15...
Page 550 Figure 2.14 Look-up Table in 4-bpp (16-Color) Mode Table 2.11 shows an example of the basic data setting. Table 2.11 Example of Look-up-Table Settings in 4-bpp (16-Color) Mode (VGA 16-Color-Mode Compatible) Index R look-up table G look-up table B look-up table EPSON B-VII-2-16 S1C33L03 FUNCTION PART...
Page 551 111 000 00 Bright red 100 000 10 Dark magenta 111 000 11 Bright magenta 100 100 00 Dark yellow 111 111 00 Bright yellow B-VII 100 100 10 Gray 111 111 11 White LCDC EPSON S1C33L03 FUNCTION PART B-VII-2-17...
Page 552 0x0 to the red and blue look-up tables. • If the look-up-table address register (0x39FFF5) is set newly again during writing to any look-up table, the red look-up table is always selected. EPSON B-VII-2-18 S1C33L03 FUNCTION PART...
Page 553: Frame Rates
From the above parameters, we obtain the number of PCLK clock cycles required for the display of one frame, as determined by (HDP + HNDP) (VDP + VNDP). The frame rate is calculated by dividing the PCLK clock frequency by this value. B-VII LCDC EPSON S1C33L03 FUNCTION PART B-VII-2-19...
Page 554: Other Settings
This setup item is provided for EL panels. Whether the frame-rate modulation pattern is to be repeated every 0x40000 frames (counted by the internal frame counter) can be set using FRMRPT (D2)/LCDC mode register 1 (0x39FFE2). FRMRPT = "1": FRM pattern repeated FRMRPT = "0": FRM pattern not repeated (default) EPSON B-VII-2-20 S1C33L03 FUNCTION PART...
Page 555: Display Control
8. The LCD controller starts a power-up sequence and the power to the LCD panel turns on a one-frame period later. 9. Set the look-up tables (refer to "Look-up Tables"). Thus, the above is the basic operation for starting up the display. B-VII LCDC EPSON S1C33L03 FUNCTION PART B-VII-2-21...
Page 556: Reading/Writing Display Data
When area 7 is used, for example, the start address of the display memory is 0x0, rather than 0x400000. Be aware that the address set here is a halfword address (byte address for portrait mode; described later). EPSON B-VII-2-22 S1C33L03 FUNCTION PART...
Page 557: Split-Screen Display
Because the view port than that required to achieve the resolution size is equal to that required to achieve the B-VII resolution of the LCD panel, the values set in the horizontal panel size register (0x39FFE4) and vertical panel size register (0x39FFE6, 0x39FFE5) are applied directly as they are. LCDC EPSON S1C33L03 FUNCTION PART B-VII-2-23...
Page 558 16 / BPP Offset (HW) (HW) BPP = 1, 2, 4, or 8 (bpp) Figure 2.19 Virtual Screen and Split-Screen Display Note: In portrait mode (described later), the memory address offset register (0x39FFF1) has no effect. EPSON B-VII-2-24 S1C33L03 FUNCTION PART...
Page 559: Inverting And Blanking The Display
3. If the LCD panel was split into two screens in landscape mode, reset the S1VSIZE[9:0] (D[9:0])/screen 1 vertical size register (0x39FFF3, 0x39FFF2) by setting a new value above the vertical resolution of the B-VII LCD panel. In portrait mode, the LCD panel cannot be split for display on screen 2. LCDC EPSON S1C33L03 FUNCTION PART B-VII-2-25...
Page 560 Always make sure the screen is scrolled two lines at a time. To this end, increment or decrement the screen 1 start address register by an amount equal to twice the number of bytes set in the line byte count register (0x39FFFC) in step 5. EPSON B-VII-2-26 S1C33L03 FUNCTION PART...
Page 561 In the example discussed here, because pixel A is at 0x0, the offset from A to B is 240 - 1 = 239 (0xEF) bytes. For 4-bpp mode, this is 240/2 - 1 = 119 (0x77) bytes. B-VII LCDC EPSON S1C33L03 FUNCTION PART B-VII-2-27...
Page 562 A greater amount of power than in default consumption power. portrait mode is consumed. Vertical scroll Can be scrolled two lines at a time. Can be scrolled one line at a time. Display Standard performance. Higher performance than default portrait performance mode. EPSON B-VII-2-28 S1C33L03 FUNCTION PART...
Page 563: Power Save
Doze mode Doze mode is a power-save mode designed for use with Epson’s MLS LCD drivers. When MLS LCD drivers are used, there is no need to send data constantly in order to refresh the display of the same image. The LCD controller can be set in doze mode during this period.
Page 564: Controlling The Gpio Pins
When the pins are set for output, write output data to GPIOxD. Setting the GPIOxD bit to "1" drives the GPIOx output high, and setting the GPIOxD bit to "0" drives the GPIOx output low. EPSON B-VII-2-30 S1C33L03 FUNCTION PART...
Page 565: I/O Memory Of Lcd Controller
V resolution (lines) - 1 register 1 LDVSIZE8 (high-order 2 bits) Horizontal 039FFE7 D7–5 – reserved – – – 0 when being read. B-VII non-display HNDP4 Horizontal non-display period Non-display period (pixels) period register HNDP3 HNDP2 LCDC HNDP1 HNDP0 EPSON S1C33L03 FUNCTION PART B-VII-2-31...
Page 566 Memory address offset address offset MADOFS6 register MADOFS5 MADOFS4 MADOFS3 MADOFS2 MADOFS1 MADOFS0 Screen 1 039FFF2 S1VSIZE7 Screen 1 vertical size vertical size S1VSIZE6 (low-order 8 bits) register 0 S1VSIZE5 S1VSIZE4 S1VSIZE3 S1VSIZE2 S1VSIZE1 S1VSIZE0 EPSON B-VII-2-32 S1C33L03 FUNCTION PART...
Page 567 P: 1/8, M: 1/4 P: 1/4, M: 1/2 P: 1/2, M: 1/1 P: 1/2, M: 1/1 Line byte 039FFFC PMODLBC7 Line byte count count register PMODLBC6 for portrait PMODLBC5 mode PMODLBC4 PMODLBC3 PMODLBC2 B-VII PMODLBC1 PMODLBC0 LCDC EPSON S1C33L03 FUNCTION PART B-VII-2-33...
Page 568 Mono Single 8-bit passive LCD Reserved Reserved Color Single 4-bit passive LCD Color Single 8-bit passive LCD format 1 Reserved Color Single 8-bit passive LCD format 2 At initial reset, LDDW is set to "0b00" (4-bit panel). EPSON B-VII-2-34 S1C33L03 FUNCTION PART...
Page 569 "0", the LCD controller stops operating. Note that if the power to the LCD panel turns on while LCD signals B-VII are not output correctly, the LCD panel may be degraded or damaged. At initial reset, LCDCEN is set to "0" (disabled). LCDC EPSON S1C33L03 FUNCTION PART B-VII-2-35...
Page 570 LCD controller executes a power-up sequence (for details, refer to "Controlling LCD Power Up/Down"). Doze mode can only be selected when Epson’s MLS LCD drivers are used. At initial reset, LPSAVE is set to "0b00" (power-save mode).
Page 571 If the amount of data in this FIFO decreases to (0xf - FIFOEO) words or less, the LCD controller sends a DMA request to the CPU requesting that the data be read. Set the value 8 in FIFOEO. At initial reset, FIFOEO is set to "0x0". B-VII LCDC EPSON S1C33L03 FUNCTION PART B-VII-2-37...
Page 572 The GPIO[2:0] pins are shared with the bus release pins listed below. These pins can only be used as GPIO[2:0] pins when LCDCEN (D5/0x39FFE3) = "1" and BREQEN (D2/0x39FFFD) = "0". GPIO2: #BUSGET/P31 GPIO1: #BUSACK/P35 GPIO0: #BUSREQ/P34 At initial reset, GPIOxC is set to "0" (input mode). EPSON B-VII-2-38 S1C33L03 FUNCTION PART...
Page 573 Setting PMODEN to "1" places the LCD controller in a type of portrait mode selected by PMODSEL (D6/0x39FFFB), producing a display suitable for a 90-degree-rotated LCD panel. Setting PMODEN to "0" selects normal landscape mode. At initial reset, PMODEN is set to "0" (landscape mode). B-VII LCDC EPSON S1C33L03 FUNCTION PART B-VII-2-39...
Page 574 SDRAM is used. The number of wait cycles set here is inserted when the LCD controller accesses the display memory. It does not affect display-memory access by the CPU. In that case, the number of wait cycles set for the BCU is inserted. At initial reset, VRAMWT is set to "0x0". EPSON B-VII-2-40 S1C33L03 FUNCTION PART...
Page 575 "0" causes it to be accessed in little endian format. Set the same value here as set in A6EC (D1/0x48132) for area 6. At initial reset, LCDCEC is set to "0" (little endian). B-VII LCDC EPSON S1C33L03 FUNCTION PART B-VII-2-41...
Page 576: Programming Notes
When the target program stops execution by a break factor during debugging with the ICD33, the LCD display goes off until the program resumes execution. Therefore, do not use the ICD33 for debugging a target system, which uses an EPSON MLS driver for driving the LCD panel.
Page 577: Examples Of Lcd Controller Setting Program
; set segment 32 xld.w %r2, 0x01 ld.b [%r1], %r2 B-VII xld.w %r1, 0x39ffe5 ; set common xld.w %r2, 0x01 ld.b [%r1], %r2 LCDC xld.w %r1, 0x39ffe8 ; set Horizontal Non-display period xld.w %r2, 0x01 EPSON S1C33L03 FUNCTION PART B-VII-2-43...
Page 578 %r2, 0x23 ld.b [%r1], %r2 ;****************************************************** Initialize the LUT ;****************************************************** xld.w %r1, 0x39fff5 ; set lut address xld.w %r2, 0x39fff7 xld.w %r3, 0x00 ld.b [%r1], %r3 ld.b [%r2], %r3 ld.b [%r2], %r3 ld.b [%r2], %r3 EPSON B-VII-2-44 S1C33L03 FUNCTION PART...
Page 579: Appendix I/O Map
S1C33L03 FUNCTION PART Appendix I/O MAP...
Page 581 Initial values that are set at initial reset. (However, the registers for the bus and input/output ports are not initialized at hot start.) Not initialized at initial reset. –: Not set in the circuit. B-ap EPSON S1C33L03 FUNCTION PART B-APPENDIX-1...
Page 582 1 On 0 Off P8TS02 8-bit timer 0 P8TS0[2:0] Division ratio : selected by P8TS01 clock division ratio selection /256 Prescaler clock select P8TS00 /128 register (0x40181) 8-bit timer 0 can generate the DRAM refresh clock. EPSON B-APPENDIX-2 S1C33L03 FUNCTION PART...
Page 583 0040154 D7–6 – reserved – – – 0 when being read. second TCMD5 Clock timer second counter data 0 to 59 seconds register TCMD4 TCMD5 = MSB TCMD3 TCMD0 = LSB TCMD2 TCMD1 TCMD0 B-ap EPSON S1C33L03 FUNCTION PART B-APPENDIX-3...
Page 584 D7–5 – reserved – – – 0 when being read. TCCN4 Clock timer day comparison data 0 to 31 days Compared with comparison TCCN3 TCCN4 = MSB TCND[4:0]. register TCCN2 TCCN0 = LSB TCCN1 TCCN0 EPSON B-APPENDIX-4 S1C33L03 FUNCTION PART...
Page 585 RLD24 RLD23 RLD22 RLD21 RLD20 8-bit timer 2 004016A PTD27 8-bit timer 2 counter data 0 to 255 counter data PTD26 PTD27 = MSB register PTD25 PTD20 = LSB PTD24 PTD23 PTD22 PTD21 PTD20 B-ap EPSON S1C33L03 FUNCTION PART B-APPENDIX-5...
Page 586 RLD50 = LSB RLD54 RLD53 RLD52 RLD51 RLD50 8-bit timer 5 004017A PTD57 8-bit timer 5 counter data 0 to 255 counter data PTD56 PTD57 = MSB register PTD55 PTD50 = LSB PTD54 PTD53 PTD52 PTD51 PTD50 EPSON B-APPENDIX-6 S1C33L03 FUNCTION PART...
Page 587 Watchdog 0040171 D7–2 – – – – – 0 when being read. timer enable Watchdog timer enable 1 NMI enabled 0 NMI disabled register – – – – – 0 when being read. B-ap EPSON S1C33L03 FUNCTION PART B-APPENDIX-7...
Page 588 Writing 10010110 (0x96) protect register CLGP6 removes the write protection of CLGP5 the power control register CLGP4 (0x40180) and the clock option CLGP3 register (0x40190). CLGP2 Writing another value set the CLGP1 write protection. CLGP0 EPSON B-APPENDIX-8 S1C33L03 FUNCTION PART...
Page 589 1 Inverted 0 Direct Valid only in IRRL0 Ch.0 IrDA I/F input logic inversion 1 Inverted 0 Direct asynchronous mode. IRMD01 Ch.0 interface mode selection IRMD0[1:0] I/F mode IRMD00 reserved IrDA 1.0 reserved General I/F B-ap EPSON S1C33L03 FUNCTION PART B-APPENDIX-9...
Page 590 OER2 Ch.2 overrun error flag 1 Error 0 Normal Reset by writing 0. TDBE2 Ch.2 transmit data buffer empty 1 Empty 0 Buffer full RDBF2 Ch.2 receive data buffer full 1 Buffer full 0 Empty EPSON B-APPENDIX-10 S1C33L03 FUNCTION PART...
Page 591 1 Inverted 0 Direct Valid only in IRRL3 Ch.3 IrDA I/F input logic inversion 1 Inverted 0 Direct asynchronous mode. IRMD31 Ch.3 interface mode selection IRMD3[1:0] I/F mode IRMD30 reserved IrDA 1.0 reserved General I/F B-ap EPSON S1C33L03 FUNCTION PART B-APPENDIX-11...
Page 592 Reset by writing 0. A/D sampling 0040245 D7–2 – – – – – 0 when being read. register Input signal sampling time setup ST[1:0] Sampring time Use with 9 clocks. 9 clocks 7 clocks 5 clocks 3 clocks EPSON B-APPENDIX-12 S1C33L03 FUNCTION PART...
Page 593 P16T52 16-bit timer 5 interrupt level 0 to 7 priority register P16T51 P16T50 – reserved – – – 0 when being read. P16T42 16-bit timer 4 interrupt level 0 to 7 P16T41 P16T40 B-ap EPSON S1C33L03 FUNCTION PART B-APPENDIX-13...
Page 594 0 when being read. interrupt PP7L2 Port input 7 interrupt level 0 to 7 priority register PP7L1 PP7L0 – reserved – – – 0 when being read. PP6L2 Port input 6 interrupt level 0 to 7 PP6L1 PP6L0 EPSON B-APPENDIX-14 S1C33L03 FUNCTION PART...
Page 595 – – 0 when being read. clock timer, Port input 7 1 Enabled 0 Disabled A/D interrupt Port input 6 enable register Port input 5 Port input 4 ECTM Clock timer EADE A/D converter B-ap EPSON S1C33L03 FUNCTION PART B-APPENDIX-15...
Page 596 0 when being read. clock timer, A/D Port input 7 1 Factor is 0 No factor is interrupt factor Port input 6 generated generated flag register Port input 5 Port input 4 FCTM Clock timer FADE A/D converter EPSON B-APPENDIX-16 S1C33L03 FUNCTION PART...
Page 597 Port input 4 register – reserved – – – 0 when being read. DEADE A/D converter 1 IDMA 0 IDMA DESTX1 SIF Ch.1 transmit buffer empty enabled disabled DESRX1 SIF Ch.1 receive buffer full B-ap EPSON S1C33L03 FUNCTION PART B-APPENDIX-17...
Page 598 IDMA enable register set method 1 Set only 0 RD/WR register selection IDMAONLY IDMA request register set method 1 Set only 0 RD/WR selection RSTONLY Interrupt factor flag reset method 1 Reset only 0 RD/WR selection EPSON B-APPENDIX-18 S1C33L03 FUNCTION PART...
Page 599 K65 input port data – K64D K64 input port data – K63D K63 input port data – K62D K62 input port data – K61D K61 input port data – K60D K60 input port data – B-ap EPSON S1C33L03 FUNCTION PART B-APPENDIX-19...
Page 600 0 TM16 Ch.4 RXD Full comp.B SIO2TS1 SIO Ch.2 transmit buffer empty 1 SIO Ch.2 0 TM16 Ch.5 TXD Emp. comp.A SIO2RS1 SIO Ch.2 receive buffer full 1 SIO Ch.2 0 TM16 Ch.5 RXD Full comp.B EPSON B-APPENDIX-20 S1C33L03 FUNCTION PART...
Page 601 1 High 0 Low P15D P15 I/O port data P14D P14 I/O port data P13D P13 I/O port data P12D P12 I/O port data P11D P11 I/O port data P10D P10 I/O port data B-ap EPSON S1C33L03 FUNCTION PART B-APPENDIX-21...
Page 602 P34 I/O control indicates the values IOC33 P33 I/O control of the I/O control IOC32 P32 I/O control signals of the ports IOC31 P31 I/O control when it is read. (See IOC30 P30 I/O control detailed explanation.) EPSON B-APPENDIX-22 S1C33L03 FUNCTION PART...
Page 603 0 16 bits A14DF1 Areas 14–13 A14DF[1:0] Number of cycles A14DF0 output disable delay time – reserved – – – 0 when being read. A14WT2 Areas 14–13 wait control A14WT[2:0] Wait cycles A14WT1 A14WT0 B-ap EPSON S1C33L03 FUNCTION PART B-APPENDIX-23...
Page 604 1 8 bits 0 16 bits A8DF1 Areas 8–7 A8DF[1:0] Number of cycles A8DF0 output disable delay time – reserved – – – 0 when being read. A8WT2 Areas 8–7 wait control A8WT[2:0] Wait cycles A8WT1 A8WT0 EPSON B-APPENDIX-24 S1C33L03 FUNCTION PART...
Page 605 Writing 1 not allowed. SBUSST External interface method selection 1 #BSL 0 A0 SEMAS External bus master setup 1 Existing 0 Nonexistent SEPD External power-down control 1 Enabled 0 Disabled SWAITE #WAIT enable 1 Enabled 0 Disabled B-ap EPSON S1C33L03 FUNCTION PART B-APPENDIX-25...
Page 606 Fixed at 0 0 when being read. order register (HW) TTBR32 Writing 1 not allowed. TTBR31 TTBR30 TTBR2B Trap table base address [27:16] 0x0C0 TTBR2A TTBR29 TTBR28 TTBR27 TTBR26 TTBR25 TTBR24 TTBR23 TTBR22 TTBR21 TTBR20 EPSON B-APPENDIX-26 S1C33L03 FUNCTION PART...
Page 607 A1X1MD Area 1 access-speed 1 2 cycles 0 4 cycles x2 speed mode only – reserved – – 0 when being read. BCLKSEL1 BCLK output clock selection BCLKSEL[1:0] BCLK BCLKSEL0 PLL_CLK OSC3_CLK BCU_CLK CPU_CLK B-ap EPSON S1C33L03 FUNCTION PART B-APPENDIX-27...
Page 608 1 External clock 0 Internal clock PTM0 16-bit timer 0 clock output control 1 On 0 Off PRESET0 16-bit timer 0 reset 1 Reset 0 Invalid 0 when being read. PRUN0 16-bit timer 0 Run/Stop control 1 Run 0 Stop EPSON B-APPENDIX-28 S1C33L03 FUNCTION PART...
Page 609 PTM1 16-bit timer 1 clock output control 1 On 0 Off PRESET1 16-bit timer 1 reset 1 Reset 0 Invalid 0 when being read. PRUN1 16-bit timer 1 Run/Stop control 1 Run 0 Stop B-ap EPSON S1C33L03 FUNCTION PART B-APPENDIX-29...
Page 610 1 External clock 0 Internal clock PTM2 16-bit timer 2 clock output control 1 On 0 Off PRESET2 16-bit timer 2 reset 1 Reset 0 Invalid 0 when being read. PRUN2 16-bit timer 2 Run/Stop control 1 Run 0 Stop EPSON B-APPENDIX-30 S1C33L03 FUNCTION PART...
Page 611 PTM3 16-bit timer 3 clock output control 1 On 0 Off PRESET3 16-bit timer 3 reset 1 Reset 0 Invalid 0 when being read. PRUN3 16-bit timer 3 Run/Stop control 1 Run 0 Stop B-ap EPSON S1C33L03 FUNCTION PART B-APPENDIX-31...
Page 612 1 External clock 0 Internal clock PTM4 16-bit timer 4 clock output control 1 On 0 Off PRESET4 16-bit timer 4 reset 1 Reset 0 Invalid 0 when being read. PRUN4 16-bit timer 4 Run/Stop control 1 Run 0 Stop EPSON B-APPENDIX-32 S1C33L03 FUNCTION PART...
Page 613 PTM5 16-bit timer 5 clock output control 1 On 0 Off PRESET5 16-bit timer 5 reset 1 Reset 0 Invalid 0 when being read. PRUN5 16-bit timer 5 Run/Stop control 1 Run 0 Stop B-ap EPSON S1C33L03 FUNCTION PART B-APPENDIX-33...
Page 614 0048204 DSTART IDMA start 1 IDMA start 0 Stop register D6–0 DCHN IDMA channel number 0 to 127 IDMA enable 0048205 D7–1 – reserved – – – register IDMAEN IDMA enable 1 Enabled 0 Disabled EPSON B-APPENDIX-34 S1C33L03 FUNCTION PART...
Page 615 Inc.(init) Dec.(no init) Note: Fixed D) Dual address S0ADRH11 D) Ch.0 source address[27:16] mode S0ADRH10 S) Ch.0 memory address[27:16] S) Single S0ADRH9 address S0ADRH8 mode S0ADRH7 S0ADRH6 S0ADRH5 S0ADRH4 S0ADRH3 S0ADRH2 S0ADRH1 S0ADRH0 B-ap EPSON S1C33L03 FUNCTION PART B-APPENDIX-35...
Page 616 DF–1 – reserved – – – Undefined in read. DMA Ch.0 (HW) trigger flag HS0_TF Ch.0 trigger flag clear (writing) 1 Clear 0 No operation register Ch.0 trigger flag status (reading) 1 Set 0 Cleared EPSON B-APPENDIX-36 S1C33L03 FUNCTION PART...
Page 617 Inc.(init) Dec.(no init) Note: Fixed D) Dual address S1ADRH11 D) Ch.1 source address[27:16] mode S1ADRH10 S) Ch.1 memory address[27:16] S) Single S1ADRH9 address S1ADRH8 mode S1ADRH7 S1ADRH6 S1ADRH5 S1ADRH4 S1ADRH3 S1ADRH2 S1ADRH1 S1ADRH0 B-ap EPSON S1C33L03 FUNCTION PART B-APPENDIX-37...
Page 618 DF–1 – reserved – – – Undefined in read. DMA Ch.1 (HW) trigger flag HS1_TF Ch.1 trigger flag clear (writing) 1 Clear 0 No operation register Ch.1 trigger flag status (reading) 1 Set 0 Cleared EPSON B-APPENDIX-38 S1C33L03 FUNCTION PART...
Page 619 Inc.(init) Dec.(no init) Note: Fixed D) Dual address S2ADRH11 D) Ch.2 source address[27:16] mode S2ADRH10 S) Ch.2 memory address[27:16] S) Single S2ADRH9 address S2ADRH8 mode S2ADRH7 S2ADRH6 S2ADRH5 S2ADRH4 S2ADRH3 S2ADRH2 S2ADRH1 S2ADRH0 B-ap EPSON S1C33L03 FUNCTION PART B-APPENDIX-39...
Page 620 DF–1 – reserved – – – Undefined in read. DMA Ch.2 (HW) trigger flag HS2_TF Ch.2 trigger flag clear (writing) 1 Clear 0 No operation register Ch.2 trigger flag status (reading) 1 Set 0 Cleared EPSON B-APPENDIX-40 S1C33L03 FUNCTION PART...
Page 621 Inc.(init) Dec.(no init) Note: Fixed D) Dual address S3ADRH11 D) Ch.3 source address[27:16] mode S3ADRH10 S) Ch.3 memory address[27:16] S) Single S3ADRH9 address S3ADRH8 mode S3ADRH7 S3ADRH6 S3ADRH5 S3ADRH4 S3ADRH3 S3ADRH2 S3ADRH1 S3ADRH0 B-ap EPSON S1C33L03 FUNCTION PART B-APPENDIX-41...
Page 622 DF–1 – reserved – – – Undefined in read. DMA Ch.3 (HW) trigger flag HS3_TF Ch.3 trigger flag clear (writing) 1 Clear 0 No operation register Ch.3 trigger flag status (reading) 1 Set 0 Cleared EPSON B-APPENDIX-42 S1C33L03 FUNCTION PART...
Page 623 SDRAM t spec SDRTRAS[2:0] Number of clocks timing set-up SDRTRAS1 register 1 SDRTRAS0 D4–3 SDRTRP1 SDRAM t spec SDRTRP[1:0] Number of clocks SDRTRP0 D2–0 SDRTRC2 SDRAM t spec SDRTRC[2:0] Number of clocks SDRTRC1 SDRTRC0 B-ap EPSON S1C33L03 FUNCTION PART B-APPENDIX-43...
Page 624 039FFCA SDRMRS SDRAM mode register set flag 1 Not finished 0 Done status register SDRSRM SDRAM current refresh mode 1 Auto refresh 0 Self refresh D5–0 – reserved – – – 0 when being read. EPSON B-APPENDIX-44 S1C33L03 FUNCTION PART...
Page 625 V resolution (lines) - 1 register 1 LDVSIZE8 (high-order 2 bits) Horizontal 039FFE7 D7–5 – reserved – – – 0 when being read. non-display HNDP4 Horizontal non-display period Non-display period (pixels) period register HNDP3 HNDP2 HNDP1 HNDP0 B-ap EPSON S1C33L03 FUNCTION PART B-APPENDIX-45...
Page 626 Memory address offset address offset MADOFS6 register MADOFS5 MADOFS4 MADOFS3 MADOFS2 MADOFS1 MADOFS0 Screen 1 039FFF2 S1VSIZE7 Screen 1 vertical size vertical size S1VSIZE6 (low-order 8 bits) register 0 S1VSIZE5 S1VSIZE4 S1VSIZE3 S1VSIZE2 S1VSIZE1 S1VSIZE0 EPSON B-APPENDIX-46 S1C33L03 FUNCTION PART...
Page 627 P: 1/8, M: 1/4 P: 1/4, M: 1/2 P: 1/2, M: 1/1 P: 1/2, M: 1/1 Line byte 039FFFC PMODLBC7 Line byte count count register PMODLBC6 for portrait PMODLBC5 mode PMODLBC4 PMODLBC3 PMODLBC2 PMODLBC1 PMODLBC0 B-ap EPSON S1C33L03 FUNCTION PART B-APPENDIX-47...
Page 628 (number of wait cycles for SRAM) VRAMWT0 EDMAEN External DMA enable 1 Enabled 0 Disabled BREQEN External bus-request enable 1 Enabled 0 Disabled LCDCST A0/BSL select 1 BSL 0 A0 LCDCEC Big/little endian select 1 Big endian 0 Little endian EPSON B-APPENDIX-48 S1C33L03 FUNCTION PART...
Page 629 Central Phone: +852-2585-4600 Fax: +852-2827-4346 101 Virginia Street, Suite 290 Telex: 65542 EPSCO HX Crystal Lake, IL 60014, U.S.A. EPSON TAIWAN TECHNOLOGY & TRADING LTD. Phone: +1-815-455-7630 Fax: +1-815-455-7633 14F, No. 7, Song Ren Road, Taipei 110 Northeast Phone: 02-8786-6688...
Page 630 In pursuit of “Saving” Technology, Epson electronic devices. Our lineup of semiconductors, displays and quartz devices assists in creating the products of our customers’ dreams. Epson IS energy savings.
Page 631 S1C33L03 Technical Manual ELECTRONIC DEVICES MARKETING DIVISION EPSON Electronic Devices Website http://www.epsondevice.com Issue April, 2003 Printed in Japan...

Epson CMOS 32-Bit Single Chip Microcomputer S1C33L03 Technical Manual

Outline

Power Supply

Internal Memory

Peripheral Circuits

Power-Down Control

Basic External Wiring Diagram

Precautions on Mounting

Electrical Characteristics

Package

Pad Layout

Appendix A <Reference> External Device Interface Timings

Appendix B Pin Characteristics

Ioutline

Introduction

Block Diagram

List of Pins

Core Block

Introduction

Cpu and Operating Mode

Initial Reset

BCU (Bus Control Unit)

ITC (Interrupt Controller)

CLG (Clock Generator)

DBG (Debug Unit)

Peripheral Block

Introduction

Prescaler

8-Bit Programmable Timers

16-Bit Programmable Timers

Watchdog Timer

Low-Speed (Osc1) Oscillation Circuit

Clock Timer

Serial Interface

Input/Output Ports

Analog Block

Introduction

A/D Converter

Dma Block

Introduction

HSDMA (High-Speed DMA)

IDMA (Intelligent DMA)

Sdram Controller Block

Introduction

Sdram Interface

Lcd Controller Block

Introduction

Lcd Controller

Quick Links

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Summary of Contents for Epson CMOS 32-Bit Single Chip Microcomputer S1C33L03