Epson S1C6200A Core Cpu Manual
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Epson S1C6200A Core Cpu Manual

Epson S1C6200A Core Cpu Manual

Epson cmos 4-nit single chip microcomputer core cpu manual
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MF297-07
CMOS 4 - BIT SINGLE CHIP MICROCOMPUTER
S1C6200/6200A
Core CPU Manual

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  • Page 1 MF297-07 CMOS 4 - BIT SINGLE CHIP MICROCOMPUTER S1C6200/6200A Core CPU Manual...
  • Page 2 No part of this material may be reproduced or duplicated in any form or by any means without the written permission of Seiko Epson. Seiko Epson reserves the right to make changes to this material without notice. Seiko Epson does not assume any...
  • Page 3 The information of the product number change Starting April 1, 2001, the product number will be changed as listed below. To order from April 1, 2001 please use the new product number. For further information, please contact Epson sales representative.

  • Page 5: Table Of Contents

    S1C6200/6200A Core CPU Manual ____________________________________________________ 1 ESCRIPTION 1.1 System Features ... 1 1.2 Instruction Set Features ... 1 1.3 Differences between S1C6200 and S1C6200A ... 1 EMORY AND PERATIONS 2.1 Program Memory (ROM) ... 3 2.1.1 Program counter block ... 4 2.1.2 Flags ...

  • Page 7: S1C6200/6200A Core Cpu Manual

    • Interrupt circuit – Interrupt timing (refer to Section 2.5.3, "Operation during interrupt generation".) – Writing to interrupt mask registers and reading of interrupt flags (refer to Appendix A, "S1C6200A (Advanced S1C6200) Core CPU".) S1C6200/6200A CORE CPU MANUAL EPSON 1 DESCRIPTION...
  • Page 8 Instruction Register (12) Program Memory (8,192 12-bit words max.) 4-bit address bus RP (4) YHL (8) XHL (8) Stack Pointer (8) 12-bit data bus Fig. 1.1 Block diagram EPSON XP (4) YP (4) Oscillator Interrupt Timing Controller Generator A (4) B (4)

  • Page 9: Memory And Operations

    Step 0 Step 1 (within bank) Step 254 Step 255 (between banks) Program or data code area Fig. 2.1.1 Program memory configuration EPSON 2 MEMORY AND OPERATIONS Bank 1 Page 15 Bank 1 Bank 1 Page 14 Step 0 Step 1...

  • Page 10: Program Counter Block

    (8,192 12-bit words max.) Address decoder Program counter block Fig. 2.1.1.1 Program counter configuration Table 2.1.2.1 Flags Flag Menus 1: Enabled 0: Disabled 1: Decimal 0: Hexadecimal 1: Set 0: Ignored 1: Set 0: Ignored EPSON Size Size S1C6200/6200A CORE CPU MANUAL...

  • Page 11: Jump Instructions

    Page 1 Bank 1 Page 0 Step 0 Step 1 Step 254 Step 255 Fig. 2.1.4.1 The PSET and jump instructions EPSON 2 MEMORY AND OPERATIONS Jump can go between banks Bank 1 Page 15 Bank 1 Page 14 Step 0...

  • Page 12: Pset Instruction

    The data set by PSET is canceled, and the program jumps to bank 0, page 1, step 9. Bank 0 Page 0 EEE... Bank 0 Page 2 PSET Not effect on destination CALZ of CALZ Fig. 2.1.7.1 The use of the CALZ instruction EPSON S1C6200/6200A CORE CPU MANUAL...

  • Page 13: Ret And Rets Instructions

    Step 255 Bank 0 Page 0 Program memory PSET CALL Bank 0 Page 10 Program memory DDD... RETS EPSON 2 MEMORY AND OPERATIONS Bank 1 Page 15 Bank 1 Bank 1 Page 14 Step 0 Step 1 CALL Bank 1...

  • Page 14: Data Memory

    Fig. 2.2.1 Data memory configuration Register/Pointer Mnemonic Index Register X Index Register Y Stack Pointer Register Fig. 2.2.1.1 The configuration of the index register IX EPSON XHL or YHL (within page) Memory or I/O Register area Size (bits) S1C6200/6200A CORE CPU MANUAL...
  • Page 15 As the register area can also be indirectly accessed M(n) – 1 using IX, IY or SP, the stack area should not grow to address 000H to 00FH when RP is used. EPSON 2 MEMORY AND OPERATIONS Table 2.2.1.2 Stack usage Instruction...

  • Page 16: Alu (Arithmetic Logic Unit) And Registers

    D = 1 : Result of Actual D = 0 : Result of decimal operation result hexadecimal operation ALU output EPSON X: Don't care. Subtraction D = 1 : Result of decimal operation ALU output ALU output S1C6200/6200A CORE CPU MANUAL...

  • Page 17: A And B Registers

    HALT or SLP, otherwise they will hang waiting for an interrupt. S1C6200/6200A CORE CPU MANUAL Execute Fetch State State State State Execute State State State State Fig. 2.4.1 Instruction execution timing EPSON 2 MEMORY AND OPERATIONS Execute State State State State...

  • Page 18: Interrupts

    HALT or SLP. <Differences between S1C6200 and S1C6200A> In the S1C6200 and the S1C6200A, the time it takes to complete interrupt processing by hardware after the Core CPU receives the interrupt request is different as follows: Table 2.5.3.1 Required interrupt processing time...
  • Page 19 S1C6200 Clock Status Instruction 5-clock Instrruction S1C6200A Clock Status Instruction 5-clock Instrruction Status: Fetch S1C6200/6200A System clock CPU clock Status Instruction 5-clock Instrruction Status: Fetch S1C6200/6200A CORE CPU MANUAL 12-clock Instrruction Interrupt Interrupt processing: 12-clock instruction 7-clock instruction 5-clock instruction...
  • Page 20 System clock CPU clock Status Instruction 5-clock Instrruction Status: Fetch S1C6200 Clock Status Instruction PSET Interrupt processing: S1C6200A Clock Status Instruction PSET Status: Fetch SLEEP Interrupt Interrupt processing: 14 to 15 clock cycles Execute Note: (*1) INT1 and INT2 are dummy instructions...

  • Page 21: Initial Reset

    Interrupt Flag Decimal Flag Zero Flag Carry Flag <Difference between S1C6200 and S1C6200A> There is a difference in the setting value of the D (decimal) flag at initial reset between the S1C6200 and the S1C6200A. D (decimal) flag setting When using the model loaded with the S1C6200 Core CPU, set or reset the D flag in the user's initial routine before using an arithmetic instruction.

  • Page 22: Instruction Set

    7. Arithmetic and logical operation b. Index in alphabetical order The instructions are arranged in alphabetical order. Page number references are provided. c. Index by operation code The instructions are arranged in numerical order by operation code. EPSON S1C6200/6200A CORE CPU MANUAL...

  • Page 23: By Function

    YL XH, i XL, i YH, i YL, i S1C6200/6200A CORE CPU MANUAL Operation Code Flag Clock I D Z C EPSON 3 INSTRUCTION SET Operation p4, NPP p3~p0 NBP, PCP NPP, PCS s7~s0 NBP, PCP NPP, PCS s7~s0 if C=1...
  • Page 24 LBPX MX, e Flag F, i operation F, i instructions Stack operation instructions PUSH Operation Code Flag Clock I D Z C EPSON Operation XH-i3~i0 XL-i3~i0 YH-i3~i0 YL-i3~i0 i3~i0 M(n3~n0) M(n3~n0) M(n3~n0) M(n3~n0) M(X) i3~i0, X q, X M(Y) i3~i0, Y...
  • Page 25 MX, r ACPY MY, r SCPX MX, r SCPY MY, r S1C6200/6200A CORE CPU MANUAL Operation Code Flag Clock I D Z C EPSON 3 INSTRUCTION SET Operation M(SP), SP SP+1 M(SP), SP SP+1 M(SP), SP SP+1 r+i3~i0 r+i3~i0+C r+q+C...

  • Page 26: In Alphabetical Order

    M(SP-1) r-i3~i0 XH-i3~i0 XL-i3~i0 YH-i3~i0 YL-i3~i0 M(n3~n0) 0 (Disables Interrupt) 1 (Enables Interrupt) r i3~i0 Halt (stop clock) M(n3~n0) M(X) EPSON Operation M(X)+r+C, X M(Y)+r+C, Y XH+i3~i0+C XL+i3~i0+C YH+i3~i0+C YL+i3~i0+C PCP, M(SP-2) PCSH, M(SP-3) SP-3, PCP NPP, PCS s7~s0 PCP, M(SP-2)
  • Page 27 M(n3~n0) M(n3~n0) i3~i0 M(X) q, X M(Y) q, Y No operation (5 clock cycles) No operation (7 clock cycles) rVi3~i0 M(SP), SP EPSON 3 INSTRUCTION SET Operation M(n3~n0) M(n3~n0) e7~e4, XL e3~e0 e7~e4, YL e3~e0 i3~i0, X i3~i0, Y M(SP), SP...
  • Page 28 Flag Clock I D Z C PCSL PCSL PCSL r-i3~i0-C r-q-C M(X) M(Y) SLEEP (stop oscillation) r i3~i0 EPSON Operation p4, NPP p3~p0 SP-1, M(SP) SP-1, M(SP) SP-1, M(SP) SP-1, M(SP) SP-1, M(SP) SP-1, M(SP) SP-1, M(SP) SP-1, M(SP) 0 (Decimal Adjuster OFF)

  • Page 29: By Operation Code

    D80 to DBF r, i DC0 to DFF r, i E00 to E3F r, i S1C6200/6200A CORE CPU MANUAL Flag Clock I D Z C EPSON 3 INSTRUCTION SET Operation NBP, PCP NPP, PCS s7~s0 PCSL M(SP), PCSH M(SP+1), PCP SP+3, M(X)
  • Page 30 F50 to F5F F, i F60 to F6F F70 to F7F F80 to F8F Mn, A Operation Code Flag Clock I D Z C EPSON Operation p4, NPP p3~p0 M(X) i3~i0, X M(Y) i3~i0, Y C, d2 d3, d1 d2, d0...
  • Page 31 FF0 to FF3 SPL, r FF4 to FF7 r, SPL HALT NOP5 NOP7 S1C6200/6200A CORE CPU MANUAL Flag Clock I D Z C EPSON 3 INSTRUCTION SET Operation M(n3~n0) M(n3~n0) M(n3~n0) SP-1, M(SP) SP-1, M(SP) SP-1, M(SP) SP-1, M(SP) SP-1, M(SP)

  • Page 32: Operands

    POP F instruction. When an interrupt is generated, the I flag is automatically reset. It is not automatically set at the end of the interrupt service routine. Table 3.2.1 Values of r and q r1 or q1 r0 or q0 EPSON S1C6200/6200A CORE CPU MANUAL...

  • Page 33: Instruction Types

    3.5 Instruction Descriptions This section describes S1C6200/6200A instructions in alphabetical order. S1C6200/6200A CORE CPU MANUAL 8-bit operand 6-bit operand 5-bit operand 4-bit operand 2-bit operand Op-code EPSON 3 INSTRUCTION SET CALL LBPX MX,e etc. r, i r, i r, i etc.

  • Page 34: Acpx Mx,R Add With Carry R-Register To M(X), Increment X By

    ACPY MY,MX 0010 0001 0010 0001 0000 1110 0000 1111 1000 1011 0100 0100 0110 0110 0010 0010 EPSON F28H to F2BH 1010 0010 0100 0110 1111 0111 0100 1000 F2CH to F2FH 0010 0001 0001 0000 1011 1010 0110...
  • Page 35 S1C6200/6200A CORE CPU MANUAL to i ADC MX,3 0100 1000 1001 1001 ADC MY,A 0101 0101 0001 0001 0111 0111 1011 0001 EPSON 3 INSTRUCTION SET C40H to C7FH ADC B,7 1000 0000 A90H to A9FH ADC MX,B 0101 0001 1001 0001...
  • Page 36 Adds the carry bit and immediate data i to XL, the four low-order bits of XHL. Example: XL register C flag Z flag to i ADC XH,2 ADC XH,4 1001 1100 to i ADC XL,3 ADC XL,0EH 0000 0100 EPSON A00H to A0FH 0000 A10H to A1FH 0010 S1C6200/6200A CORE CPU MANUAL...
  • Page 37 Adds the carry bit and immediate data i to YL, the four low-order bits of YHL. Example: YL register C flag Z flag S1C6200/6200A CORE CPU MANUAL to i ADC YH,3 ADC YH,6 1010 1110 to i ADC YL,3 ADC YL,2 1010 1110 EPSON 3 INSTRUCTION SET A20H to A2FH 0100 A30H to A3FH 0000...
  • Page 38 Z flag to i ADD A,5 1010 1111 0110 0110 ADD A,MY 0010 1111 0100 0100 0111 0111 1101 1101 EPSON C00H to C3FH ADD MY,2 1111 1000 A80H to A8FH ADD MX,B 1111 0100 1011 1101 S1C6200/6200A CORE CPU MANUAL...

  • Page 39: And R,I

    S1C6200/6200A CORE CPU MANUAL to i AND A,5 0110 0100 1000 1000 AND MX,A 0100 0100 1011 1011 1010 0000 0010 0010 EPSON 3 INSTRUCTION SET C80H to CBFH AND MX,3 0100 0000 AC0H to ACFH AND B,MY 0100 0010 0000 0010...
  • Page 40 CALZ 10H 1010 0000 0010 1110 0001 0000 xxxx 1010 xxxx 0010 xxxx 1111 EPSON PCSL + 1, SP SP - 3, 400H to 4FFH CALL 10H 0110 0001 0000 0110 0011 0010 1101 PCSL + 1, SP...

  • Page 41: Cp R,I

    CP A,4 CP MX,7 0100 0100 1010 1010 0010 0010 CP A,B 1000 1000 0100 0100 0111 0111 EPSON 3 INSTRUCTION SET DC0H to DFFH CP B,2 0100 0100 1010 1010 0010 0010 F00H to F0FH CP MY,A 1000 0100 0111...

  • Page 42: Cp Xh,I

    CP XH,2 CP XH,4 0100 0100 to i ; otherwise, reset. to i ; otherwise, reset. CP XL,7 CP XL,9 1001 1001 EPSON A40H to A4FH CP XH,9 0100 0100 A50H to A5FH CP XL,0AH 1001 1001 S1C6200/6200A CORE CPU MANUAL...

  • Page 43: Cp Yh,I

    CP YH,0AH CP YH,3 1010 1010 to i ; otherwise, reset. to i ; otherwise, reset. CP YL,5 CP YL,1 0100 0100 EPSON 3 INSTRUCTION SET A60H to A6FH CP YH,0FH 1010 1010 A70H to A7FH CP YL,4 0100 0100...
  • Page 44 Z flag to n ) - 1 DEC M0 DEC M2 1001 1000 0000 0000 0001 0001 DEC SP 1011 0001 1011 0000 EPSON F70H to F7FH DEC M0FH 1000 1000 1111 1111 0001 0000 FCBH S1C6200/6200A CORE CPU MANUAL...

  • Page 45: Disable Interrupts

    Clock Cycles: Flag: C – Not affected Z – Not affected D – Not affected I – Description: Enables all interrupts. Example: C flag Z flag D flag I flag S1C6200/6200A CORE CPU MANUAL F57H F48H EPSON 3 INSTRUCTION SET...
  • Page 46 1000 1000 0100 0100 1000 1000 FAN A,B FAN MX,B 1000 1000 1010 1010 0101 0101 1110 1110 EPSON D80H to DBFH FAN B,2 1000 1000 0100 0100 1000 1000 F10H to F1FH FAN A,MY 1000 1000 1010 1010 0101...
  • Page 47 0001 0001 to n ) + 1 INC M1 INC M3 0100 0101 1111 1111 0111 0111 EPSON 3 INSTRUCTION SET FF8H I flag 0011 0011 0011 0100 Interrupt vector address F60H to F6FH INC M0DH 0101 0101 0000 0000...

  • Page 48: Inc Sp

    Increments the contents of register X by 1. This operation does not affect the flags. Example: X register C flag Z flag FDBH INC SP 1110 1111 1111 0000 EE0H INC X 1111 1110 1111 1111 EPSON S1C6200/6200A CORE CPU MANUAL...

  • Page 49: Inc Y

    S1C6200/6200A CORE CPU MANUAL INC Y 1011 0111 1011 1000 NBP, PCP NPP, PCSH B, PCSL PSET 15H 1000 1000 0001 0101 1001 0000 1001 0001 0110 0110 0000 0000 EPSON 3 INSTRUCTION SET EF0H FE8H JPBA 0101 0101 0000 0110 0110 0000...
  • Page 50 1000 0000 NBP, PCP NPP, PCS to s PSET 11H 1001 1001 0001 0001 1000 1111 1001 0000 EPSON if C = 1 200H to 2FFH JP C,10H 0010 0110 0110 0110 0011 1110 0001 0000 0000 0000 if C = 0...
  • Page 51 0000 0111 0001 0000 NBP, PCP NPP, PCS to s PSET 0AH 0000 0000 0001 1010 0100 0010 0100 0011 EPSON 3 INSTRUCTION SET if Z = 0 700H to 7FFH 000H to 0FFH JP 10H 1010 1010 0001 0000...

  • Page 52: Lbpx Mx,E Load Immediate Data E To Memory, And Increment X By

    LBPX MX,18H LBPX MX,36H 0001 1110 0010 0000 0010 1000 1111 0001 0000 0000 0111 0111 EPSON if Z = 1 600H to 6FFH JP Z,10H 0101 1011 1011 1011 0000 0100 0001 0000 0000 0000 0110 0110...

  • Page 53: Ld A,Mn

    LD A,M5 0100 1111 1111 1111 0100 0100 to n LD B,M7 0100 0110 0110 0110 1010 1010 EPSON 3 INSTRUCTION SET FA0H to FAFH LD A,M6 0100 1111 0100 FB0H to FBFH LD B,M8 1010 0110 1010...
  • Page 54 Memory (00H) Memory (01H) LD M0AH,A LD M0BH,A 0110 0110 0100 0110 1011 1011 LD M0,B 0100 0100 1011 0100 1111 1111 EPSON F80H to F8FH 0110 0110 0110 F90H to F9FH LD M1,B 0100 0100 0100 S1C6200/6200A CORE CPU MANUAL...
  • Page 55 0010 0111 1001 1001 X + 1 LDPX A,B LDPX B,MY 0100 1001 0100 1010 1010 1101 1101 1101 0000 0000 EPSON 3 INSTRUCTION SET E60H to E6FH 1000 0101 0111 1010 EE0H to EEFH 0100 1011 1101 0000 0000...
  • Page 56 0111 0010 0010 Y + 1 LDPY A,B LDPY MX,B 0100 1000 0100 1001 1010 1000 1000 1000 0010 0010 EPSON E70H to E7FH 0010 1111 0111 0000 EF0H to EFFH 0100 1010 1000 1000 1000 S1C6200/6200A CORE CPU MANUAL...
  • Page 57 B register Memory (MY) S1C6200/6200A CORE CPU MANUAL LD A,6 0101 0110 1001 1001 LD A,B 0010 0000 0000 0000 0110 0110 EPSON 3 INSTRUCTION SET E00H to E3FH LD MY,0 0110 0000 EC0H to ECFH LD B,MY 0000 0110 0110...
  • Page 58 A register Memory (MY) FE4H to FE7H LD MX,SPH LD A,SPH 0111 0111 0111 0000 0000 0111 1100 0111 0111 FF4H to FF7H LD A,SPL LD MY,SPL 1001 1001 1001 0010 1001 1001 0000 0000 1001 EPSON S1C6200/6200A CORE CPU MANUAL...
  • Page 59 S1C6200/6200A CORE CPU MANUAL EA4H to EA7H LD B,XH LD MX,XH 1010 1010 1010 0010 1010 1010 0000 0000 1010 EA8H to EABH LD MY,XL LD A,XL 0000 0000 0000 1101 1101 0000 0001 0000 0000 EPSON 3 INSTRUCTION SET...
  • Page 60 A register Memory (MY) EA0H to EA3H LD MX,XP LD A,XP 1111 1111 1111 0010 0010 1111 0101 1111 1111 EB4H to EB7H LD A,YH LD MY,YH 1010 1010 1010 1100 1010 1010 1110 1110 1010 EPSON S1C6200/6200A CORE CPU MANUAL...
  • Page 61 S1C6200/6200A CORE CPU MANUAL EB8H to EBBH LD B,YL LD MX,YL 0000 0000 0000 0110 0000 0000 1011 1011 0000 EB0H to EB3H LD MY,YP LD B,YP 1010 1010 1010 1100 1100 1010 0110 1010 1010 EPSON 3 INSTRUCTION SET...
  • Page 62 B register Memory (MX) LD SPH,A 1001 0011 0011 0011 1100 1100 LD SPL,B 1011 0111 0111 0111 1111 1111 EPSON FE0H to FE3H LD SPH,MY 1100 0011 1100 FF0H to FF3H LD SPL,MX 1111 0111 1111 S1C6200/6200A CORE CPU MANUAL...
  • Page 63 Memory (MY) S1C6200/6200A CORE CPU MANUAL to e , XL to e LD X,6FH 0000 0110 1011 1111 LD XH,A 0000 1011 1011 1011 0110 0110 EPSON 3 INSTRUCTION SET B00H to BFFH E84H to E87H LD XH,MY 0110 1011 0110...
  • Page 64 B register Memory (MX) E88H to E8BH LD XL,MY LD XL,A 0000 0010 1011 1011 1011 1011 0010 0010 0010 E80H to E83H LD XP,B LD XP,MX 1001 0001 1011 0001 0001 0001 1011 1011 1011 EPSON S1C6200/6200A CORE CPU MANUAL...
  • Page 65 Memory (MX) S1C6200/6200A CORE CPU MANUAL to e , YL to e LD Y,E1H 0001 1110 1100 0001 LD YH,B 0000 0110 0110 0110 0101 0101 EPSON 3 INSTRUCTION SET 800H to 8FFH E94H to E97H LD YH,MX 0101 0110 0101...
  • Page 66 A register Memory (MX) E98H to E9BH LD YL,B LD YL,MX 1011 1010 0111 1010 1010 1010 0111 0111 0111 E90H to E93H LD YP,MX LD YP,A 0011 0000 0100 0100 0100 0100 0000 0000 0000 EPSON S1C6200/6200A CORE CPU MANUAL...

  • Page 67: No Operation For 5 Clock Cycles

    Increments the program counter by 1. Has no other effect for 7 clock cycles. Example: S1C6200/6200A CORE CPU MANUAL 1 0 1 1 FFBH NOP5 0011 0011 0001 0011 0001 0100 1 1 1 1 FFFH NOP7 1010 1010 1001 1001 1001 1010 EPSON 3 INSTRUCTION SET...
  • Page 68 Memory (MX) Z flag 1 1 1 1 NOT A 1001 0110 1111 1111 to i OR B,5 0100 0101 0011 0011 EPSON D0FH to D3FH NOT MY 0110 0000 CC0H to CFFH OR MX,0BH 0101 0111 S1C6200/6200A CORE CPU MANUAL...

  • Page 69: Or R,Q

    S1C6200/6200A CORE CPU MANUAL OR MY,0 0011 0011 0000 0000 SP + 1 1 0 1 0 POP F 1001 1001 0001 1001 EPSON 3 INSTRUCTION SET AD0H to ADFH OR A,0CH 1111 0000 FDAH M(SP) = flag flag flag flag...
  • Page 70 SP + 1 0 0 r FD0H to FD3H M(SP) = POP B 1001 1001 0101 1001 SP + 1 0 1 0 1 FD5H M(SP) = POP XH 0110 0110 0010 0110 EPSON = r-register = XH S1C6200/6200A CORE CPU MANUAL...

  • Page 71: Pop Xl

    SP + 1 0 1 1 0 FD6H M(SP) = POP XL 0001 0001 1101 0001 SP + 1 0 1 0 0 FD4H POP XP M(SP) = 0101 0101 0111 0101 EPSON 3 INSTRUCTION SET = XL = XP...

  • Page 72: Pop Yh

    SP + 1 1 0 0 0 FD8H M(SP) = POP YH 1101 1101 0010 1101 SP + 1 1 0 0 1 FD9H POP YL M(SP) = 0100 0100 0101 0100 EPSON = YH = YL S1C6200/6200A CORE CPU MANUAL...
  • Page 73 0 1 1 1 POP YP 0000 0000 0001 0000 , NPP to p PSET 1FH 1000 1000 0001 1111 0010 0011 0010 0100 EPSON 3 INSTRUCTION SET FD7H M(SP) = = YP E40H to E5FH JP 00H 1111 1111 0000 0000...
  • Page 74 A register 1 0 1 0 FCAH M(SP) = PUSH F 0100 0001 0001 0001 0 0 r FC0H to FC3H PUSH A M(SP) = 1000 0010 0010 0010 EPSON flag flag flag flag = r-register S1C6200/6200A CORE CPU MANUAL...

  • Page 75: Push Xh

    XL register S1C6200/6200A CORE CPU MANUAL 0 1 0 1 FC5H M(SP) = PUSH XH 0000 1000 1000 1000 0 1 1 0 FC6H PUSH XL M(SP) = 1111 0110 0110 0110 EPSON 3 INSTRUCTION SET = XH = XL...

  • Page 76: Push Xp

    Example: Memory (BEH) YH register 0 1 0 0 FC4H M(SP) = PUSH XP 0011 0000 0000 0000 1 0 0 0 FC8H M(SP) = PUSH YH 0100 0001 0001 0001 EPSON = XP = YH S1C6200/6200A CORE CPU MANUAL...

  • Page 77: Push Yl

    YP register S1C6200/6200A CORE CPU MANUAL 1 0 0 1 FC9H M(SP) = PUSH YL 0001 0111 0111 0111 0 1 1 1 FC7H PUSH YP M(SP) = 1111 0000 0000 0000 EPSON 3 INSTRUCTION SET = YL = YP...

  • Page 78: Reset Carry Flag

    Example: A register D flag C flag Z flag 1 1 1 0 F5EH ADD A,4 1101 0001 0001 1 0 1 1 F5BH ADD A,8 LD A,6 0110 0100 0100 EPSON ADD A,8 0110 1110 S1C6200/6200A CORE CPU MANUAL...

  • Page 79: Return From Subroutine

    0010 1010 1011 0010 1101 1101 1101 0010 0010 0010 0010 0010 1010 0010 1100 0000 0101 0000 1111 EPSON 3 INSTRUCTION SET M(SP+2), SP SP + 3 FDFH M(SP+2), SP SP + 3, X + 2 100H to 1FFH...
  • Page 80 1 1 1 0 RETS 0110 0000 1001 0000 0000 0111 0110 0110 0000 0000 0000 0000 C, C r-register RLC A 0011 0111 EPSON M(SP+2), SP SP + 3, PC FDEH AF0H to AFFH r-register S1C6200/6200A CORE CPU MANUAL PC + 1...
  • Page 81 RRC MY 1010 1101 to i is zero; otherwise, not affected. is zero; otherwise, not affected. is zero; otherwise, not affected. is zero; otherwise, not affected. RST F,2 1010 0010 EPSON 3 INSTRUCTION SET E8CH to E8FH F50H to F5FH...
  • Page 82 Subtracts the carry flag and immediate data i from the r-register. Example: A register Memory (MY) C flag Z flag 1 1 0 1 ADD A,3 1101 0000 to i SBC A,9 SBC MY,0DH 1000 1111 1110 1110 EPSON F5DH 0000 D40H to D7FH 1111 0000 S1C6200/6200A CORE CPU MANUAL...

  • Page 83: Sbc R,Q

    Sets the C (carry) flag. Example: C flag S1C6200/6200A CORE CPU MANUAL AB0H to ABFH SBC A,B SBC MY,MX 1110 1011 1011 0010 0010 0010 1001 1001 1001 0100 0100 1011 0 0 0 1 F41H EPSON 3 INSTRUCTION SET...
  • Page 84 0101 0000 0101 0001 0110 0100 0010 0010 M(Y) - r - C, Y Y + 1 1 1 r SCPY MY,A 1111 1111 0000 0000 0111 0100 0010 0010 EPSON F38H to F3BH F3CH to F3FH S1C6200/6200A CORE CPU MANUAL...

  • Page 85: Set Decimal Flag

    S1C6200/6200A CORE CPU MANUAL 0 1 0 0 to i is 1; otherwise, not affected. is 1; otherwise, not affected. is 1; otherwise, not affected. is 1; otherwise, not affected. SET F,0DH 0011 1111 EPSON 3 INSTRUCTION SET F44H F40H to F4FH...
  • Page 86 B register C flag Z flag 1 0 0 1 FF9H Instruction State 0100 0011 0000 0100 0011 0001 SLEEP NOP5 0001 0000 0001 AA0H to AAFH SUB A,B 1100 1001 0011 0011 EPSON I flag S1C6200/6200A CORE CPU MANUAL...

  • Page 87: Set Zero Flag

    The result is stored in the r-register. Example: A register Memory (MX) Z flag S1C6200/6200A CORE CPU MANUAL 0 0 1 0 to i XOR A,12 0110 1010 0001 0001 EPSON 3 INSTRUCTION SET F42H D00H to D3FH XOR MX,1 1010 0000...
  • Page 88 Operation: OP-Code: Type: Clock Cycles: Flag: C – Z – D – I – Description: Example: XOR A,MY 0100 1100 1111 1111 0111 0111 1000 1000 EPSON AE0H to AEFH XOR MX,B 1100 1111 1000 1000 S1C6200/6200A CORE CPU MANUAL...
  • Page 89 Logical AND Clock Cycles: ... Logical OR Flag: C – ... Exclusive-OR Z – ... Reset flag D – ... Set flag I – ... Set/reset flag Description: ... Decimal addition/subtraction Example: S1C6200/6200A CORE CPU MANUAL EPSON 3 INSTRUCTION SET...

  • Page 90: Appendix

    S1C6200. It is recommended that users of S1C6200A read this section. S1C6200A is a Core CPU which has been made easier to integrate software by improving the parts of the S1C6200 CPU which are difficult to use.
  • Page 91 Status: Fetch Clock Status Instruction PSET Interrupt processing: Status: Fetch Fig. A2.2.1 Timing chart of S1C6200A interrupt S1C6200/6200A CORE CPU MANUAL APPENDIX A. S1C6200A (ADVANCED S1C6200) CORE CPU 12-clock Instrruction Interrupt Interrupt processing: 12-clock instruction 7-clock instruction 5-clock instruction Execute...

  • Page 92: Instruction

    This section describes the operation for reading the interrupt factor flag during EI (enable interrupt flag) in the regular 1-chip micro controller which uses S1C6200 Core CPU and in the regular 1-chip micro control- ler which uses S1C6200A Core CPU. For information on accurate operation, see the respective hardware manuals of the S1C62 Family.

  • Page 93: B. I Nstruction I Ndex

    Indirect jump using registers A and B ... 43 Jump if carry flag is set ... 44 Jump if not carry ... 44 Jump if not zero ... 45 Jump ... 45 Jump if zero ... 46 EPSON APPENDIX B. INSTRUCTION INDEX...
  • Page 94 Pop stack data into XP ... 65 Pop stack data into YH ... 66 Pop stack data into YL ... 66 Pop stack data into YP ... 67 Page set ... 67 Push flag onto stack ... 68 EPSON S1C6200/6200A CORE CPU MANUAL...
  • Page 95 Set flags using immediate data i ... 79 Sleep ... 80 Subtract q-register from r-register ... 80 Set zero flag ... 81 Exclusive-OR immediate data i with r-register ... 81 Exclusive-OR q-register with r-register ... 82 EPSON APPENDIX B. INSTRUCTION INDEX...
  • Page 96 EPSON HONG KONG LTD. 20/F., Harbour Centre, 25 Harbour Road Wanchai, Hong Kong Phone: +852-2585-4600 Fax: +852-2827-4346 Telex: 65542 EPSCO HX EPSON TAIWAN TECHNOLOGY & TRADING LTD. 10F, No. 287, Nanking East Road, Sec. 3 Taipei Phone: 02-2717-7360 Fax: 02-2712-9164 Telex: 24444 EPSONTB HSINCHU OFFICE 13F-3, No.
  • Page 97 In pursuit of “Saving” Technology, Epson electronic devices. Our lineup of semiconductors, liquid crystal displays and quartz devices assists in creating the products of our customers’ dreams. Epson IS energy savings.
  • Page 98 S1C6200/6200A Core CPU Manual ELECTRONIC DEVICES MARKETING DIVISION EPSON Electronic Devices Website http://www.epson.co.jp/device/ First issue February, 1989 Printed February, 2001 in Japan...

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