Epson S1C33210 Technical Manual page 123

Pin No. Signal name
101 CTS
102 V
SS
103 PLLC
104 V
SS
105 PLLS1
106 PLLS0
107 RXD/SIN3
108 DCD
109 MSEL
110 GOUT
111 V
DD
112 OSC3
113 OSC4
114 EA10MD0
115 EA10MD1
116 #X2SPD
117 P21/#DWE/#GAAS
118 P22/TM0
119 P23/TM1
120 DSIO
121 P10/EXCL0/T8UF0/DST0
122 P11/EXCL1/T8UF1/DST1
123 P12/EXCL2/T8UF2/DST2
124 P13/EXCL3/T8UF3/DPC0
125 P14/FOSC1/DCLK
126 P24/TM2/#SRDY2
127 P25/TM3/#SCLK2
128 P15/EXCL4/#DMAEND0
Note 1) The voltage applied to this pin must be 0V V
Note 2) This pin is set as an input pin during device testing. Normally it is an output pin.
Note 3) The XBB1 cell is a fail-safe cell.
S1C33210 PRODUCT PART
I/O cell Characteristic
name Input
XIBC CMOS/LVTTL
XLIN
XIBCD1 CMOS/LVTTL
XIBC CMOS/LVTTL
XIBC CMOS/LVTTL
XIBC CMOS/LVTTL
XIBC CMOS/LVTTL
XIBCP2
XOB1T CMOS/LVTTL
XLIN
XLOT
XIBC CMOS/LVTTL
XIBCP2 CMOS/LVTTL
XIBC CMOS/LVTTL
XBH1T CMOS/LVTTL SCHMITT
XBH1T CMOS/LVTTL SCHMITT
XBH1T CMOS/LVTTL SCHMITT
XBH2P2T CMOS/LVTTL SCHMITT
XBH2T CMOS/LVTTL SCHMITT
XBH2T CMOS/LVTTL SCHMITT
XBH2T CMOS/LVTTL SCHMITT
XBH2T CMOS/LVTTL SCHMITT
XBH2T CMOS/LVTTL SCHMITT
XBH1T CMOS/LVTTL SCHMITT
XBH1T CMOS/LVTTL SCHMITT
XBH1T CMOS/LVTTL SCHMITT
V
IN DD
EPSON
APPENDIX B PIN CHARACTERISTICS
Pull-up/
Output down
Pull-down
Pull-up
2 mA
Pull-up
2 mA
2 mA
2 mA
6 mA Pull-up
6 mA
6 mA
6 mA
6 mA
6 mA
2 mA
2 mA
2 mA
.
Power Remarks
supply
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
A-109