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Epson S1C63666 Technical Manual

Cmos 4-bit single chip microcomputer
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CMOS 4 - BIT SINGLE CHIP MICROCOMPUTER
S1C63666
Technical Manual
S1C63666 Technical Hardware

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Summary of Contents for Epson S1C63666

  • Page 1 CMOS 4 - BIT SINGLE CHIP MICROCOMPUTER S1C63666 Technical Manual S1C63666 Technical Hardware...
  • Page 2 No part of this material may be reproduced or duplicated in any form or by any means without the written permission of Seiko Epson. Seiko Epson reserves the right to make changes to this material without notice. Seiko Epson does not assume any...
  • Page 3 Revisions and Additions for this manual Chapter Section Page Item Contents Features Explanation was revised. 5–8 Mask Option Explanation was revised. 2.1.5 LCD system voltage circuit Figure 2.1.5.1 was revised. Initial Reset Figure 2.2.1 was revised. 2.2.1 Reset terminal (RESET) Explanation was added.
  • Page 5 Configuration of product number Devices 63158 0A01 Packing specifications 00 : Besides tape & reel 0A : TCP BL 2 directions 0B : Tape & reel BACK 0C : TCP BR 2 directions 0D : TCP BT 2 directions 0E : TCP BD 2 directions 0F : Tape &...

  • Page 7: Features

    4.4.2 OSC1 oscillation circuit ................32 4.4.3 OSC3 oscillation circuit ................33 4.4.4 Switching of operating voltage ..............34 4.4.5 Clock frequency and instruction execution time ........34 4.4.6 I/O memory of oscillation circuit .............. 35 4.4.7 Programming notes ................... 36 EPSON S1C63666 TECHNICAL MANUAL...
  • Page 8 4.11.5 16-bit timer (timer 0 + timer 1) .............. 81 4.11.6 Interrupt function ..................82 4.11.7 Control of TOUT output ................82 4.11.8 Transfer rate setting for serial interface ..........83 4.11.9 I/O memory of programmable timer ............84 4.11.10 Programming notes ................89 EPSON S1C63666 TECHNICAL MANUAL...
  • Page 9 4.18.5 Programming notes ................133 ______________________________________ 134 CHAPTER UMMARY OF OTES 5.1 Notes for Low Current Consumption ............134 5.2 Summary of Notes by Function ..............135 5.3 Precautions on Mounting ................139 ___________________________ 141 CHAPTER ASIC XTERNAL IRING IAGRAM EPSON S1C63666 TECHNICAL MANUAL...
  • Page 10 OARD FOR A.1 Names and Functions of Each Part ............152 A.2 Connecting to the Target System ..............155 A.3 Usage Precautions ..................157 A.3.1 Operational precautions ................157 A.3.2 Differences with the actual IC ..............157 EPSON S1C63666 TECHNICAL MANUAL...
  • Page 11 CHAPTER UTLINE The S1C63666 is a microcomputer which has a high-performance 4-bit CPU S1C63000 as the core CPU, ROM (16,384 words × 13 bits), RAM (5,120 words × 4 bits), multiply-divide circuit, serial interface, watchdog timer, programmable timer, time base counters (2 systems), an LCD driver that can drive a maximum 64 segments ×...

  • Page 12: Block Diagram

    K00–K03 K10–K13 Input Port – TEST – Power Controller Serial Interface CA–CD P00–P03 I/O Port P10–P13 R00–R03 Output Port R10–R13 Sound Generator SEN0, SEN1 R/F Converter CMPP0 Analog RFIN CMPM0 Comparator RFOUT Fig. 1.2.1 Block diagram EPSON S1C63666 TECHNICAL MANUAL...

  • Page 13: Pin Layout Diagram

    SEG58 SEG26 OSC3 SEG59 SEG27 OSC4 SEG60 SEG28 SEG61 SEG29 TEST SEG62 SEG30 RESET SEG63 SEG31 N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. : No Connection Fig. 1.3.1 Pin layout diagram (QFP20-144pin) EPSON S1C63666 TECHNICAL MANUAL...

  • Page 14: Pin Description

    R/f converter oscillation frequency output pin CMPP0 Analog comparator non-inverted input pin CMPM0 Analog comparator inverted input pin Sound output pin Sound inverted output pin SVD external voltage input pin RESET Initial reset input pin TEST Testing input pin EPSON S1C63666 TECHNICAL MANUAL...
  • Page 15 S1C63666, are used for this selection. Mask pattern of the IC is finally generated based on the data created by winfog and winsog. Refer to the "S5U1C63000A Manual" for winfog and winsog.
  • Page 16 Refer to Section 4.8.5, "Segment option", for details. <Option list> The following is the option list for the S1C63666. Multiple selections are available in each option item as indicated in the option list. Select the specifica- tions that meet the target system and check the appropriate box. Be sure to record the specifications for unused functions too.
  • Page 17 12. LCD DRIVING POWER 1. Internal Power (3.0 V panel) 2. External Power 1/3 bias, V (4.5 V panel) 3. External Power 1/3 bias, V (3.0 V panel) 4. External Power 1/2 bias, V (3.0 V panel) EPSON S1C63666 TECHNICAL MANUAL...
  • Page 18 SEG output SEG61 DC output SEG62 SEG output SEG63 DC output <address> H: <Output specification> S: RAM data high-order address (0–9) Segment output RAM data low-order address (0–F) Complementary output Data bit (0–3) Nch open drain output EPSON S1C63666 TECHNICAL MANUAL...

  • Page 19: Lcd System Voltage Circuit

    The S1C63666 operates by applying a single power supply within the above range between V and V The S1C63666 itself generates the voltage necessary for all the internal circuits by the built-in power supply circuits shown in Table 2.1.2. Table 2.1.2 Power supply circuits...
  • Page 20 CPU and internal logic circuits. The S1C63666 is designed with twin clock specifications; it has two types of oscillation circuits OSC1 and OSC3 built-in. Use OSC1 clock for normal operation, and switch to OSC3 using software when high- speed operation is necessary.
  • Page 21 R/f converter in order to avoid decreasing the conversion accuracy due to noise. However, the same voltage level as the V –V must be supplied to the V –V EPSON S1C63666 TECHNICAL MANUAL...

  • Page 22: Reset Terminal (Reset

    CHAPTER 2: POWER SUPPLY AND INITIAL RESET 2.2 Initial Reset To initialize the S1C63666 circuits, initial reset must be executed. There are two ways of doing this. (1) External initial reset by the RESET terminal (2) External initial reset by simultaneous high input to terminals K00–K03 (mask option setting) The circuits are initialized by either (1) or (2).
  • Page 23 Index register X Undefined ∗ See Section 4.1, "Memory Map". Index register Y Undefined Program counter 0110H Stack pointer SP1 Undefined Stack pointer SP2 Undefined Zero flag Undefined Carry flag Undefined Interrupt flag Extension flag Queue register Undefined EPSON S1C63666 TECHNICAL MANUAL...

  • Page 24: Special Output

    For setting procedure of the functions, see explanations for each of the peripheral circuits. 2.3 Test Terminal (TEST) This is the terminal used for the factory inspection of the IC. During normal operation, connect the TEST terminal to V EPSON S1C63666 TECHNICAL MANUAL...
  • Page 25 The core CPU can linearly access the program space up to step FFFFH from step 0000H, however, the program area of the S1C63666 is step 0000H to step 3FFFH. The program start address after initial reset is assigned to step 0110H. The non-maskable interrupt (NMI) vector and hardware interrupt vectors are allocated to step 0100H and steps 0102H–010EH, respectively.
  • Page 26 4,096 words × 4 bits. The data ROM is assigned to addresses 8000H to 8FFFH on the data memory map, and the data can be read using the same data memory access instructions as the RAM. EPSON S1C63666 TECHNICAL MANUAL...

  • Page 27: Memory Map

    IRCUITS AND PERATION The peripheral circuits of S1C63666 (timer, I/O, etc.) are interfaced with the CPU in the memory mapped I/O method. Thus, all the peripheral circuits can be controlled by accessing the I/O memory on the memory map using the memory operation instructions. The following sections explain the detailed operation of each peripheral circuit.
  • Page 28 R02 output port data (PTOUT=0) Fix at "1" when TOUT is used. FF31H High R01 output port data High R00 output port data Remarks ∗1 Initial value at initial reset ∗2 Not set in the circuit ∗3 Constantly "0" when being read EPSON S1C63666 TECHNICAL MANUAL...
  • Page 29 ∗2 – Unused ALOFF ALON ALOFF All Off Normal LCD all Off control FF61H ALON All On Normal LCD all On control ∗3 ∗2 – Unused LCD contrast adjustment [LC3–0] – FF62H Contrast Light – Dark EPSON S1C63666 TECHNICAL MANUAL...
  • Page 30 Key mask K10–11 K10–12 K10–13 LCURF Request Lap data carry-up request flag LCURF CRNWF SWRUN SWRST CRNWF Renewal Capture renewal flag FF79H SWRUN Stop Stopwatch timer Run/Stop ∗3 SWRST Reset Reset Invalid Stopwatch timer reset (writing) EPSON S1C63666 TECHNICAL MANUAL...
  • Page 31 RFRUNR Stop Reference oscillation Run/Stop control RFRUNS Stop Sensor oscillation Run/Stop control ∗2 – ∗2 – FF92H Measurement counter MC0–MC3 ∗2 – ∗2 – ∗2 – ∗2 – FF93H Measurement counter MC4–MC7 ∗2 – ∗2 – EPSON S1C63666 TECHNICAL MANUAL...
  • Page 32 Timer 1 Run/Stop PTPS21 Prescaler 2 [PTPS21, 20] PTPS21 PTPS20 PTRST2 PTRUN2 division ratio Division ratio 1/32 1/256 PTPS20 selection FFC5H ∗3 ∗2 PTRST2 – Reset Invalid Timer 2 reset (reload) PTRUN2 Stop Timer 2 Run/Stop EPSON S1C63666 TECHNICAL MANUAL...
  • Page 33 – Unused FFE2H ∗3 ∗2 – Unused EISIF Enable Mask Interrupt mask register (Serial I/F) ∗3 ∗2 – Unused EIK0 ∗3 ∗2 – Unused FFE3H ∗3 ∗2 – Unused EIK0 Enable Mask Interrupt mask register (K00–K03) EPSON S1C63666 TECHNICAL MANUAL...
  • Page 34 Interrupt factor flag (Stopwatch timer 10 Hz) ∗3 ∗2 – Unused IRFB IRFM ∗3 ∗2 – Unused FFF7H IRFB Interrupt factor flag (R/f converter reference oscillate completion) IRFM Reset Invalid Interrupt factor flag (R/f converter sensor oscillate completion) EPSON S1C63666 TECHNICAL MANUAL...

  • Page 35: Power Control

    4.2 Power Control 4.2.1 Configuration of power supply circuit The S1C63666 has built-in power supply circuits shown in Figure 4.2.1.1 so the voltages to drive the CPU, internal logic circuits, oscillation circuits and LCD driver can be generated on the chip.

  • Page 36: Power Control Procedure

    1. Check that the supply voltage V is 2.4 V or higher using the SVD circuit to 1.13 V or lower (LC3–LC0 ≤ 6) 2. Set the LCD drive voltage V 3. Set the halver mode (VDC3 = "1") EPSON S1C63666 TECHNICAL MANUAL...
  • Page 37 CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Power Control) Switching to high-speed operation The S1C63666 is designed with twin clock specifications; it has two types of oscillation circuits OSC1 (for low-speed operation) and OSC3 (for high-speed operation) built-in. Use OSC1 clock for normal operation, and switch it to OSC3 using software when high-speed operation is necessary.
  • Page 38 It takes about 100 msec for the LCD drive voltage to stabilize after starting up the LCD system voltage circuit by writing "1" to the LPWR register. At initial reset, this register is set to "0". EPSON S1C63666 TECHNICAL MANUAL...
  • Page 39 (2) When setting the LCD system voltage circuit to the halver mode, make sure that the supply voltage is 2.4 V or higher using the SVD circuit before writing "1" to VDC3. Furthermore, set the V voltage (contrast) to 1.13 V or lower (LC register = 6 or less). EPSON S1C63666 TECHNICAL MANUAL...

  • Page 40: Watchdog Timer

    4.3.1 Configuration of watchdog timer The S1C63666 has a built-in watchdog timer that operates with a 256 Hz divided clock from the OSC1 as the source clock. The watchdog timer starts operating after initial reset, however, it can be stopped by the software.
  • Page 41 (1) When the watchdog timer is being used, the software must reset it within 3-second cycles. (2) Because the watchdog timer is set in operation state by initial reset, set the watchdog timer to disabled state (not used) before generating an interrupt (NMI) if it is not used. EPSON S1C63666 TECHNICAL MANUAL...

  • Page 42: Osc1 Oscillation Circuit

    4.4.1 Configuration of oscillation circuit The S1C63666 has two oscillation circuits (OSC1 and OSC3). OSC1 is a crystal oscillation circuit that supplies the operating clock to the CPU and peripheral circuits. OSC3 is either a CR or a ceramic oscilla- tion circuit.

  • Page 43: Osc3 Oscillation Circuit

    CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Oscillation Circuit) 4.4.3 OSC3 oscillation circuit The S1C63666 has built-in the OSC3 oscillation circuit that generates the CPU's sub-clock (Max. 4 MHz) for high speed operation and the source clock for peripheral circuits needing a high speed clock (pro- grammable timer, FOUT output).
  • Page 44 Table 4.4.5.1 shows the instruction execution time according to each frequency of the system clock. Table 4.4.5.1 Clock frequency and instruction execution time Instruction execution time (µsec) Clock frequency 1-cycle instruction 2-cycle instruction 3-cycle instruction OSC1: 32.768 kHz OSC3: 1.1 MHz OSC3: 4 MHz EPSON S1C63666 TECHNICAL MANUAL...
  • Page 45 When VDC0 = "0" and OSCC = "0" (OSC3 oscillation is off), setting of CLKCHG = "1" becomes invalid and switching to OSC3 is not performed. Furthermore, do not switch the CPU clock to OSC3 in the halver mode. At initial reset, this register is set to "0". EPSON S1C63666 TECHNICAL MANUAL...
  • Page 46 OSC1 clock. Do not switch the system clock to OSC3. (5) Do not switch the operating voltage to V while the CPU is operating with the OSC3 clock. Further- more, do not stop the high-speed operating voltage regulator. EPSON S1C63666 TECHNICAL MANUAL...

  • Page 47: Configuration Of Input Ports

    4.5 Input Ports (K00–K03 and K10–K13) 4.5.1 Configuration of input ports The S1C63666 has eight bits of general-purpose input ports (K00–K03, K10–K13). Each input port termi- nal provides an internal pull-down resistor that can be enabled by mask option. Figure 4.5.1.1 shows the configuration of input port.
  • Page 48 K13) with the input port mask option. When "Gate direct" is selected, take care that the floating status does not occur for the input. Select "With pull-down resistor" for input ports that are not being used. EPSON S1C63666 TECHNICAL MANUAL...
  • Page 49 The reading is "1" when the terminal voltage of the eight bits of the input ports (K00–K03, K10–K13) goes high (V ), and "0" when the voltage goes low (V These bits are dedicated for reading, so writing cannot be done. EPSON S1C63666 TECHNICAL MANUAL...
  • Page 50 RETI instruction is executed unless the interrupt factor flag is reset. Therefore, be sure to reset (write "1" to) the interrupt factor flag in the interrupt service routine before shifting to the interrupt enabled state. At initial reset, these flags are set to "0". EPSON S1C63666 TECHNICAL MANUAL...
  • Page 51 "1") is set or the RETI instruction is executed unless the interrupt factor flag is reset. Therefore, be sure to reset (write "1" to) the interrupt factor flag in the interrupt service routine before shifting to the interrupt enabled state. EPSON S1C63666 TECHNICAL MANUAL...

  • Page 52: Configuration Of Output Ports

    (R00–R03 and R10–R13) 4.6.1 Configuration of output ports The S1C63666 has eight bits of general output ports. Output specifications of the output ports can be selected individually with the mask option. Two kinds of output specifications are available: complementary output and P-channel open drain output.

  • Page 53: High Impedance Control

    R02 and R03 registers when the special output has been selected. • Be aware that the output terminal shifts into high impedance status when "1" is written to the high impedance control register (R02HIZ, R03HIZ). EPSON S1C63666 TECHNICAL MANUAL...
  • Page 54 Note: A hazard may occur when the FOUT signal is turned on and off. Figure 4.6.4.3 shows the output waveform of the FOUT signal. R03HIZ register Fix at "0" R03 register Fix at "1" FOUTE register "0" "1" "0" FOUT output Fig. 4.6.4.3 Output waveform of FOUT signal EPSON S1C63666 TECHNICAL MANUAL...
  • Page 55 When "1" is written, it shifts into high impedance status. When the output ports R02 and R03 are used for special output (TOUT, FOUT), fix the R02HIZ register and the R03HIZ register at "0" (data output). At initial reset, these registers are set to "0". EPSON S1C63666 TECHNICAL MANUAL...
  • Page 56 "0", the TOUT signal is output from the R02 terminal. When "0" is written, the R02 termi- nal goes high (V When using the R02 output port for DC output, fix this register at "0". At initial reset, this register is set to "0". EPSON S1C63666 TECHNICAL MANUAL...
  • Page 57 (2) A hazard may occur when the FOUT signal and the TOUT signal are turned on and off. (3) When f is selected for the FOUT signal frequency, it is necessary to control the OSC3 oscillation OSC3 circuit before output. Refer to Section 4.4, "Oscillation Circuit", for the control and notes. EPSON S1C63666 TECHNICAL MANUAL...
  • Page 58 CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (I/O Ports) 4.7 I/O Ports (P00–P03 and P10–P13) 4.7.1 Configuration of I/O ports The S1C63666 has eight bits of general-purpose I/O ports. Figure 4.7.1.1 shows the configuration of the I/ O port. Pull-down control...
  • Page 59 I/O control. (See Table 4.7.1.1.) 4.7.4 Pull-down during input mode A pull-down resistor that operates during the input mode is built into each I/O port of the S1C63666. Mask option can set the use or non-use of this pull-down.
  • Page 60 Serial I/F clock trigger (writing) FF70H Stop Serial I/F clock status (reading) ESIF Serial I/F enable (P1 port function selection) *1 Initial value at initial reset *2 Not set in the circuit *3 Constantly "0" when being read EPSON S1C63666 TECHNICAL MANUAL...
  • Page 61 Make this waiting time the amount of time or more calculated by the following expression. 10 × C × R C: terminal capacitance 5 pF + parasitic capacitance ? pF R: pull-down resistance 375 k Ω (Max.) EPSON S1C63666 TECHNICAL MANUAL...
  • Page 62 Make this waiting time the amount of time or more calculated by the following expression. 10 × C × R C: terminal capacitance 5 pF + parasitic capacitance ? pF R: pull-down resistance 375 kΩ (Max.) EPSON S1C63666 TECHNICAL MANUAL...

  • Page 63: Configuration Of Lcd Driver

    ALOFF, ALON (all on) has priority over the ALOFF (all off). (2) Setting of drive duty In the S1C63666, the drive duty can be set to 1/4, 1/5 or 1/8 using the LDUTY1 and LDUTY0 registers as shown in Table 4.8.3.1.
  • Page 64 CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver) COM0 COM1 COM2 COM3 COM4 COM5 LCD lighting status COM0 COM1 COM2 COM6 COM3 SEG0–63 COM7 Not lit SEG0 SEG63 Frame Fig. 4.8.3.1 Dynamic drive waveform for 1/4 duty EPSON S1C63666 TECHNICAL MANUAL...
  • Page 65 CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver) COM0 COM1 COM2 COM3 COM4 LCD lighting status COM5 COM0 COM1 COM2 COM6 COM3 COM4 SEG0–63 COM7 Not lit SEG0 SEG63 Frame Fig. 4.8.3.2 Dynamic drive waveform for 1/5 duty EPSON S1C63666 TECHNICAL MANUAL...
  • Page 66 CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver) COM0 COM1 COM2 COM3 COM4 LCD lighting status COM0 COM1 COM2 COM5 COM3 COM4 COM5 COM6 COM6 COM7 SEG0–63 Not lit COM7 SEG0 SEG63 Frame Fig. 4.8.3.3 Dynamic drive waveform for 1/8 duty EPSON S1C63666 TECHNICAL MANUAL...
  • Page 67 CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver) (3) Static drive The S1C63666 provides software setting of the LCD static drive. However, this function is available only when "External power supply 1/2 bias (for 3.0 V panel)" is selected by mask option.

  • Page 68: Segment Option

    2. When DC output is selected, either complementary output or N-channel open drain output can be selected for each terminal with the mask option. ∗ The terminal pairs are combination of SEG2 × n and SEG2 × n + 1 (where n is an integer from 0 to 31). EPSON S1C63666 TECHNICAL MANUAL...
  • Page 69 SEG output SEG61 DC output SEG62 SEG output SEG63 DC output <address> H: RAM data high-order address (0–9) <Output specification> S: Segment output RAM data low-order address (0–F) Complementary output Data bit (0–3) Nch open drain output EPSON S1C63666 TECHNICAL MANUAL...
  • Page 70 CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver) 4.8.6 LCD contrast adjustment In the S1C63666, the LCD contrast can be adjusted by the software. It is realized by controlling the voltages V and V output from the LCD system voltage circuit.
  • Page 71 Table 4.8.7.2 Drive duty setting LDUTY1 LDUTY0 Drive duty Common terminal used Maximum segment number ∗ 512 (64 × 8) COM0–COM7 320 (64 × 5) COM0–COM4 256 (64 × 4) COM0–COM3 At initial reset, this register is set to "0". EPSON S1C63666 TECHNICAL MANUAL...
  • Page 72 Because at initial reset, the contents of display memory are undefined and LC3–LC0 (LCD contrast) is set to 0000B, there is need to initialize by the software. Furthermore, take care of the registers LPWR and ALOFF because these are set so that the display goes off. EPSON S1C63666 TECHNICAL MANUAL...

  • Page 73: Clock Timer

    4.9 Clock Timer 4.9.1 Configuration of clock timer The S1C63666 has a built-in clock timer that uses OSC1 (crystal oscillator) as the source oscillator. The clock timer is configured of an 8-bit binary counter that serves as the input clock, f...

  • Page 74: Interrupt Function

    (EIT0, EIT1, EIT2, EIT3). However, regardless of the interrupt mask register setting, the interrupt factor flag is set to "1" at the falling edge of the corresponding signal. EPSON S1C63666 TECHNICAL MANUAL...
  • Page 75 "0" is written. In the STOP status, the timer data is maintained until the next RUN status or the timer is reset. Also, when the STOP status changes to the RUN status, the data that is maintained can be used for resuming the count. At initial reset, this register is set to "0". EPSON S1C63666 TECHNICAL MANUAL...
  • Page 76 "1") is set or the RETI instruction is executed unless the interrupt factor flag is reset. Therefore, be sure to reset (write "1" to) the interrupt factor flag in the interrupt service routine before shifting to the interrupt enabled state. EPSON S1C63666 TECHNICAL MANUAL...
  • Page 77 4.10.1 Configuration of stopwatch timer The S1C63666 has a 1/1,000 sec stopwatch timer. The stopwatch timer is configured of a 3-stage, 4-bit BCD counter serving as the input clock of a 1,000 Hz signal output from the prescaler. Data can be read out four bits (1/1,000 sec, 1/100 sec and 1/10 sec) at a time by the software.
  • Page 78 Figure 4.10.3.1 shows the timing for data holding and reading. Direct LAP input (K01/K00) Direct LAP internal signal Capture renewal flag CRNWF SWD0–3 reading SWD4–7 reading SWD8–11 reading Data holding Fig. 4.10.3.1 Timing for data holding and reading EPSON S1C63666 TECHNICAL MANUAL...
  • Page 79 SWRUN control. The chattering judgment is performed at the point where the key turns off, and a chattering less than 46.8–62.5 msec is removed. Therefore, more time is needed for an interval be- tween RUN and STOP key inputs. EPSON S1C63666 TECHNICAL MANUAL...
  • Page 80 Capture renewal flag CRNWF SWD0–3 reading SWD4–7 reading SWD8–11 reading Data holding 1 Hz interrupt factor flag ISW1 Lap data carry-up request flag LCURF Counter data Fig. 4.10.5.3 Timing for data holding and reading during direct LAP input EPSON S1C63666 TECHNICAL MANUAL...
  • Page 81 5. Both the RUN and LAP keys and the mask key are pressed at the same time if no other key is held down. (RUN and LAP functions are effective.) Simultaneous key input is referred to as two or more key inputs are sampled at the same falling edge of 1,024 Hz clock. EPSON S1C63666 TECHNICAL MANUAL...
  • Page 82 The respective interrupts can be masked separately through the interrupt mask registers (EISW10, EISW1). However, regardless of the setting of the interrupt mask registers, the interrupt factor flags are set to "1" by the overflow of their corresponding counters. EPSON S1C63666 TECHNICAL MANUAL...
  • Page 83 995 996 997 998 999 000 001 002 003 004 005 006 Capture buffer SWD0–3 reading SWD4–7 reading SWD8–11 reading CRNWF 1 Hz interrupt factor flag ISW1 LCURF Direct RUN interrupt Direct LAP interrupt 10 Hz interrupt 1 Hz interrupt Fig. 4.10.6.2 Timing chart for stopwatch timer EPSON S1C63666 TECHNICAL MANUAL...

  • Page 84: I/O Memory Of Stopwatch Timer

    Data (BCD) of the 1/10 sec column of the capture buffer can be read out. These 4 bits are read-only, and cannot be used for writing operations. At initial reset, the timer data is set to "0". Note: Be sure to data reading in the order of SWD0–3 → SWD4–7 → SWD8–11. EPSON S1C63666 TECHNICAL MANUAL...
  • Page 85 Also, in the STOP status the reset data is maintained. Since this reset does not affect the capture buffer, the capture buffer data in hold status is not cleared and is maintained. This bit is write-only, and is always "0" at reading. EPSON S1C63666 TECHNICAL MANUAL...
  • Page 86 The interrupt mask registers EIRUN, EILAP, EISW1 and EISW10 are used to separately select whether to mask the direct RUN, direct LAP, 1 Hz and 10 Hz interrupts. At initial reset, these registers are set to "0". EPSON S1C63666 TECHNICAL MANUAL...
  • Page 87 "1") is set or the RETI instruction is executed unless the interrupt factor flag is reset. Therefore, be sure to reset (write "1" to) the interrupt factor flag in the interrupt service routine before shifting to the interrupt enabled state. EPSON S1C63666 TECHNICAL MANUAL...

  • Page 88: Configuration Of Programmable Timer

    4.11.1 Configuration of programmable timer The S1C63666 has three 8-bit programmable timer systems (timer 0, timer 1 and timer 2) built-in. The timers are composed of 8-bit presettable down counters and they can be used as 8 bits × 3 channels or 16 bits ×...
  • Page 89 In addition to reloading the counter, this underflow signal controls the interrupt generation, pulse (TOUT signal) output and clock supplying to the serial interface. PTRUNx PTRSTx RLDx0–x7 Input clock PTDx7 PTDx6 PTDx5 PTDx4 PTDx3 PTDx2 PTDx1 PTDx0 Preset Reload & Interrupt generation Fig. 4.11.2.1 Basic operation timing of down counter EPSON S1C63666 TECHNICAL MANUAL...
  • Page 90 "1" is written, the rising edge is selected. The count down timing is shown in Figure 4.11.4.1. EVCNT PTRUN0 PLPOL K13 input Count data Fig. 4.11.4.1 Timing chart in event counter mode EPSON S1C63666 TECHNICAL MANUAL...
  • Page 91 Timer 1 operates with the timer 0 underflow signal as the count clock, so the clock and RUN/STOP control registers for timer 1 become invalid. The counter data in 16-bit mode must be read in the order below. PTD00–PTD03 → PTD04–PDT07 → PTD10–PTD13 → PTD14–PTD17 EPSON S1C63666 TECHNICAL MANUAL...

  • Page 92: Control Of Tout Output

    Figure 4.11.7.2 shows the output waveform of the TOUT signal. R02HIZ register Fix at "0" R02 register Fix at "1" PTOUT register "0" "1" "0" TOUT output Fig. 4.11.7.2 Output waveform of the TOUT signal EPSON S1C63666 TECHNICAL MANUAL...
  • Page 93 Oscillation frequency (OSC1/OSC3) bps: Transfer rate (00H can be set to RLD2x) Be aware that the maximum clock frequency for the serial interface is limited to 1 MHz when OSC3 is used as the clock source. EPSON S1C63666 TECHNICAL MANUAL...

  • Page 94: I/O Memory Of Programmable Timer

    Programmable timer 2 reload data (high-order 4 bits) RLD25 RLD24 PTD03 PTD03 PTD02 PTD01 PTD00 PTD02 FFCCH Programmable timer 0 data (low-order 4 bits) PTD01 PTD00 PTD07 PTD07 PTD06 PTD05 PTD04 PTD06 FFCDH Programmable timer 0 data (high-order 4 bits) PTD05 PTD04 EPSON S1C63666 TECHNICAL MANUAL...
  • Page 95 When the event counter mode is selected to timer 0, the setting of PTPS00 and PTPS01 becomes invalid. When timers 0 and 1 are used as a 16-bit timer, the setting of PTPS10 and PTPS11 becomes invalid. At initial reset, these registers are set to "0". EPSON S1C63666 TECHNICAL MANUAL...
  • Page 96 "1" is written, the rising edge is selected. Setting of this register is effective only when timer 0 is used in the event counter mode. At initial reset, this register is set to "0". EPSON S1C63666 TECHNICAL MANUAL...
  • Page 97 "0". In STOP status, the counter data is maintained until the counter is reset or is set in the next RUN status. When STOP status changes to RUN status, the data that has been maintained can be used for resuming the count. At initial reset, these registers are set to "0". EPSON S1C63666 TECHNICAL MANUAL...
  • Page 98 RETI instruction is executed unless the interrupt factor flag is reset. Therefore, be sure to reset (write "1" to) the interrupt factor flag in the interrupt service routine before shifting to the interrupt enabled state. At initial reset, these flags are set to "0". EPSON S1C63666 TECHNICAL MANUAL...
  • Page 99 . Be especially careful when using the OSC1 (low- speed clock) as the clock source of the programmable timer and the CPU is operating with the OSC3 (high-speed clock). EPSON S1C63666 TECHNICAL MANUAL...

  • Page 100: Configuration Of Serial Interface

    The synchronous clock for serial data input/output may be set by selecting by software any one of three types of master mode (internal clock mode: when the S1C63666 is to be the master for serial input/ output) and a type of slave mode (external clock mode: when the S1C63666 is to be the slave for serial input/output).

  • Page 101: Master Mode And Slave Mode Of Serial Interface

    4.12.3 Master mode and slave mode of serial interface The serial interface of the S1C63666 has two types of operation mode: master mode and slave mode. The master mode uses an internal clock as the synchronous clock for the built-in shift register, and outputs this internal clock from the SCLK (P12) terminal to control the external (slave side) serial device.
  • Page 102 Serial data output procedure and interrupt The S1C63666 serial interface is capable of outputting parallel data as serial data, in units of 8 bits. By setting the parallel data to the data registers SD0–SD3 (FF72H) and SD4–SD7 (FF73H) and writing "1"...
  • Page 103 Serial data input procedure and interrupt The S1C63666 serial interface is capable of inputting serial data as parallel data, in units of 8 bits. The serial data is input from the SIN (P10) terminal, synchronizes with the synchronous clock, and is sequentially read in the 8-bit shift register.
  • Page 104 CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Serial Interface) Timing chart The S1C63666 serial interface timing charts are shown in Figures 4.12.4.2 and 4.12.4.3. SCTRG (W) SCTRG (R) SCLK 8-bit shift register SOUT ISIF SRDY (Slave mode) (a) When SCPS = "1"...
  • Page 105 When "1" is written to the ESIF register, P10, P11, P12 and P13 function as SIN, SOUT, SCLK, SRDY, respectively. In the slave mode, the P13 terminal functions as SRDY output terminal, while in the master mode, it functions as the I/O port terminal. At initial reset, this register is set to "0". EPSON S1C63666 TECHNICAL MANUAL...
  • Page 106 Falling edge of SCLK _________ When "0" is written: Rising edge of SCLK Reading: Valid Select whether the fetching for the serial input data to registers (SD0–SD7) at the rising edge or falling edge of the synchronous signal. EPSON S1C63666 TECHNICAL MANUAL...
  • Page 107 Write data to be output in these registers. The register data is converted into serial data and output from the SOUT (P11) terminal; data bits set at "1" are output as high (V ) level and data bits set at "0" are output as low (V ) level. EPSON S1C63666 TECHNICAL MANUAL...
  • Page 108 "1") is set or the RETI instruction is executed unless the interrupt factor flag is reset. Therefore, be sure to reset (write "1" to) the interrupt factor flag in the interrupt service routine before shifting to the interrupt enabled state. EPSON S1C63666 TECHNICAL MANUAL...
  • Page 109 4.13 Sound Generator 4.13.1 Configuration of sound generator The S1C63666 has a built-in sound generator for generating buzzer signals. Hence, generated buzzer signals can be output from the BZ and BZ (BZ inverted output) terminals. Aside permitting the respective setting of the buzzer signal frequency and sound level to 8 stages, it permits the adding of a digital envelope by means of duty ratio control.
  • Page 110 (b) BZ output Fig. 4.13.3.1 Duty ratio of the buzzer signal waveform Note: When a digital envelope has been added to the buzzer signal, the BDTY0–BDTY2 settings will be invalid due to the control of the duty ratio. EPSON S1C63666 TECHNICAL MANUAL...
  • Page 111 BZFQ0–2 ENON ENRST ENRTM BZ signal Level 1 (Max.) duty ratio 8 (Min.) = 62.5 msec = 125 msec –4 –4 = 62.5 msec = 125 msec 02–07 12–17 Fig. 4.13.4.1 Timing chart for digital envelope EPSON S1C63666 TECHNICAL MANUAL...
  • Page 112 One-shot output is invalid during normal buzzer output (during BZE = "1"). Figure 4.13.5.1 shows timing chart for one-shot output. 256 Hz SHTPW BZSHT (W) BZSHT (R) BZSTP BZ output BZ output Fig. 4.13.5.1 Timing chart for one-shot output EPSON S1C63666 TECHNICAL MANUAL...
  • Page 113 Buzzer frequency (Hz) 4096.0 3276.8 2730.7 2340.6 2048.0 1638.4 1365.3 1170.3 Select the buzzer frequency from among the above 8 types that have divided the oscillation clock. At initial reset, this register is set to "0". EPSON S1C63666 TECHNICAL MANUAL...
  • Page 114 When "1" has been written in ENRTM, it becomes 125 msec (8 Hz) units and when "0" has been written, it becomes 62.5 msec (16 Hz) units. At initial reset, this register is set to "0". EPSON S1C63666 TECHNICAL MANUAL...
  • Page 115 BZE register. (2) The one-shot output is only valid when the normal buzzer output is off (BZE = "0") and will be invalid when the normal buzzer output is on (BZE = "1"). EPSON S1C63666 TECHNICAL MANUAL...
  • Page 116 4.14 Integer Multiplier 4.14.1 Configuration of integer multiplier The S1C63666 has a built-in unsigned-integer multiplier. This multiplier performs 8 bits × 8 bits of multiplication or 16 bits ÷ 8 bits of division and returns the results and three flag states.
  • Page 117 = 0AH. However, since the operation flags (NF/VF/ZF) are changed in each step, they cannot indicate the states according to the final operation results. Note: Make sure that the division results are correct using software as the hardware does not check. EPSON S1C63666 TECHNICAL MANUAL...
  • Page 118 ; Jump to error routine if VF = "1" %y, -4 ; Set DRL again %ba, [%y]+ [%x]+, %ba ; Store result (quotient) into RAM %ba, [%y]+ [%x]+, %ba ; Store result (remainder) into RAM EPSON S1C63666 TECHNICAL MANUAL...
  • Page 119 After the operation has finished, the low-order 8 bits of the product or the quotient are loaded to this register. However, if an overflow occurs in a division process, the quotient is not loaded and the low-order 8 bits of the dividend remains. At initial reset, this register is undefined. EPSON S1C63666 TECHNICAL MANUAL...
  • Page 120 CALMD until the operation result is set to the destination register DRH/DRL and the operation flags. While this operation is in process, do not read/write from/to the destination register DRH/DRL and do not read NF/VF/ZF. EPSON S1C63666 TECHNICAL MANUAL...

  • Page 121: Connection Terminals And Cr Oscillation

    Fig. 4.15.1.1 Configuration of R/f converter 4.15.2 Connection terminals and CR oscillation circuit The S1C63666 has the connecting terminals that can configure an R/f converter with a reference resis- tance and two sensors. Figure 4.15.2.1 shows the connection diagram of external elements.
  • Page 122 The "L" pulse width of the RFOUT output must be 10 µsec or more (when V = 3.0 V, R = 50 kΩ, SEN0/1 = 1000 pF). RFIN terminal 10 µsec or more RFOUT output Fig. 4.15.2.3 Oscillation waveform EPSON S1C63666 TECHNICAL MANUAL...
  • Page 123 RFRUNR register is set to "0", and the R/f converter circuit stops operation completely. The time base counter value should be saved into the RAM for R/f conversion of the sensor. Figure 4.15.3.1 shows a timing chart for the reference oscillation. EPSON S1C63666 TECHNICAL MANUAL...
  • Page 124 The time base counter is enabled at the falling edge of the first OSC1 clock. Then, it counts up by the rising edge of the OSC1 clock. Depending on the timing, the measurement counter may not count the CR oscillation clock at the time RFRUNS is set to "0". EPSON S1C63666 TECHNICAL MANUAL...
  • Page 125 (3) Read the measurement counter and process the m - n value by the program Fig. 4.15.3.3 Sequence of R/f conversion Note: Set the initial value of the measurement counter taking into account the measurable range and the overflow of counters. EPSON S1C63666 TECHNICAL MANUAL...

  • Page 126: Interrupt Function

    Interrupt request Fig. 4.15.4.2 Sensor oscillate completion interrupt OSC1 RFRUNS register Count-up Time base counter Measurement counter clock Measurement counter FFFFDH FFFFEH FFFFFH Oscillation by sensor resistance OVMC, IRFM Interrupt request Fig. 4.15.4.3 Measurement counter overflow interrupt EPSON S1C63666 TECHNICAL MANUAL...
  • Page 127 • When an interrupt occurs by the counter overflow, the same interrupt will occur if the overflow flag (OVMC or OVTBC) is not reset. Be sure to check and reset to "0" (writing "1") the overflow flag when the R/f converter interrupt occurs. EPSON S1C63666 TECHNICAL MANUAL...

  • Page 128: I/O Memory Of R/F Converter

    Interrupt factor flag (R/f converter reference oscillate completion) IRFM Reset Invalid Interrupt factor flag (R/f converter sensor oscillate completion) *1 Initial value at initial reset *3 Constantly "0" when being read *2 Not set in the circuit EPSON S1C63666 TECHNICAL MANUAL...
  • Page 129 "1" during R/f conversion and is set to "0" when R/f conversion is terminated. When "0" is written to RFRUNR during R/f conversion, R/f conversion is paused. At initial reset, this register is set to "0". EPSON S1C63666 TECHNICAL MANUAL...
  • Page 130 EIRFM and EIRFB are the interrupt mask registers for the sensor oscillate completion interrupt and the reference oscillate completion interrupt. The R/f converter interrupt is permitted when "1" is written to EIRFM and EIRFB. When "0" is written, interrupt is masked. At initial reset, these registers are set to "0". EPSON S1C63666 TECHNICAL MANUAL...

  • Page 131: Programming Notes

    (FF92H → FF93H → FF94H → FF95H → FF96H). Furthermore, an LD instruction should be used for writing data to the measurement counter and a read-modify-write instruction (AND, OR, ADD, SUB, etc.) cannot be used. EPSON S1C63666 TECHNICAL MANUAL...
  • Page 132 4.16 Analog Comparator 4.16.1 Configuration of analog comparator The S1C63666 has a built-in MOS input analog comparator. Two differential input terminals (inverted input terminal CMPM0 and non-inverted input terminal CMPP0) are provided for the analog comparator. Figure 4.16.1.1 shows the configuration of the analog comparator.
  • Page 133 (2) After the analog comparator is turned on, a maximum of 3 msec is necessary until the output stabi- lizes. Consequently, allow an adequate waiting time after turning the analog comparator on, before reading the comparison result. EPSON S1C63666 TECHNICAL MANUAL...

  • Page 134: Mask Option

    4.17.1 Configuration of SVD circuit The S1C63666 has a built-in SVD (supply voltage detection) circuit, so that the software can find when the source voltage lowers. It is possible to check an external voltage drop, other than the supply voltage, by mask option.

  • Page 135: Svd Operation

    1. Set SVDON to "1" 2. Maintain for 500 µsec minimum 3. Set SVDON to "0" 4. Read SVDDT When the SVD circuit is on, the IC draws a large current, so keep the SVD circuit off unless it is. EPSON S1C63666 TECHNICAL MANUAL...

  • Page 136: I/O Memory Of Svd Circuit

    SVD detection result, follow the programming sequence below. 1. Set SVDON to "1" 2. Maintain for 500 µsec minimum 3. Set SVDON to "0" 4. Read SVDDT (2) The SVD circuit should normally be turned off because SVD operation increase current consumption. EPSON S1C63666 TECHNICAL MANUAL...

  • Page 137: Interrupt And Halt

    NMI are masked and interrupts cannot be accepted until the other one is set. <HALT> The S1C63666 has HALT functions that considerably reduce the current consumption when it is not necessary. The CPU enters HALT status when the HALT instruction is executed.

  • Page 138: Interrupt Factor

    Interrupt mask register EIK1 KCP12 Input comparison register SIK12 Interrupt selection register KCP13 SIK13 EIT3 EIT2 EIT1 EIT0 IRUN EIRUN ILAP EILAP ISW1 EISW1 ISW10 EISW10 IRFM EIRFM IRFB EIRFB Fig. 4.18.1 Configuration of the interrupt circuit EPSON S1C63666 TECHNICAL MANUAL...
  • Page 139 "1") is set or the RETI instruction is executed unless the interrupt factor flag is reset. Therefore, be sure to reset (write "1" to) the interrupt factor flag in the interrupt service routine before shifting to the interrupt enabled state. EPSON S1C63666 TECHNICAL MANUAL...

  • Page 140: Interrupt Vector

    0102H R/f converter 0104H Programmable timer 0106H Serial interface 0108H K00–K03 input 010AH K10–K13 input 010CH Clock timer 010EH Stopwatch timer The four low-order bits of the program counter are indirectly addressed through the interrupt request. EPSON S1C63666 TECHNICAL MANUAL...

  • Page 141: I/O Memory Of Interrupt

    ISIF ∗3 ∗2 – Unused FFF2H ∗3 ∗2 – Unused ISIF Reset Invalid Interrupt factor flag (Serial I/F) *1 Initial value at initial reset *2 Not set in the circuit *3 Constantly "0" when being read EPSON S1C63666 TECHNICAL MANUAL...
  • Page 142 EIRUN, EILAP, EISW1, EISW10: Interrupt mask registers (FFE6H) IRUN, ILAP, ISW1, ISW10: Interrupt factor flags (FFF6H) Refer to Section 4.10, "Stopwatch Timer". EIRFB, EIRFM: Interrupt mask registers (FFE7H•D1, D0) IRFB, IRFM: Interrupt factor flags (FFF7H•D1, D0) Refer to Section 4.15, "R/f Converter". EPSON S1C63666 TECHNICAL MANUAL...
  • Page 143 SP1 and SP2 must be set as a pair. When one of them is set, all the interrupts including NMI are masked and interrupts cannot be accepted until the other one is set. EPSON S1C63666 TECHNICAL MANUAL...

  • Page 144: Notes For Low Current Consumption

    UMMARY OF OTES 5.1 Notes for Low Current Consumption The S1C63666 contains control registers for each of the circuits so that current consumption can be reduced. These control registers reduce the current consumption through programs that operate the circuits at the minimum levels.

  • Page 145: Summary Of Notes By Function

    0000H to 00FFH. Therefore, pay attention to the SP1 value because it may be set to 0200H or more exceeding the 4-bit/16-bit accessible range in the S1C63666 or it may be set to 00FFH or less. Memory accesses except for stack operations by SP1 are 4-bit data access. After initial reset, all the interrupts including NMI are masked until both the stack pointers SP1 and SP2 are set by software.
  • Page 146 (2) The programmable timer actually enters RUN/STOP status in synchronization with the falling edge of the input clock after writing to the PTRUNx register. Consequently, when "0" is written to the PTRUNx register, the timer enters STOP status at the point where the counter is decremented (-1). EPSON S1C63666 TECHNICAL MANUAL...
  • Page 147 SD0–SD7. (4) Be aware that the maximum clock frequency for the serial interface is limited to 1 MHz when OSC3 is used as the clock source of the programmable timer or in the slave mode. EPSON S1C63666 TECHNICAL MANUAL...
  • Page 148 SP1 and SP2 must be set as a pair. When one of them is set, all the interrupts including NMI are masked and interrupts cannot be accepted until the other one is set. EPSON S1C63666 TECHNICAL MANUAL...

  • Page 149: Precautions On Mounting

    In particular, the V –V voltages affect the display quality. Do not connect anything to the V –V terminals when the LCD driver is not used. EPSON S1C63666 TECHNICAL MANUAL...
  • Page 150 (1) Design the product and implement the IC on the board so that it is shielded from visible radiation in actual use. (2) The inspection process of the product needs an environment that shields the IC from visible radiation. (3) As well as the face of the IC, shield the back and side too. EPSON S1C63666 TECHNICAL MANUAL...

  • Page 151: Lcd Panel

    Resistor for OSC3 CR oscillation 30 kΩ (2 MHz) 0.2 µF –C Capacitor 3.3 µF Capacitor 0.1 µF RESET terminal capacitor 100 Ω Protective resistor Note: The above table is simply an example, and is not guaranteed to work. EPSON S1C63666 TECHNICAL MANUAL...

  • Page 152: Absolute Maximum Rating

    -0.05V SEG0–63 µA (during LCD output) +0.05V µA Segment output current =0.9·V SEG0–63 -300 µA (during DC output) =0.1·V Ω R/f converter transistor ON =0.1V =1.5V RFINTr Ω resistance =0.1V =1.5V REFTr Ω =0.1V =1.5V SEN0Tr SEN1Tr EPSON S1C63666 TECHNICAL MANUAL...

  • Page 153: Analog Circuit Characteristics And Power

    No panel load. When SVD circuit, R/f converter and analog comparator are in OFF status. ∗2 VDC0=VDC1="0", OSCC="0" ∗3 VDC2=VDC3="0" ∗4 VDC2=VDC3="1" ∗5 VDC0=VDC1="1", OSCC="1", VDC2=VDC3="0" ∗6 Do not input a voltage exceeding the power supply voltage range (V –V ) to the SVD terminal. EPSON S1C63666 TECHNICAL MANUAL...

  • Page 154: Oscillation Characteristics

    Unless otherwise specified: =3.0V, V =0V, R =30kΩ (2MHz), Ta=-20 to 70°C Item Symbol Condition Min. Typ. Max. Unit Oscillation frequency dispersion OSC3 Oscillation start voltage Vsta Oscillation start time =2.4 to 3.6V Oscillation stop voltage Vstp EPSON S1C63666 TECHNICAL MANUAL...
  • Page 155 The oscillation characteristics change depending on the conditions (components used, board pattern, etc.). Use the following characteristics as reference values and evaluate the characteristics on the actual product. 10000 = 2.4–3.6 V Ta = 25°C Typ. value 1000 Resistor value for CR oscillation R [kΩ] EPSON S1C63666 TECHNICAL MANUAL...

  • Page 156: Serial Interface Ac Characteristics

    Transmitting data output delay time Receiving data input set-up time Receiving data input hold time Note that the maximum clock frequency is limited to 1 MHz. <Master mode> SCLK OUT SOUT <Slave mode> SCLK IN SOUT EPSON S1C63666 TECHNICAL MANUAL...
  • Page 157 Capacitance [pF] (external RFIN) R/f converter oscillation frequency - resistance characteristic Ta = -20 ~ 70°C, C = 1000 pF, V = 3.0 V 1,000,000 100,000 +20% 10,000 -20% 1,000 Typ. 1,000 Resistance [kΩ] (external SEN0, SEN1 or REF) EPSON S1C63666 TECHNICAL MANUAL...

  • Page 158: Plastic Package

    CHAPTER 8: PACKAGE CHAPTER ACKAGE 8.1 Plastic Package QFP20-144pin (Unit: mm) ±0.4 ±0.1 INDEX +0.1 –0.05 +0.05 0.125 –0.025 0° 10° ±0.2 The dimensions are subject to change without notice. EPSON S1C63666 TECHNICAL MANUAL...

  • Page 159: Ceramic Package For Test Samples

    CHAPTER 8: PACKAGE 8.2 Ceramic Package for Test Samples QFP17-144pin (Unit: mm) ±0.25 22.00 ±0.19 19.20 0.50 0.20 ±0.20 0.50 EPSON S1C63666 TECHNICAL MANUAL...

  • Page 160: Diagram Of Pad Layout

    CHAPTER 9: PAD LAYOUT CHAPTER AYOUT 9.1 Diagram of Pad Layout Die No. (0, 0) 4.75 mm Chip thickness: 400 µm Pad opening: 85 µm EPSON S1C63666 TECHNICAL MANUAL...

  • Page 161: Pad Coordinates

    -2,341 SEG29 2,241 1,340 SEG40 -2,241 1,180 -2,341 SEG30 2,241 1,460 SEG41 -2,241 1,060 -2,341 SEG31 2,241 1,580 SEG42 -2,241 -2,341 N.C. 2,241 1,754 SEG43 -2,241 -2,341 N.C. 2,241 1,925 SEG44 -2,241 -2,341 N.C. 2,241 2,096 EPSON S1C63666 TECHNICAL MANUAL...
  • Page 162 This description of the S1C63 Family Peripheral Circuit Board (S5U1C63000P1) provided in this docu- ment assumes that circuit data for the S1C63666 has already been downloaded to the board. For informa- tion on downloading various circuit data and on common board specifications, please see the S5U1C63000P Manual (S1C63 Family Peripheral Circuit Board) included with the product.
  • Page 163 The oscillation frequency can be adjusted in the range of approx. 100 kHz to 8 MHz. Note that the actual IC does not operate with all of these frequencies; consult the technical manual for the S1C63666 to select the appropriate operating frequency. Not used...
  • Page 164 APPENDIX S5U1C63000P1 MANUAL (PERIPHERAL CIRCUIT BOARD FOR S1C63666) (8) R/f converter monitor pins and external part connecting socket These monitor pins are used to check the R/f converter operation. The socket is used to connect external resistors and a capacitor for R/f conversion.
  • Page 165 APPENDIX S5U1C63000P1 MANUAL (PERIPHERAL CIRCUIT BOARD FOR S1C63666) A.2 Connecting to the Target System This section explains how to connect the S5U1C63000P1 to the target system. To connect this board (S5U1C63000P1) to the target system, use the I/O connecting cables supplied with the board (80-pin/40-pin ×...
  • Page 166 APPENDIX S5U1C63000P1 MANUAL (PERIPHERAL CIRCUIT BOARD FOR S1C63666) Table A.2.1 I/O connector pin assignment 40-pin CN1-1 connector 40-pin CN1-2 connector 50-pin CN2-1 connector 50-pin CN2-2 connector Pin name Pin name Pin name Pin name (= 3.3 V) (= 3.3 V) (= 3.3 V)
  • Page 167 The pull-down resistance values on this board are set to 220 kΩ which differ from those for the actual IC. For the resistance values on the actual IC, refer to the technical manual for the S1C63666. Note that when using pull-down resistors to pull the input pins low, the input pins may require a certain period to reach a valid low level.
  • Page 168 <Access to undefined address space> If any undefined space in the S1C63666's internal ROM/RAM or I/O is accessed for data read or write operations, the read/written value is indeterminate. Additionally, it is important to remain aware that indeterminate state differs between this board and the actual IC.
  • Page 169 - Although this board contains VDC0–VDC3 registers, it does not actually exercise power supply control by these registers. Be sure to refer to the technical manual for the S1C63666 when setting the correct voltage. Also, when switching the control voltages, consult the technical manual to determine the appropriate wait time to be inserted.
  • Page 170 Riesstrasse 15 Hi- Tech Park, Shenzhen 80992 Munich, GERMANY Phone: +86-755-2699-3828 Fax: +86-755-2699-3838 Phone: +49-89-14005-0 Fax: +49-89-14005-110 EPSON TAIWAN TECHNOLOGY & TRADING LTD. DÜSSELDORF BRANCH OFFICE 14F, No. 7, Song Ren Road Altstadtstrasse 176 Taipei 110 51379 Leverkusen, GERMANY Phone: +886-2-8786-6688...
  • Page 171 S1C63666 Technical Manual SEMICONDUCTOR OPERATIONS DIVISION EPSON Electronic Devices Website http://www.epson.jp/device/semicon_e Document code: 404519503 First issue November, 2001 Printed March, 2007 in Japan...

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