Table of Contents
Advertisement
Register name
Address
Bit
Port input 0–3,
0040290
D7
high-speed
(B)
D6
DMA Ch. 0/1,
D5
16-bit timer 0
D4
IDMA request
D3
register
D2
D1
D0
16-bit timer 1–4
0040291
D7
IDMA request
(B)
D6
register
D5
D4
D3
D2
D1
D0
16-bit timer 5,
0040292
D7
8-bit timer,
(B)
D6
serial I/F Ch.0
D5
IDMA request
D4
register
D3
D2
D1
D0
Serial I/F Ch.1,
0040293
D7
A/D,
(B)
D6
port input 4–7
D5
IDMA request
D4
register
D3
D2
D1
D0
Port input 0–3,
0040294
D7
high-speed
(B)
D6
DMA Ch. 0/1,
D5
16-bit timer 0
D4
IDMA enable
D3
register
D2
D1
D0
16-bit timer 1–4
0040295
D7
IDMA enable
(B)
D6
register
D5
D4
D3
D2
D1
D0
16-bit timer 5,
0040296
D7
8-bit timer,
(B)
D6
serial I/F Ch.0
D5
IDMA enable
D4
register
D3
D2
D1
D0
Serial I/F Ch.1,
0040297
D7
A/D,
(B)
D6
port input 4–7
D5
IDMA enable
D4
register
D3
D2
D1
D0
S1C33210 FUNCTION PART
Name
Function
R16TC0
16-bit timer 0 comparison A
R16TU0
16-bit timer 0 comparison B
RHDM1
High-speed DMA Ch.1
RHDM0
High-speed DMA Ch.0
RP3
Port input 3
RP2
Port input 2
RP1
Port input 1
RP0
Port input 0
R16TC4
16-bit timer 4 comparison A
R16TU4
16-bit timer 4 comparison B
R16TC3
16-bit timer 3 comparison A
R16TU3
16-bit timer 3 comparison B
R16TC2
16-bit timer 2 comparison A
R16TU2
16-bit timer 2 comparison B
R16TC1
16-bit timer 1 comparison A
R16TU1
16-bit timer 1 comparison B
RSTX0
SIF Ch.0 transmit buffer empty
RSRX0
SIF Ch.0 receive buffer full
R8TU3
8-bit timer 3 underflow
R8TU2
8-bit timer 2 underflow
R8TU1
8-bit timer 1 underflow
R8TU0
8-bit timer 0 underflow
R16TC5
16-bit timer 5 comparison A
R16TU5
16-bit timer 5 comparison B
RP7
Port input 7
RP6
Port input 6
RP5
Port input 5
RP4
Port input 4
–
reserved
RADE
A/D converter
RSTX1
SIF Ch.1 transmit buffer empty
RSRX1
SIF Ch.1 receive buffer full
DE16TC0
16-bit timer 0 comparison A
DE16TU0
16-bit timer 0 comparison B
DEHDM1
High-speed DMA Ch.1
DEHDM0
High-speed DMA Ch.0
DEP3
Port input 3
DEP2
Port input 2
DEP1
Port input 1
DEP0
Port input 0
DE16TC4
16-bit timer 4 comparison A
DE16TU4
16-bit timer 4 comparison B
DE16TC3
16-bit timer 3 comparison A
DE16TU3
16-bit timer 3 comparison B
DE16TC2
16-bit timer 2 comparison A
DE16TU2
16-bit timer 2 comparison B
DE16TC1
16-bit timer 1 comparison A
DE16TU1
16-bit timer 1 comparison B
DESTX0
SIF Ch.0 transmit buffer empty
DESRX0
SIF Ch.0 receive buffer full
DE8TU3
8-bit timer 3 underflow
DE8TU2
8-bit timer 2 underflow
DE8TU1
8-bit timer 1 underflow
DE8TU0
8-bit timer 0 underflow
DE16TC5
16-bit timer 5 comparison A
DE16TU5
16-bit timer 5 comparison B
DEP7
Port input 7
DEP6
Port input 6
DEP5
Port input 5
DEP4
Port input 4
–
reserved
DEADE
A/D converter
DESTX1
SIF Ch.1 transmit buffer empty
DESRX1
SIF Ch.1 receive buffer full
Setting
1 IDMA
0 Interrupt
request
request
1 IDMA
0 Interrupt
request
request
1 IDMA
0 Interrupt
request
request
1 IDMA
0 Interrupt
request
request
–
1 IDMA
0 Interrupt
request
request
1 IDMA
0 IDMA
enabled
disabled
1 IDMA
0 IDMA
enabled
disabled
1 IDMA
0 IDMA
enabled
disabled
1 IDMA
0 IDMA
enabled
disabled
–
1 IDMA
0 IDMA
enabled
disabled
EPSON
APPENDIX: I/O MAP
Init. R/W
Remarks
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
–
–
0 when being read.
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
–
–
0 when being read.
0
R/W
0
R/W
0
R/W
B-APPENDIX-17
Advertisement
Table of Contents
