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III PERIPHERAL BLOCK: 16-BIT PROGRAMMABLE TIMERS
Register name
Address
Bit
16-bit timer 2
0048192
DF
comparison
(HW)
DE
data B set-up
DD
register
DC
DB
DA
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
16-bit timer 2
0048194
DF
counter data
(HW)
DE
register
DD
DC
DB
DA
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
16-bit timer 2
0048196
D7
control register
(B)
D6
D5
D4
D3
D2
D1
D0
16-bit timer 3
0048198
DF
comparison
(HW)
DE
data A set-up
DD
register
DC
DB
DA
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
16-bit timer 3
004819A
DF
comparison
(HW)
DE
data B set-up
DD
register
DC
DB
DA
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
B-III-4-16
Name
Function
CR2B15
16-bit timer 2 comparison data B
CR2B14
CR2B15 = MSB
CR2B13
CR2B0 = LSB
CR2B12
CR2B11
CR2B10
CR2B9
CR2B8
CR2B7
CR2B6
CR2B5
CR2B4
CR2B3
CR2B2
CR2B1
CR2B0
TC215
16-bit timer 2 counter data
TC214
TC215 = MSB
TC213
TC20 = LSB
TC212
TC211
TC210
TC29
TC28
TC27
TC26
TC25
TC24
TC23
TC22
TC21
TC20
–
reserved
SELFM2
16-bit timer 2 fine mode selection
SELCRB2
16-bit timer 2 comparison buffer
OUTINV2
16-bit timer 2 output inversion
CKSL2
16-bit timer 2 input clock selection
PTM2
16-bit timer 2 clock output control
PRESET2
16-bit timer 2 reset
PRUN2
16-bit timer 2 Run/Stop control
CR3A15
16-bit timer 3 comparison data A
CR3A14
CR3A15 = MSB
CR3A13
CR3A0 = LSB
CR3A12
CR3A11
CR3A10
CR3A9
CR3A8
CR3A7
CR3A6
CR3A5
CR3A4
CR3A3
CR3A2
CR3A1
CR3A0
CR3B15
16-bit timer 3 comparison data B
CR3B14
CR3B15 = MSB
CR3B13
CR3B0 = LSB
CR3B12
CR3B11
CR3B10
CR3B9
CR3B8
CR3B7
CR3B6
CR3B5
CR3B4
CR3B3
CR3B2
CR3B1
CR3B0
Setting
0 to 65535
0 to 65535
–
1 Fine mode
0 Normal
1 Enabled
0 Disabled
1 Invert
0 Normal
1 External clock 0 Internal clock
1 On
0 Off
1 Reset
0 Invalid
1 Run
0 Stop
0 to 65535
0 to 65535
EPSON
Init. R/W
Remarks
X
R/W
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
R
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
–
0 when being read.
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
W
0 when being read.
0
R/W
X
R/W
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
R/W
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
S1C33210 FUNCTION PART
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