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Register name
Address
Bit
HDLC residue
0200332
D15–8
code register
(HW)
D7
D6
D5
D4
D3
D2
D1
D0
HDLC transmit
0200334
D15–8
status register
(HW)
D7
D6
D5–1
D0
HDLC monitor
0200336
D15–8
register
(HW)
D7
D6
D5
D4
D3–0
CKD3–CKD0:
Clock frequency divider (D[3:0]) / Communications block clock frequency divider register
(0x0200004)
These bits specify the divisor for deriving the communications block clock (SCK) signal from the PERICLK clock
signal.
CKD3 CKD2 CKD1 CKD0
MCRS1–MCRS0:
Communications macro select (D[1:0]) / Communications macro select register (0x200000)
These bits, together with the MSEL external pin input, specify the communications mode and thus configures the
I/O pin the I/O signals to match the target mobile device.
U_OUTCNT(MSEL)
S1C33210 FUNCTION PART
III PERIPHERAL BLOCK: MONITORED MOBILE ACCESS INTERFACES
Name
Function
–
–
RCODE7
HDLC residue code
RCODE6
RCODE5
RCODE4
RCODE3
RCODE2
RCODE1
RCODE0
–
–
TXUE
HDLC Tx underrun/EOM
TXBRDY
HDLC transmit buffer ready
–
–
TXUDR
HDLC Tx underrun
–
–
ESINT
HDLC E/S INT monitored
SPINT
HDLC Sp INT monitored
RXINT
HDLC Rx INT monitored
TXINT
HDLC Tx INT monitored
–
–
Table 10.12 Communications Block Clock (SCK) Frequency
1
1
1
1
1
1
1
0
1
1
0
1
1
1
0
0
1
0
1
1
1
0
1
0
1
0
0
1
1
0
0
0
0
1
1
1
0
1
1
0
0
1
0
1
0
1
0
0
0
0
1
1
0
0
1
0
0
0
0
1
0
0
0
0
Table 10.13 Communications Modes
MCRS1 MCRS0
1
1
1
1
1
0
1
0
0
X
Setting
–
RCODE[7:0]
Effective bits
11111110
11111100
11111000
11110000
11100000
11000000
10000000
–
1 Yes
0 No
1 not Full
0 Full
–
1 Underrun
0 No underrun
–
1 Request pending 0 No interrupts
1 Request pending 0 No interrupts
1 Request pending 0 No interrupts
1 Request pending 0 No interrupts
–
SCK Clock Frequency Divider
Settings
fout/16
fout/15
fout/14
fout/13
fout/12
fout/11
fout/10
fout/9
fout/8
fout/7
fout/6
fout/5
fout/4
fout/3
fout/2
fout/2
fout = PERICLK output frequency
Communications Mode
1
PHS communications
0
PDC communications
1
HDLC communications
0
UART communications
X
Serial IF Ch. 3 (asynchronous)
EPSON
Init. R/W
Remarks
–
–
0 when being read.
X
R
Only valid when
7
X
RESID = 1
6
X
5
X
4
X
3
X
2
X
1
X
–
–
0 when being read.
X
R
X
R
–
–
0 when being read.
X
R
–
–
0 when being read.
X
R
X
R
X
R
X
R
–
–
0 when being read.
B-III-10-25
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