Epson S1C33210 Technical Manual page 12

TABLE OF CONTENTS
IV ANALOG BLOCK
IV-1 INTRODUCTION............................................................................................ B-IV-1-1
IV-2 A/D CONVERTER.......................................................................................... B-IV-2-1
Features and Structure of A/D Converter ................................................................................................B-IV-2-1
I/O Pins of A/D Converter ..............................................................................................................................B-IV-2-2
Setting A/D Converter .....................................................................................................................................B-IV-2-3
Control and Operation of A/D Conversion...............................................................................................B-IV-2-5
A/D Converter Interrupt and DMA...............................................................................................................B-IV-2-7
I/O Memory of A/D Converter.......................................................................................................................B-IV-2-9
Programming Notes.......................................................................................................................................B-IV-2-15
V DMA BLOCK
V-1 INTRODUCTION............................................................................................. B-V-1-1
V-2 HSDMA (HIGH-SPEED DMA) .......................................................................... B-V-2-1
Functional Outline of HSDMA........................................................................................................................B-V-2-1
I/O Pins of HSDMA............................................................................................................................................B-V-2-2
Programming Control Information ................................................................................................................B-V-2-3
Setting the Registers in Dual-Address Mode............................................................................B-V-2-3
Setting the Registers in Single-Address Mode ........................................................................B-V-2-6
Enabling/Disabling DMA Transfer.................................................................................................................B-V-2-7
Trigger Factor.......................................................................................................................................................B-V-2-8
Operation of HSDMA.........................................................................................................................................B-V-2-9
Operation in Dual-Address Mode ..................................................................................................B-V-2-9
Operation in Single-Address Mode............................................................................................B-V-2-12
Timing Chart........................................................................................................................................B-V-2-13
Interrupt Function of HSDMA......................................................................................................................B-V-2-15
I/O Memory of HSDMA..................................................................................................................................B-V-2-17
Programming Notes........................................................................................................................................B-V-2-36
V-3 IDMA (Intelligent DMA) .................................................................................. B-V-3-1
Functional Outline of IDMA.............................................................................................................................B-V-3-1
Programming Control Information ................................................................................................................B-V-3-1
IDMA Invocation..................................................................................................................................................B-V-3-5
Operation of IDMA..............................................................................................................................................B-V-3-8
Linking .................................................................................................................................................................B-V-3-12
Interrupt Function of Intelligent DMA........................................................................................................B-V-3-13
I/O Memory of Intelligent DMA ...................................................................................................................B-V-3-14
Programming Notes........................................................................................................................................B-V-3-17
APPENDIX I/O MAP ................................................................................... B-Appendix-1
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