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I/O Memory of A/D Converter
Table 2.6 shows the control bits of the A/D converter.
For details on the I/O memory of the prescaler used to set clocks, refer to "Prescaler". For details on the I/O memory
of the programmable timers used for a trigger, refer to "8-Bit Programmable Timers" or "16-Bit Programmable
Timers".
Register name
Address
Bit
A/D conversion
0040240
D7
result (low-
(B)
D6
order) register
D5
D4
D3
D2
D1
D0
A/D conversion
0040241
D7–2
result (high-
(B)
D1
order) register
D0
A/D trigger
0040242
D7–6
register
(B)
D5
D4
D3
D2
D1
D0
A/D channel
0040243
D7–6
register
(B)
D5
D4
D3
D2
D1
D0
A/D enable
0040244
D7–4
register
(B)
D3
D2
D1
D0
A/D sampling
0040245
D7–2
register
(B)
D1
D0
S1C33210 FUNCTION PART
Table 2.6 Control Bits of A/D Converter
Name
Function
ADD7
A/D converted data
ADD6
(low-order 8 bits)
ADD5
ADD0 = LSB
ADD4
ADD3
ADD2
ADD1
ADD0
–
–
ADD9
A/D converted data
ADD8
(high-order 2 bits) ADD9 = MSB
–
–
MS
A/D conversion mode selection
TS1
A/D conversion trigger selection
TS0
CH2
A/D conversion channel status
CH1
CH0
–
–
CE2
A/D converter
CE1
end channel selection
CE0
CS2
A/D converter
CS1
start channel selection
CS0
–
–
ADF
Conversion-complete flag
ADE
A/D enable
ADST
A/D conversion control/status
OWE
Overwrite error flag
–
–
ST1
Input signal sampling time setup
ST0
IV ANALOG BLOCK: A/D CONVERTER
Setting
0x0 to 0x3FF
(low-order 8 bits)
–
0x0 to 0x3FF
(high-order 2 bits)
–
1 Continuous 0 Normal
TS[1:0]
Trigger
1
1
#ADTRG pin
1
0
8-bit timer 0
0
1
16-bit timer 0
0
0
Software
CH[2:0]
Channel
0
1
1
0
1
0
0
0
1
0
0
0
–
CE[2:0]
End channel
0
1
1
0
1
0
0
0
1
0
0
0
CS[2:0]
Start channel
0
1
1
0
1
0
0
0
1
0
0
0
–
1 Completed 0 Run/Standby
1 Enabled
0 Disabled
1 Start/Run
0 Stop
1 Error
0 Normal
–
ST[1:0]
Sampring time
1
1
9 clocks
1
0
7 clocks
0
1
5 clocks
0
0
3 clocks
EPSON
Init. R/W
Remarks
0
R
0
0
0
0
0
0
0
–
–
0 when being read.
0
R
0
–
–
0 when being read.
0
R/W
0
R/W
0
0
R
Always set CH2 to 0
AD3
0
AD2
0
AD1
AD0
–
–
0 when being read.
0
R/W
Always set CE2 to 0.
AD3
0
AD2
0
AD1
AD0
0
R/W
Always set CS2 to 0.
AD3
0
AD2
0
AD1
AD0
–
–
0 when being read.
0
R
Reset when ADD is read.
0
R/W
0
R/W
0
R/W
Reset by writing 0.
–
–
0 when being read.
1
R/W
Use with 9 clocks.
1
B-IV-2-9
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