Table of Contents
Advertisement
4 PERIPHERAL CIRCUITS
Register name
Address
Bit
High-speed
0048248
DF
DMA Ch.2
(HW)
DE
low-order
DD
destination
DC
address set-up
DB
register
DA
D9
Note:
A8
D) Dual address
D7
mode
D6
S) Single
D5
address
D4
mode
D3
D2
D1
D0
High-speed
004824A
DF
DMA Ch.2
(HW)
DE
high-order
destination
address set-up
register
DD
DC
Note:
D) Dual address
mode
S) Single
DB
address
DA
mode
D9
A8
D7
D6
D5
D4
D3
D2
D1
D0
High-speed
004824C
DF–1
DMA Ch.2
(HW)
enable register
D0
High-speed
004824E
DF–1
DMA Ch.2
(HW)
trigger flag
D0
register
A-54
Name
Function
D2ADRL15
D) Ch.2 destination address[15:0]
D2ADRL14
S) Invalid
D2ADRL13
D2ADRL12
D2ADRL11
D2ADRL10
D2ADRL9
D2ADRL8
D2ADRL7
D2ADRL6
D2ADRL5
D2ADRL4
D2ADRL3
D2ADRL2
D2ADRL1
D2ADRL0
D2MOD1
Ch.2 transfer mode
D2MOD0
D2IN1
D) Ch.2 destination address
D2IN0
control
S) Invalid
D2ADRH11
D) Ch.2 destination
D2ADRH10
address[27:16]
D2ADRH9
S) Invalid
D2ADRH8
D2ADRH7
D2ADRH6
D2ADRH5
D2ADRH4
D2ADRH3
D2ADRH2
D2ADRH1
D2ADRH0
–
reserved
HS2_EN
Ch.2 enable
–
reserved
HS2_TF
Ch.2 trigger flag clear (writing)
Ch.2 trigger flag status (reading)
Setting
D2MOD[1:0]
Mode
1
1
Invalid
1
0
Block
0
1
Successive
0
0
Single
D2IN[1:0]
Inc/dec
1
1
Inc.(no init)
1
0
Inc.(init)
0
1
Dec.(no init)
0
0
Fixed
–
1 Enable
0 Disable
–
1 Clear
0 No operation
1 Set
0 Cleared
EPSON
Init. R/W
Remarks
X
R/W
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
R/W
0
0
R/W
0
X
R/W
X
X
X
X
X
X
X
X
X
X
X
–
–
Undefined in read.
0
R/W
–
–
Undefined in read.
0
R/W
S1C33210 PRODUCT PART
Advertisement
Table of Contents
