Epson S1C33210 Technical Manual page 473

Register name Address Bit
High-speed 004822A DF
DMA Ch.0 (HW) DE
high-order
destination
address set-up
register DD
DC
Note:
D) Dual address
mode
S) Single
DB
address
DA
mode
D9
A8
D7
D6
D5
D4
D3
D2
D1
D0
High-speed 004822C DF–1
DMA Ch.0 (HW)
enable register D0
High-speed 004822E DF–1
DMA Ch.0 (HW)
trigger flag D0
register
High-speed 0048230 DF
DMA Ch.1 (HW) DE
transfer DD
counter DC
register DB
DA
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
High-speed 0048232 DF
DMA Ch.1 (HW) DE
control register
DD–8
Note:
D7
D) Dual address
D6
mode
D5
S) Single
D4
address
D3
mode
D2
D1
D0
S1C33210 FUNCTION PART
Name Function
D0MOD1 Ch.0 transfer mode
D0MOD0
D0IN1 D) Ch.0 destination address
D0IN0 control
S) Invalid
D0ADRH11 D) Ch.0 destination
D0ADRH10 address[27:16]
D0ADRH9 S) Invalid
D0ADRH8
D0ADRH7
D0ADRH6
D0ADRH5
D0ADRH4
D0ADRH3
D0ADRH2
D0ADRH1
D0ADRH0
– reserved
HS0_EN Ch.0 enable
– reserved
HS0_TF Ch.0 trigger flag clear (writing)
Ch.0 trigger flag status (reading)
TC1_L7 Ch.1 transfer counter[7:0]
TC1_L6 (block transfer mode)
TC1_L5
TC1_L4 Ch.1 transfer counter[15:8]
TC1_L3 (single/successive transfer mode)
TC1_L2
TC1_L1
TC1_L0
BLKLEN17 Ch.1 block length
BLKLEN16 (block transfer mode)
BLKLEN15
BLKLEN14 Ch.1 transfer counter[7:0]
BLKLEN13 (single/successive transfer mode)
BLKLEN12
BLKLEN11
BLKLEN10
DUALM1 Ch.1 address mode selection
D1DIR D) Invalid
S) Ch.1 transfer direction control
– reserved
TC1_H7 Ch.1 transfer counter[15:8]
TC1_H6 (block transfer mode)
TC1_H5
TC1_H4 Ch.1 transfer counter[23:16]
TC1_H3 (single/successive transfer mode)
TC1_H2
TC1_H1
TC1_H0
V DMA BLOCK: HSDMA (High-Speed DMA)
Setting
D0MOD[1:0] Mode
1 1 Invalid
1 0 Block
0 1 Successive
0 0 Single
D0IN[1:0] Inc/dec
1 1 Inc.(no init)
1 0 Inc.(init)
0 1 Dec.(no init)
0 0 Fixed
–
1 Enable 0 Disable
–
1 Clear 0 No operation
1 Set 0 Cleared
1 Dual addr 0 Single addr
–
1 Memory WR 0 Memory RD
–
EPSON
Init. R/W Remarks
0 R/W
0
0 R/W
0
X R/W
X
X
X
X
X
X
X
X
X
X
X
– – Undefined in read.
0 R/W
– – Undefined in read.
0 R/W
X R/W
X
X
X
X
X
X
X
X R/W
X
X
X
X
X
X
X
0 R/W
– –
0 R/W
– – Undefined in read.
X R/W
X
X
X
X
X
X
X
B-V-2-21