Epson S1C33210 Technical Manual page 513

Cmos 32-bit single chip microcomputer
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Register name
Address
Bit
8-bit timer 0
0040160
D7–3
control register
(B)
D2
D1
D0
8-bit timer 0
0040161
D7
reload data
(B)
D6
register
D5
D4
D3
D2
D1
D0
8-bit timer 0
0040162
D7
counter data
(B)
D6
register
D5
D4
D3
D2
D1
D0
8-bit timer 1
0040164
D7–3
control register
(B)
D2
D1
D0
8-bit timer 1
0040165
D7
reload data
(B)
D6
register
D5
D4
D3
D2
D1
D0
8-bit timer 1
0040166
D7
counter data
(B)
D6
register
D5
D4
D3
D2
D1
D0
8-bit timer 2
0040168
D7–3
control register
(B)
D2
D1
D0
8-bit timer 2
0040169
D7
reload data
(B)
D6
register
D5
D4
D3
D2
D1
D0
8-bit timer 2
004016A
D7
counter data
(B)
D6
register
D5
D4
D3
D2
D1
D0
S1C33210 FUNCTION PART
Name
Function
reserved
PTOUT0
8-bit timer 0 clock output control
PSET0
8-bit timer 0 preset
PTRUN0
8-bit timer 0 Run/Stop control
RLD07
8-bit timer 0 reload data
RLD06
RLD07 = MSB
RLD05
RLD00 = LSB
RLD04
RLD03
RLD02
RLD01
RLD00
PTD07
8-bit timer 0 counter data
PTD06
PTD07 = MSB
PTD05
PTD00 = LSB
PTD04
PTD03
PTD02
PTD01
PTD00
reserved
PTOUT1
8-bit timer 1 clock output control
PSET1
8-bit timer 1 preset
PTRUN1
8-bit timer 1 Run/Stop control
RLD17
8-bit timer 1 reload data
RLD16
RLD17 = MSB
RLD15
RLD10 = LSB
RLD14
RLD13
RLD12
RLD11
RLD10
PTD17
8-bit timer 1 counter data
PTD16
PTD17 = MSB
PTD15
PTD10 = LSB
PTD14
PTD13
PTD12
PTD11
PTD10
reserved
PTOUT2
8-bit timer 2 clock output control
PSET2
8-bit timer 2 preset
PTRUN2
8-bit timer 2 Run/Stop control
RLD27
8-bit timer 2 reload data
RLD26
RLD27 = MSB
RLD25
RLD20 = LSB
RLD24
RLD23
RLD22
RLD21
RLD20
PTD27
8-bit timer 2 counter data
PTD26
PTD27 = MSB
PTD25
PTD20 = LSB
PTD24
PTD23
PTD22
PTD21
PTD20
Setting
1 On
0 Off
1 Preset
0 Invalid
1 Run
0 Stop
0 to 255
0 to 255
1 On
0 Off
1 Preset
0 Invalid
1 Run
0 Stop
0 to 255
0 to 255
1 On
0 Off
1 Preset
0 Invalid
1 Run
0 Stop
0 to 255
0 to 255
EPSON
APPENDIX: I/O MAP
Init. R/W
Remarks
0 when being read.
0
R/W
W
0 when being read.
0
R/W
X
R/W
X
X
X
X
X
X
X
X
R
X
X
X
X
X
X
X
0 when being read.
0
R/W
W
0 when being read.
0
R/W
X
R/W
X
X
X
X
X
X
X
X
R
X
X
X
X
X
X
X
0 when being read.
0
R/W
W
0 when being read.
0
R/W
X
R/W
X
X
X
X
X
X
X
X
R
X
X
X
X
X
X
X
B-APPENDIX-5

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