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III PERIPHERAL BLOCK: SERIAL INTERFACE
PER0: Ch.0 parity-error flag (D3) / Serial I/F Ch.0 status register (0x401E2)
PER1: Ch.1 parity-error flag (D3) / Serial I/F Ch.1 status register (0x401E7)
PER2: Ch.2 parity-error flag (D3) / Serial I/F Ch.2 status register (0x401F2)
PER3: Ch.3 parity-error flag (D3) / Serial I/F Ch.3 status register (0x401F7)
Indicates whether a parity error occurred.
Read "1": An error occurred
Read "0": No error occurred
Write "1": Invalid
Write "0": Reset to "0"
The PERx flag is an error flag indicating whether a parity error occurred. When an error has occurred, it is set to "1".
Parity checks are valid only in the asynchronous mode with EPRx set to "1" (parity added). This check is performed
when the received data is transferred from the shift register to the receive data register.
The PERx flag is reset by writing "0".
At initial reset, as well as when RXENx and TXENx both are set to "0", PERx is set to "0" (no error).
OER0: Ch.0 overrun-error flag (D2) / Serial I/F Ch.0 status register (0x401E2)
OER1: Ch.1 overrun-error flag (D2) / Serial I/F Ch.1 status register (0x401E7)
OER2: Ch.2 overrun-error flag (D2) / Serial I/F Ch.2 status register (0x401F2)
OER3: Ch.3 overrun-error flag (D2) / Serial I/F Ch.3 status register (0x401F7)
Indicates whether an overrun error occurred.
Read "1": An error occurred
Read "0": No error occurred
Write "1": Invalid
Write "0": Reset to "0"
The OERx flag is an error flag indicating whether an overrun error occurred. When an error has occurred, it is set to
"1". An overrun error occurs when the next receive operation is completed before the receive data register is read out,
resulting in the receive data register being overwritten.
The OERx flag is reset by writing "0".
At initial reset, as well as when RXENx and TXENx both are set to "0", OERx is set to "0" (no error).
TDBE0: Ch.0 transmit data buffer empty (D1) / Serial I/F Ch.0 status register (0x401E2)
TDBE1: Ch.1 transmit data buffer empty (D1) / Serial I/F Ch.1 status register (0x401E7)
TDBE2: Ch.2 transmit data buffer empty (D1) / Serial I/F Ch.2 status register (0x401F2)
TDBE3: Ch.3 transmit data buffer empty (D1) / Serial I/F Ch.3 status register (0x401F7)
Indicates the status of the transmit data register (buffer).
Read "1": Buffer empty
Read "0": Buffer full
Write: Invalid
TDBEx is set to "0" when transmit data is written to the transmit data register, and is set to "1" when this data is
transferred to the shift register (transmit operation started).
Transmit data is written to the transmit data register when this bit = "1".
At initial reset, TDBEx is set to "1" (buffer empty).
B-III-8-36
EPSON
S1C33210 FUNCTION PART
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