Epson S1C33210 Technical Manual page 420

III PERIPHERAL BLOCK: MONITORED MOBILE ACCESS INTERFACES
RXENS: HDLC receive enable (D7) / HDLC transfer settings register (0x0200308)
TXENS: HDLC transmit enable (D6) / HDLC transfer settings register (0x0200308)
RXIES: HDLC Rx and Sp INT enable (D1) / HDLC transfer settings register (0x0200308)
TXIES: HDLC Tx INT enable (D0) / HDLC transfer settings register (0x0200308)
Writing "1" to a bit enables the corresponding operation or interrupts. Writes of "0" are ignored. Clearing a bit
requires writing to the corresponding bit in the HDLC cancel transfer register.
Reading this register returns the current setting for these enable bits: disabled ("0") or enabled ("1").
Setting RXENS to "1" starts receive operation. Note that there is no flag or abort detection while operation is
disabled.
Write "1": Receive enabled
Write "0": Invalid
Read "1": Receive enabled
Read "0": Receive disabled
Setting TXENS to "1" starts transmit operation. The Mark/Flag on idle (MRKFLG) bit specifies whether the
interface transmits the mark or flag pattern while transmit operation is disabled.
Write "1": Transmit enabled
Write "0": Invalid
Read "1": Transmit enabled
Read "0": Transmit disabled
Setting RXIES to "1" enables Rx and Sp INT interrupts. Note that the Rx enable/disable setting does not affect Rx
INT interrupts.
Write "1": Interrupt disabled
Write "0": Invalid
Read "1": Interrupt enabled
Read "0": Interrupt disabled
Setting TXIES to "1" produces Tx INT interrupts when the transmit queue exceeds the threshold setting.
Write "1": Interrupt disabled
Write "0": Invalid
Read "1": Interrupt enabled
Read "0": Interrupt disabled
B-III-10-34
EPSON
S1C33210 FUNCTION PART