Dram Read/Write Cycles - Epson S1C33210 Technical Manual

DRAM Read/Write Cycles

The following shows the basic bus cycles of DRAM.
The DRAM interface does not accept wait cycles inserted via the #WAIT pin.
DRAM random read cycle
Example: RAS: 1 cycle; CAS: 2 cycles; Precharge: 1 cycle
BCLK
A[11:0]
#RASx
#HCAS/
#LCAS
#RD
D[15:0]
DRAM read cycle (fast page mode)
Example: RAS: 1 cycle; CAS: 2 cycles; Precharge: 1 cycle
RAS cycle
BCLK
ROW
A[11:0]
#RASx
#HCAS/
#LCAS
#RD
D[15:0]
DRAM read cycle (EDO page mode)
Example: RAS: 1 cycle; CAS: 2 cycles; Precharge: 1 cycle
RAS cycle
BCLK
ROW
A[11:0]
#RASx
#HCAS/
#LCAS
#RD
D[15:0]
The read timing in EDO page-mode lags 0.5 cycles behind that in fast page mode.
S1C33210 FUNCTION PART
RAS cycle
ROW
Figure 4.29 DRAM Random Read Cycle
CAS cycle #1
COL #1
Figure 4.30 DRAM Read Cycle (fast page mode)
CAS cycle #1
COL #1
Figure 4.31 DRAM Read Cycle (EDO page mode)
EPSON
II CORE BLOCK: BCU (Bus Control Unit)
Precharge
CAS cycle
COL
data
CAS cycle #2
COL #2
data
CAS cycle #2
COL #2
data
cycle
Precharge
cycle
data
Precharge
cycle
data
B-II-4-27