Page 1 MF1517-01 CMOS 32 - BIT SINGLE CHIP MICROCOMPUTER S1C33210 Technical Manual S1C33210 PRODUCT PART S1C33210 FUNCTION PART...
Page 2 Seiko Epson. Seiko Epson reserves the right to make changes to this material without notice. Seiko Epson does not assume any liability of any kind arising out of any inaccuracies contained in this material or due to its application or use in any product or circuit and, further, there is no representation that this material is applicable to products requiring high level reliability, such as medical products.
Page 3 S1C33210 Technical Manual This manual describes the hardware specifications of the Seiko Epson original 32-bit microcomputer S1C33210. S1C33210 PRODUCT PART Describes the hardware specifications of the S1C33210 except for details of the peripheral circuits. S1C33210 FUNCTION PART Describes details of all the peripheral circuit blocks for the S1C33 Family microcomputers.
Page 5: Table Of Contents
8.6.4 C33 Block AC Characteristic Timing Charts...A-78 8.7 Oscillation Characteristics...A-85 8.8 PLL Characteristics...A-86 9 Package ... A-87 9.1 Plastic Package...A-87 10 Pad Layout ... A-88 10.1 Pad Layout Diagram ...A-88 10.2 Pad Coordinate...A-89 S1C33210 PRODUCT PART Table of Contents ) ...A-11 )...A-12 EPSON TABLE OF CONTENTS...
Page 6 TABLE OF CONTENTS Appendix A <Reference> External Device Interface Timings...A-92 A.1 DRAM (70ns)...A-93 A.2 DRAM (60ns)...A-96 A.3 ROM and Burst ROM...A-100 A.4 SRAM (55ns)...A-102 A.5 SRAM (70ns)...A-104 A.6 8255A...A-106 Appendix B Pin Characteristics... A-107 EPSON...
Page 7 Setting Device Type and Size ...B-II-4-9 Setting SRAM Timing Conditions...B-II-4-10 Setting Timing Conditions of Burst ROM ...B-II-4-11 Bus Operation...B-II-4-12 Data Arrangement in Memory...B-II-4-12 Bus Operation of External Memory...B-II-4-12 Bus Clock...B-II-4-16 S1C33210 FUNCTION PART Table of Contents EPSON TABLE OF CONTENTS...
Page 8 Controlling Oscillation...B-II-6-3 Setting and Switching Over the CPU Operating Clock...B-II-6-4 Power-Control Register Protection Flag ...B-II-6-5 Operation in Standby Mode ...B-II-6-5 I/O Memory of Clock Generator...B-II-6-6 Programming Notes...B-II-6-9 II-7 DBG (Debug Unit) ...B-II-7-1 Debug Circuit...B-II-7-1 I/O Pins of Debug Circuit...B-II-7-1 EPSON...
Page 9 I/O Pins of Low-Speed (OSC1) Oscillation Circuit...B-III-6-1 Oscillator Types ...B-III-6-2 Controlling Oscillation...B-III-6-3 Switching Over the CPU Operating Clock...B-III-6-3 Power-Control Register Protection Flag ...B-III-6-4 Operation in Standby Mode ...B-III-6-4 OSC1 Clock Output to External Devices...B-III-6-4 I/O Memory of Clock Generator...B-III-6-5 Programming Notes...B-III-6-8 EPSON TABLE OF CONTENTS...
Page 10 I/O Memory for Input Interrupts ...B-III-9-17 Programming Notes ...B-III-9-23 III-10 Mobile Access Interfaces... B-III-10-1 Configuration of Mobile Access Interfaces ...B-III-10-1 I/O Pins for Mobile Access Interfaces...B-III-10-2 Basic Settings for Mobile Access Interfaces ...B-III-10-4 UART Communications Mode...B-III-10-7 Overview...B-III-10-7 PDC Communications Mode...B-III-10-8 EPSON...
Page 11 PHS Communications Mode...B-III-10-11 PHS Communications Control and Operation...B-III-10-13 HDLC Communications Mode...B-III-10-14 Overview...B-III-10-14 HDLC Communications Control and Operation...B-III-10-15 Mobile Access Interface Interrupts ...B-III-10-18 Overview...B-III-10-18 Mobile Access Interface Interrupt Outputs...B-III-10-20 I/O Memory for Mobile Access Interfaces...B-III-10-21 Important Notes on Debugging...B-III-10-42 EPSON TABLE OF CONTENTS...
Page 12 V-3 IDMA (Intelligent DMA) ... B-V-3-1 Functional Outline of IDMA...B-V-3-1 Programming Control Information ...B-V-3-1 IDMA Invocation...B-V-3-5 Operation of IDMA...B-V-3-8 Linking ...B-V-3-12 Interrupt Function of Intelligent DMA...B-V-3-13 I/O Memory of Intelligent DMA ...B-V-3-14 Programming Notes...B-V-3-17 APPENDIX I/O MAP ... B-Appendix-1 viii EPSON...
Page 13 S1C33210 PRODUCT PART...
Page 15: Outline
The S1C33210 consists of an S1C33000 32-bit RISC type CPU as its core, peripheral circuits including a bus control unit, DMA controller, interrupt controller, timers, serial interface, and A/D converter, and also mobile access interface and RAM.
Page 16 (3.3 V, 50 MHz) 238 mW typ. (3.3 V, 50 MHz) program that consisted of 55% load instructions, 23% arithmetic operation instructions, 1% mac instruction, 12% branch instructions and 9% ext instruction was being continuously executed. EPSON S1C33210 PRODUCT PART...
Page 17: Block Diagram
Programmable Timer (6 ch.) Programmable Timer (6 ch.) Serial Interface (4 ch.) A/D Converter (4 ch.) Input Port I/O Port Mobile Access Interface Figure 1.2.1 S1C33210 Block Diagram EPSON 1 OUTLINE #RESET #NMI #X2SPD DSIO EA10MD[1:0] BCLK #BUSREQ(P34) #BUSACK(P35) #BUSGET(P31) DST[2:0](P10–12)
Page 18: Pin Description
Pin name P30/#WAIT/#CE4&5 #CE5/#CE15/#CE15&16 P16/EXCL5/#DMAEND1 P04/SIN1 P05/SOUT1 P20/#DRD EPSON Pin name CNT2 CNT1 TXD/SOUT3 PLLC PLLS1 PLLS0 RXD/SIN3 MSEL GOUT OSC3 OSC4 EA10MD0 EA10MD1 #X2SPD P21/#DWE/#GAAS P22/TM0 P23/TM1 DSIO P10/EXCL0/T8UF0/DST0 P11/EXCL1/T8UF1/DST1 P12/EXCL2/T8UF2/DST2 P13/EXCL3/T8UF3/DPC0 P14/FOSC1/DCLK P24/TM2/#SRDY2 P25/TM3/#SCLK2 P15/EXCL4/#DMAEND0 S1C33210 PRODUCT PART...
Page 19: Pin Functions
#CE17&18 #CE8 #RAS1 #CE14 #RAS3 #CE7 #RAS0 #CE13 #RAS2 #CE6 #CE7&8 #CE5 #CE15 #CE15&16 S1C33210 PRODUCT PART Pull-up – – Power supply (+) – (104 Power supply (-); GND Pull- down) – – Analog system power supply (+); AV Pull-up –...
Page 20 #BUSGET: Bus status monitor signal output when CFP31(D1/0x402DC) = "1" and CFEX3(D3/0x402DF) = "0" #GARD: Area read signal output for GA when CFEX3(D3/0x402DF) = "1" Pull-up Area 10 boot mode selection EA10MD1 EA10MD0 External ROM mode – – – – EPSON Function Mode S1C33210 PRODUCT PART...
Page 21 #DMAACK1 SIN1 EXCL4 #DMAEND0 EXCL5 #DMAEND1 SOUT1 S1C33210 PRODUCT PART Pull-up Pull-up K50: Input port when CFK50(D0/0x402C0) = "0" (default) #DMAREQ0: HSDMA Ch. 0 request input when CFK50(D0/0x402C0) = "1" Pull-up K51: Input port when CFK51(D1/0x402C0) = "0" (default) #DMAREQ1: HSDMA Ch. 1 request input when CFK51(D1/0x402C0) = "1"...
Page 22 16-bit timer 2 event counter input when CFP12(D2/0x402D4) = "1", IOC12(D2/0x402D6) = "0" and CFEX0(D0/0x402DF) = "0" T8UF2: 8-bit timer 2 output when CFP12(D2/0x402D4) = "1", IOC12(D2/0x402D6) = "1" and CFEX0(D0/0x402DF) = "0" DST2: DST2 signal output when CFEX0(D0/0x402DF) = "1" (default) EPSON Function S1C33210 PRODUCT PART...
Page 23 #DMAEND1 #DRD #DWE #GAAS #SRDY2 #SCLK2 SOUT2 SIN2 S1C33210 PRODUCT PART Pull-up – P13: I/O port when CFP13(D3/0x402D4) = "0" and CFEX1(D1/0x402DF) = "0" EXCL3: 16-bit timer 3 event counter input when CFP13(D3/0x402D4) = "1", IOC13(D3/0x402D6) = "0" and CFEX1(D1/0x402DF) = "0"...
Page 24 Clock doubling mode set-up pin1: CPU clock = bus clock 1, 0: CPU clock = bus clock Pull-up NMI request input pin Pull-up Initial reset input pin EPSON Function Function fin (f fout (f OSC3 PSCIN 10–25MHz 20–50MHz 10–12.5MHz 40–50MHz PLL is not used Function S1C33210 PRODUCT PART...
Page 25: Power Supply
2 Power Supply This chapter explains the operating voltage of the S1C33210. 2.1 Power Supply Pins The S1C33210 has the power supply pins shown in Table 2.1.1. Pin name Pin No. QFP15-128 8, 27, 47, 74, 93, 111 Power supply (+)
Page 26: Power Supply For Analog Circuits (Av Dd
Noise on the analog power lines decrease the A/D converting precision, so use a stabilized power supply and make the board pattern with consideration given to that. EPSON A-12 S1C33210 PRODUCT PART...
Page 27: Internal Memory
Area 2 is used in debug mode only and it cannot be accessed in user mode (normal program execution status). 3.1 ROM and Boot Address The S1C33210 does not have a built-in ROM. The boot address is fixed at 0x0C00000, and so external ROM/Flash should be used in Area 10.
Page 28: Peripheral Circuits
This chapter lists the built-in peripheral circuits and the I/O memory map. For details of the circuits, refer to the "S1C33210 FUNCTION PART". 4.1 List of Peripheral Circuits The S1C33210 consists of the C33 Core Block, C33 Peripheral Block, C33 DMA Block and C33 Analog Block. C33 Core Block BCU (Bus Control Unit)
Page 29: I/O Memory Map
0, 1: Initial values that are set at initial reset. (However, the registers for the bus and input/output ports are not initialized at hot start.) Not initialized at initial reset. –: Not set in the circuit. S1C33210 PRODUCT PART Table 4.2.1 I/O Memory Map Function Setting reserved...
Page 30 /1024 /512 8-bit timer 1 can /256 generate the OSC3 /128 oscillation-stabilize waiting period. 0 Off Division ratio : selected by /256 Prescaler clock select /128 register (0x40181) 8-bit timer 0 can generate the DRAM refresh clock. S1C33210 PRODUCT PART...
Page 31 D7–6 – second TCMD5 register TCMD4 TCMD3 TCMD2 TCMD1 TCMD0 S1C33210 PRODUCT PART Function 8-bit timer 3 clock control 1 On 8-bit timer 3 P8TS3[2:0] clock division ratio selection 8-bit timer 2 clock control 1 On 8-bit timer 2 P8TS2[2:0]...
Page 32 – – 0 when being read. – – – 0 when being read. – – – 0 when being read. – – – 0 when being read. – – – 0 when being read. Compared with TCND[4:0]. S1C33210 PRODUCT PART...
Page 33 PTD26 register PTD25 PTD24 PTD23 PTD22 PTD21 PTD20 S1C33210 PRODUCT PART Function reserved 8-bit timer 0 clock output control 1 On 8-bit timer 0 preset 1 Preset 8-bit timer 0 Run/Stop control 1 Run 8-bit timer 0 reload data...
Page 34 – 0 when being read. 0 Stop 0 to 255 0 to 255 – – – 0 when being read. 0 Off 0 Invalid – 0 when being read. 0 Stop 0 to 255 0 to 255 S1C33210 PRODUCT PART...
Page 35 D6–0 – protect register Watchdog 0040171 D7–2 – timer enable register – S1C33210 PRODUCT PART Function EWD write protection 1 Write enabled 0 Write-protect – – Watchdog timer enable 1 NMI enabled 0 NMI disabled – EPSON 4 PERIPHERAL CIRCUITS Setting Init.
Page 36 0 Off – – Writing 1 not allowed. 0 OSC1 0 Off 0 Off – – 0 OSC3/PLL – – – 0 when being read. 0 Off 0 On – – Do not write 1. 0 Off S1C33210 PRODUCT PART...
Page 37 00401E4 D7–5 – IrDA register DIVMD0 IRTL0 IRRL0 IRMD01 IRMD00 S1C33210 PRODUCT PART Function Serial I/F Ch.0 transmit data 0x0 to 0xFF(0x7F) TXD07(06) = MSB TXD00 = LSB Serial I/F Ch.0 receive data 0x0 to 0xFF(0x7F) RXD07(06) = MSB RXD00 = LSB –...
Page 38 I/F mode reserved IrDA 1.0 reserved General I/F – – – 0 when being read. 0 Normal Reset by writing 0. 0 Normal Reset by writing 0. 0 Normal Reset by writing 0. 0 Buffer full 0 Empty S1C33210 PRODUCT PART...
Page 39 Serial I/F Ch.3 00401F9 D7–5 – IrDA register DIVMD3 IRTL3 IRRL3 IRMD31 IRMD30 S1C33210 PRODUCT PART Function Ch.2 transmit enable 1 Enabled Ch.2 receive enable 1 Enabled Ch.2 parity enable 1 With parity Ch.2 parity mode selection 1 Odd Ch.2 stop bit selection 1 2 bits Ch.2 input clock selection...
Page 40 0 when being read. Reset when ADD is read. 0 Disabled 0 Stop 0 Normal Reset by writing 0. – – – 0 when being read. Sampring time Use with 9 clocks. 9 clocks 7 clocks 5 clocks 3 clocks S1C33210 PRODUCT PART...
Page 41 – interrupt P16T52 priority register P16T51 P16T50 – P16T42 P16T41 P16T40 S1C33210 PRODUCT PART Function reserved Port input 1 interrupt level reserved Port input 0 interrupt level reserved Port input 3 interrupt level reserved Port input 2 interrupt level reserved...
Page 42 0 when being read. 0 to 7 – – – 0 when being read. 0 to 7 – – – 0 when being read. 0 to 7 – – – 0 when being read. 0 to 7 S1C33210 PRODUCT PART...
Page 43 ESERR0 Port input 4–7, 0040277 D7–6 – clock timer, A/D interrupt enable register ECTM EADE S1C33210 PRODUCT PART Function reserved Key input 1 1 Enabled Key input 0 Port input 3 Port input 2 Port input 1 Port input 0...
Page 44 0 when being read. – – – 0 when being read. 0 No factor is generated – – – 0 when being read. 0 No factor is generated – – – 0 when being read. 0 No factor is generated S1C33210 PRODUCT PART...
Page 45 4–7 DEP5 IDMA enable DEP4 register – DEADE DESTX1 DESRX1 S1C33210 PRODUCT PART Function 16-bit timer 0 comparison A 1 IDMA 16-bit timer 0 comparison B request High-speed DMA Ch.1 High-speed DMA Ch.0 Port input 3 Port input 2...
Page 46 IDMA request register set method 1 Set only selection Interrupt factor flag reset method 1 Reset only selection EPSON Setting Init. R/W Remarks – – – 0 when being read. 0 Invalid – – – 0 RD/WR 0 RD/WR 0 RD/WR S1C33210 PRODUCT PART...
Page 47 K6 input port 00402C4 CP3D data register CP2D CP1D CP0D K63D K62D K61D K60D S1C33210 PRODUCT PART Function reserved 1 – K52 function selection 1 #ADTRG K51 function selection 1 #DMAREQ1 0 K51 K50 function selection 1 #DMAREQ0 0 K50 reserved –...
Page 48 0 Level – – – 0 when being read. K5[2:0] comp.A comp.B 0 TM16 Ch.3 comp.A 0 TM16 Ch.3 comp.B 0 TM16 Ch.4 comp.A 0 TM16 Ch.4 comp.B 0 TM16 Ch.5 comp.A 0 TM16 Ch.5 comp.B S1C33210 PRODUCT PART...
Page 49 P1 I/O port data 00402D5 – register P16D P15D P14D P13D P12D P11D P10D S1C33210 PRODUCT PART Function reserved FPK04 input comparison 1 High FPK03 input comparison FPK02 input comparison FPK01 input comparison FPK00 input comparison reserved FPK13 input comparison...
Page 50 0 P27/TM5 – – – 0 when being read. 0 P35 0 P34 0 P31 Ext. func.(0x402DF) 0 P30 – – – 0 when being read. 0 Low – – – 0 when being read. 0 Input S1C33210 PRODUCT PART...
Page 51 (HW) A14DRA A13DRA A14SZ A14DF1 A14DF0 – A14WT2 A14WT1 A14WT0 S1C33210 PRODUCT PART Function reserved P05 port extended function – P04 port extended function – P31 port extended function 1 #GARD P21 port extended function 1 #GAAS P10, P11, P13 port extended...
Page 52 0 16 bits – Wait cycles – – 0 when being read. – – – 0 when being read. 0 Not used 0 Not used 0 16 bits – – – 0 when being read. Wait cycles S1C33210 PRODUCT PART...
Page 53 RCA0 RPC2 RPC1 RPC0 RRA1 RRA0 – SBUSST SEMAS SEPD SWAITE S1C33210 PRODUCT PART Function reserved Area 6 A6DF[1:0] Number of cycles output disable delay time reserved Area 6 wait control A6WT[2:0] reserved Areas 5–4 device size selection 1 8 bits Areas 5–4...
Page 54 – 0 when being read. 0 External access – – 0 when being read. 0 External access 0 Little endian 0 when being read. Writing 1 not allowed. 0 when being read. Writing 1 not allowed. 0x0C0 S1C33210 PRODUCT PART...
Page 55 004813A D7–4 – register A1X1MD – BCLKSEL1 BCLKSEL0 S1C33210 PRODUCT PART Function Area 18, 17 address strobe signal 1 Enabled Area 16, 15 address strobe signal Area 14, 13 address strobe signal Area 12, 11 address strobe signal reserved Area 8, 7 address strobe signal...
Page 56 16-bit timer 0 reset 1 Reset 16-bit timer 0 Run/Stop control 1 Run EPSON Setting Init. R/W Remarks – – 0 when being read. 0 Normal 0 Disabled 0 Normal 0 Off 0 Invalid 0 when being read. 0 Stop S1C33210 PRODUCT PART...
Page 57 SELFM1 SELCRB1 OUTINV1 CKSL1 PTM1 PRESET1 PRUN1 S1C33210 PRODUCT PART Function 16-bit timer 1 comparison data A 0 to 65535 CR1A15 = MSB CR1A0 = LSB 16-bit timer 1 comparison data B 0 to 65535 CR1B15 = MSB...
Page 58 16-bit timer 2 reset 1 Reset 16-bit timer 2 Run/Stop control 1 Run EPSON Setting Init. R/W Remarks – – 0 when being read. 0 Normal 0 Disabled 0 Normal 0 Off 0 Invalid 0 when being read. 0 Stop S1C33210 PRODUCT PART...
Page 59 SELFM3 SELCRB3 OUTINV3 CKSL3 PTM3 PRESET3 PRUN3 S1C33210 PRODUCT PART Function 16-bit timer 3 comparison data A 0 to 65535 CR3A15 = MSB CR3A0 = LSB 16-bit timer 3 comparison data B 0 to 65535 CR3B15 = MSB...
Page 60 16-bit timer 4 reset 1 Reset 16-bit timer 4 Run/Stop control 1 Run EPSON Setting Init. R/W Remarks – – 0 when being read. 0 Normal 0 Disabled 0 Normal 0 Off 0 Invalid 0 when being read. 0 Stop S1C33210 PRODUCT PART...
Page 61 SELFM5 SELCRB5 OUTINV5 CKSL5 PTM5 PRESET5 PRUN5 S1C33210 PRODUCT PART Function 16-bit timer 5 comparison data A 0 to 65535 CR5A15 = MSB CR5A0 = LSB 16-bit timer 5 comparison data B 0 to 65535 CR5B15 = MSB...
Page 62 (Initial value: 0x0C003A0) IDMA start 1 IDMA start IDMA channel number reserved IDMA enable 1 Enabled EPSON Setting Init. R/W Remarks – – – Undefined in read. 0 Stop 0 to 127 – – – 0 Disabled S1C33210 PRODUCT PART...
Page 63 S0ADRH8 mode S0ADRH7 S0ADRH6 S0ADRH5 S0ADRH4 S0ADRH3 S0ADRH2 S0ADRH1 S0ADRH0 S1C33210 PRODUCT PART Function Ch.0 transfer counter[7:0] (block transfer mode) Ch.0 transfer counter[15:8] (single/successive transfer mode) Ch.0 block length (block transfer mode) Ch.0 transfer counter[7:0] (single/successive transfer mode) Ch.0 address mode selection...
Page 64 1 Set EPSON Setting Init. R/W Remarks Mode Invalid Block Successive Single Inc/dec Inc.(no init) Inc.(init) Dec.(no init) Fixed – – – Undefined in read. 0 Disable – – – Undefined in read. 0 No operation 0 Cleared S1C33210 PRODUCT PART...
Page 65 S1ADRH8 mode S1ADRH7 S1ADRH6 S1ADRH5 S1ADRH4 S1ADRH3 S1ADRH2 S1ADRH1 S1ADRH0 S1C33210 PRODUCT PART Function Ch.1 transfer counter[7:0] (block transfer mode) Ch.1 transfer counter[15:8] (single/successive transfer mode) Ch.1 block length (block transfer mode) Ch.1 transfer counter[7:0] (single/successive transfer mode) Ch.1 address mode selection...
Page 66 1 Set EPSON Setting Init. R/W Remarks Mode Invalid Block Successive Single Inc/dec Inc.(no init) Inc.(init) Dec.(no init) Fixed – – – Undefined in read. 0 Disable – – – Undefined in read. 0 No operation 0 Cleared S1C33210 PRODUCT PART...
Page 67 S2ADRH8 mode S2ADRH7 S2ADRH6 S2ADRH5 S2ADRH4 S2ADRH3 S2ADRH2 S2ADRH1 S2ADRH0 S1C33210 PRODUCT PART Function Ch.2 transfer counter[7:0] (block transfer mode) Ch.2 transfer counter[15:8] (single/successive transfer mode) Ch.2 block length (block transfer mode) Ch.2 transfer counter[7:0] (single/successive transfer mode) Ch.2 address mode selection...
Page 68 1 Set EPSON Setting Init. R/W Remarks Mode Invalid Block Successive Single Inc/dec Inc.(no init) Inc.(init) Dec.(no init) Fixed – – – Undefined in read. 0 Disable – – – Undefined in read. 0 No operation 0 Cleared S1C33210 PRODUCT PART...
Page 69 S3ADRH8 mode S3ADRH7 S3ADRH6 S3ADRH5 S3ADRH4 S3ADRH3 S3ADRH2 S3ADRH1 S3ADRH0 S1C33210 PRODUCT PART Function Ch.3 transfer counter[7:0] (block transfer mode) Ch.3 transfer counter[15:8] (single/successive transfer mode) Ch.3 block length (block transfer mode) Ch.3 transfer counter[7:0] (single/successive transfer mode) Ch.3 address mode selection...
Page 70 1 Set EPSON Setting Init. R/W Remarks Mode Invalid Block Successive Single Inc/dec Inc.(no init) Inc.(init) Dec.(no init) Fixed – – – Undefined in read. 0 Disable – – – Undefined in read. 0 No operation 0 Cleared S1C33210 PRODUCT PART...
Page 71 D15–5 – block CP3 (HW) CP3EN4 interrupt select CP3EN3 register CP3EN2 CP3EN1 CP3EN0 S1C33210 PRODUCT PART Function – Master configuration selection MCRS[1:0] – Reset PHS communications block 1 Reset Reset PDC communications block 1 Reset Reset HDLC communications block 1 Reset –...
Page 72 0 when being read. 0 Disable – – – 0 when being read. Write "1" to clear – – – 0 when being read. 0 No error 0 Buffer A – – – 0 when being read. S1C33210 PRODUCT PART...
Page 73 HDLC receive 0200310 D15–3 – queue interrupt (HW) RXFTH2 threshold RXFTH1 register RXFTH0 S1C33210 PRODUCT PART Function – HDLC error reset 1 Reset HDLC E/S interrupt reset 1 Reset – HDLC receive interrupt reset 1 Reset HDLC transmit interrupt reset 1 Reset –...
Page 74 – 0 when being read. 0 Not detected 0 Not detected – – – 0 when being read. 0 Not detected – – – 0 when being read. 0 Not detected 0 Not available 0 Not detected S1C33210 PRODUCT PART...
Page 75 HDLC monitor 0200336 D15–8 – register (HW) ESINT SPINT RXINT TXINT D3–0 – S1C33210 PRODUCT PART Function – Residue Code RCODE[7:0] Number of valid bits in excess 11111110 residue code bits at end of frame 11111100 11111000 11110000 11100000 11000000 10000000 –...
Page 76: Power-Down Control
OSC3 OSC3 Circuits/functions stopped CPU and DMA CPU, BCU, bus clock, and DMA CPU, BCU, bus clock, DMA, high-speed (OSC3) oscillation circuit, prescaler, and peripheral circuits that use the prescaler output clocks "1" "0" S1C33210 PRODUCT PART high OSC3 Default...
Page 77 2 above. Also, if only some of the circuits in group 1 above are used, turn off all the other circuits and stop clock supply from the prescaler to those circuits. The table below shows prescaler operation control and control of clock supply to these blocks from the prescaler. S1C33210 PRODUCT PART 5 POWER-DOWN CONTROL Control bit CLKCHG(D2)/...
Page 78 Control bit Control bit EPSON "1" "0" Default STOP STOP STOP STOP STOP STOP STOP STOP STOP STOP STOP STOP STOP STOP STOP STOP STOP STOP STOP STOP STOP STOP STOP STOP STOP STOP "1" "0" Default OSC3/ S1C33210 PRODUCT PART...
Page 79: Basic External Wiring Diagram
Gate capacitor Drain capacitor Feedback resistor Resistor Capacitor Capacitor Note: The above table is simply an example, and is not guaranteed to work. S1C33210 PRODUCT PART 6 BASIC EXTERNAL WIRING DIAGRAM EA10MD0 EA10MD1 #X2SPD S1C33210 [The potential of the substrate...
Page 80: Precautions On Mounting
OSC3 pattern to connect other components than the oscillation system. pattern PLLC OSC4 OSC3 or other signals on the board pattern. and AV affects A/D conversion precision. EPSON PLLC pins with patterns as short and large as S1C33210 PRODUCT PART...
Page 81 Prohibited pattern Large current signal line High-speed signal line S1C33210 PRODUCT PART and V pins with a bypass capacitor, the pins should be connected as for the analog system should be connected to K60 (AD0)
Page 82: Electrical Characteristics
Storage temperature A-68 Condition 1 pin Total of all pins 1 pin Total of all pins EPSON Rated value Unit -0.3 to +4.0 -0.3 to V +0.5 -0.3 to +7.0 -0.3 to AV +0.3 -65 to +150 S1C33210 PRODUCT PART =0V)
Page 83: Recommended Operating Conditions
CPU operating clock frequency Low-speed oscillation frequency Operating temperature Input rise time (normal input) Input fall time (normal input) Input rise time (schmitt input) Input fall time (schmitt input) S1C33210 PRODUCT PART 8 ELECTRICAL CHARACTERISTICS Symbol Condition OSC1 EPSON =0V) Min.
Page 84: Dc Characteristics
V f=1MHz, V EPSON =2.7V to 3.6V, Ta=-40 C to +85 C) Min. Typ. Max. Unit – – – – -0.4 – – – – – – – – – – – – – – – – S1C33210 PRODUCT PART...
Page 85: Current Consumption
1: The values of current consumption while the CPU is operating were measured when a test program that consists of 55% load instructions, 23% arithmetic operation instructions, 1% mac instruction, 12% branch instructions and 9% ext instruction is being executed in the built-in ROM continuously. S1C33210 PRODUCT PART (Unless otherwise specified: V Condition...
Page 86: A/D Converter Characteristics
Indicates the maximum value when A/D clock = 32 kHz (minimum clock frequency in 3V system). Note: • Be sure to use as V = AV • The A/D converter cannot be used when the S1C33210 is used with a 2V power source. A/D conversion error V[000]h = Ideal voltage at zero-scale point (=0.5LSB) V'[000]h = Actual voltage at zero-scale point V[3FF]h = Ideal voltage at full-scale point (=1022.5LSB)
Page 87 Actual conversion characteristic Ideal conversion characteristic V'[000]h Analog input Differential linearity error V'[N]h V'[N-1]h Analog input S1C33210 PRODUCT PART V'[3FF]h Integral linearity error E Ideal conversion characteristic Actual conversion characteristic Differential linearity error E EPSON 8 ELECTRICAL CHARACTERISTICS ' - V...
Page 88: Ac Characteristics
Low level = 0.4 V = 1/2 V Low level = 1/2 V High level = 1/2 V Low level = 1/2 V 90% V ) 5 ns 10% V ) 5 ns = 50 pF EPSON S1C33210 PRODUCT PART...
Page 89: C33 Block Ac Characteristic Tables
Minimum reset pulse width BCLK clock output characteristics (Note) These AC characteristic values are applied only when the high-speed oscillation circuit is used. Item BCLK clock output duty S1C33210 PRODUCT PART to V voltage range. (Unless otherwise specified: V =2.7V to 3.6V, V Symbol Min.
Page 90 =2.7V to 3.6V, V Symbol Min. WRD2 (1+WC)-10 EPSON =0V, Ta=-40 C to +85 C) Max. Unit – – =0V, Ta=-40 C to +85 C) Max. Unit (1+WC)-25 (1+WC)-25 (0.5+WC)-25 =0V, Ta=-40 C to +85 C) Max. Unit S1C33210 PRODUCT PART...
Page 91 Input, Output and I/O port Item Input data setup time Input data hold time Output data delay time K-port interrupt SLEEP, HALT2 mode input pulse width Others S1C33210 PRODUCT PART (Unless otherwise specified: V =2.7V to 3.6V, V Symbol Min. RASD1 RASD2 (2+WC)-10...
Page 92: C33 Block Ac Characteristic Timing Charts
8.6.4 C33 Block AC Characteristic Timing Charts Clock (1) When an external clock is input (in x1 speed mode): OSC3 (High-speed clock) BCLK (Clock output) (2) When the high-speed oscillation circuit is used for the operating clock: BCLK (Clock output) A-78 EPSON C3ED S1C33210 PRODUCT PART...
Page 93 SRAM read cycle (when a wait cycle is inserted) BCLK A[23:0] #CEx RDD1 D[15:0] #WAIT is measured with respect to the first signal change (negation) from among the #RD, #CEx and A[23:0] signals. S1C33210 PRODUCT PART RDD1 CEAC1 ACC1 RDAC1 (wait cycle) (C1 only) CEAC1 ACC1...
Page 94 A[23:0] #CEx D[15:0] #WAIT SRAM write cycle (when wait cycles are inserted) BCLK A[23:0] #CEx WRD1 WDD1 D[15:0] #WAIT A-80 WRD1 WDD1 (wait cycle) (wait cycle) Wait cycle follows Last cycle follows EPSON WRD2 (last cycle) WRD2 S1C33210 PRODUCT PART...
Page 95 RASD1 #RAS #HCAS/ #LCAS RDD1 D[15:0] WRD1 WDD1 D[15:0] is measured with respect to the first signal change (negation) of either the #RD or the A[23:0] signals. S1C33210 PRODUCT PART CAS1 PRE1 (precharge) RASD1 RASW CASD1 CASD2 CASW RDD1 RDW2...
Page 96 WDD1 WDD2 Data transfer #2 CAS1 CAS2 RASW CASD1 CASD2 CASW RDW2 ACCE CACE RACE ACCE WRW2 WDD2 EPSON Next data transfer RAS1' CAS1' RASD2 RDD3 WRD3 Next data transfer PRE1 RAS1' (precharge) RASD2 RDD3 WRD3 WDD2 S1C33210 PRODUCT PART...
Page 97 A[1:0] #CEx RDD1 ACC2 CEAC RDAC2 D[15:0] is measured with respect to the first signal change (negation) from among the #RD, #CEx and A[23:0] signals. S1C33210 PRODUCT PART CBR refresh cycle CBR1 CBR2 RASD1 CASD1 Self-refresh mode RASD1 CASD1 Burst cycle...
Page 98 A[23:0], #RD, #WRL, #WRH, #HCAS, #LCAS, #CE[17:4], D[15:0] Input, output and I/O port timing BCLK Kxx, Pxx (input: data read from the port) Pxx, Rxx (output) (K-port interrupt input) A-84 BRQS BRQH Valid input BAKD NMIW INPS INPH Valid input OUTD KINW EPSON S1C33210 PRODUCT PART...
Page 99: Oscillation Characteristics
OSC1 crystal oscillation (Unless otherwise specified: crystal=Q11C02RX Item Operating temperature #1 Q11C02RX: Crystal resonator made by Seiko Epson #2 "C =15pF" includes board capacitance. (Unless otherwise specified: V Item Oscillation start time...
Page 100: Pll Characteristics
PLLS1 PLLS0 PLL characteristics (Unless otherwise specified: V Item Symbol Jitter (peak jitter) Lockup time #1 Q3204DC: Crystal oscillator made by Seiko Epson A-86 Mode Fin (OSC3 clock) 10 to 25MHz 10 to 12.5MHz PLL not used – =2.7V to 3.6V, V =0V, crystal oscillator=Q3204DC =4.7k , C...
Page 101: Package
This thermal resistance is a value under the condition that the measured device is hanging in the air and has no air-cooling. Thermal resistance greatly varies according to the mounting condition on the board and air-cooling condition. S1C33210 PRODUCT PART INDEX +0.1 0.16...
Page 102: Pad Layout
10 PAD LAYOUT 10 Pad Layout 10.1 Pad Layout Diagram Die No. A-88 (0, 0) TBD mm EPSON S1C33210 PRODUCT PART...
Page 103: Pad Coordinate
41 N.C. 42 D9 43 N.C. 44 D8 45 N.C. 46 V 47 N.C. 48 VRL 49 K63/AD3 50 N.C. S1C33210 PRODUCT PART Pad name -2.352 -2.54 51 K62/AD2 -2.268 -2.54 52 N.C. -2.184 -2.54 53 AV -2.1 -2.54 54 K61/AD1 -2.016...
Page 104 0.63 -2.834 0.546 -2.834 0.462 -2.834 0.378 -2.834 0.294 -2.834 0.21 -2.834 0.126 -2.834 0.042 -2.834 -0.042 -2.834 -0.126 -2.834 -0.21 -2.834 -0.294 -2.834 -0.378 -2.834 -0.462 -2.834 -0.546 -2.834 -0.63 -2.834 -0.714 -2.834 -0.798 -2.834 -0.882 S1C33210 PRODUCT PART...
Page 105 215 N.C. 216 N.C. Note: The S1C33210 is constructed with 0.35 m process technology. Since the pad pitch is to small, it is impossible to use all pads when mounting the chip (die form) on the board. When mounting the chip use the pads other than "N.C."...
Page 106: Appendix A External Device Interface Timings
Conditions such as the output delay time of the device, delay due to wiring and load capacitance, and input setup time are not considered. • The described contents are reference data and cannot be guaranteed to work. A-92 External Device Interface Timings EPSON S1C33210 PRODUCT PART...
Page 107: Dram (70Ns
Access time after #CAS precharge <Refresh cycle> #CAS setup time #CAS hold time #RAS precharge #CAS hold time #RAS pulse width (only in refresh cycle) S1C33210 PRODUCT PART APPENDIX A <REFERENCE> EXTERNAL DEVICE INTERFACE TIMINGS RAS cycle CAS cycle Unit: ns 33MHz Symbol Min.
Page 108 CAS cycle COL #1 RD data WR data CAS cycle COL #1 RD data WR data Fixed Refresh RAS pulse width EPSON RAS precharge ROW #2 CAS cycle RAS precharge COL #2 RD data WR data RAS precharge S1C33210 PRODUCT PART...
Page 109 #RAS #CAS D[15:0](RD) D[15:0](WR) DRAM: 70ns, CPU: 25/20MHz, CAS-before-RAS refresh cycle RPC delay BCLK #RAS #CAS S1C33210 PRODUCT PART APPENDIX A <REFERENCE> EXTERNAL DEVICE INTERFACE TIMINGS CAS cycle ROW #1 COL #1 RD data WR data CAS cycle CAS cycle...
Page 110: Dram (60Ns
Cycle – – 10000 10000 – – – – – – – – – – – – – – – – 10000 EPSON Refresh RAS pulse Refresh RPC delay width 25MHz 20MHz Time Cycle Time Cycle Time S1C33210 PRODUCT PART...
Page 111 #RAS #CAS D[15:0](RD) D[15:0](WR) DRAM: 60ns, CPU: 33MHz, CAS-before-RAS refresh cycle RPC delay BCLK #RAS #CAS S1C33210 PRODUCT PART APPENDIX A <REFERENCE> EXTERNAL DEVICE INTERFACE TIMINGS CAS cycle COL #1 RD data WR data CAS cycle COL #1 RD data...
Page 112 ROW #1 COL #1 RD data WR data CAS cycle CAS cycle COL #1 COL #2 RD data WR data WR data Fixed Refresh RAS pulse width EPSON RAS precharge ROW #2 RAS precharge RD data RAS precharge S1C33210 PRODUCT PART...
Page 113 #RAS #CAS D[15:0](RD) D[15:0](WR) DRAM: 60ns, CPU: 20MHz, CAS-before-RAS refresh cycle RPC delay BCLK #RAS #CAS S1C33210 PRODUCT PART APPENDIX A <REFERENCE> EXTERNAL DEVICE INTERFACE TIMINGS RAS cycle CAS cycle ROW #1 COL #1 RD data WR data CAS cycle...
Page 114: Rom And Burst Rom
Wait cycle 33MHz Symbol Min. Max. Cycle – – – – RD data Burst read cycle RD data RD data RD data EPSON Output disable Read cycle delay cycle 25MHz 20MHz Time Cycle Time Cycle Time RD data S1C33210 PRODUCT PART...
Page 115 #CE9, 10 D[15:0] ROM: 100ns, CPU: 20MHz, burst read BCLK Normal read cycle A[23:0] #CE9, 10 D[15:0] S1C33210 PRODUCT PART APPENDIX A <REFERENCE> EXTERNAL DEVICE INTERFACE TIMINGS RD data Burst read cycle RD data RD data RD data RD data...
Page 116: Sram (55Ns
#CEx D[15:0] A-102 Write cycle Read cycle 33MHz Symbol Min. Max. Cycle – – – – – – – – – RD data WR data EPSON Output disable delay time 25MHz 20MHz Time Cycle Time Cycle Time S1C33210 PRODUCT PART...
Page 117 SRAM: 55ns, CPU: 20MHz, read cycle BCLK A[23:0] #CEx D[15:0] SRAM: 55ns, CPU: 20MHz, write cycle S1C33210 PRODUCT PART APPENDIX A <REFERENCE> EXTERNAL DEVICE INTERFACE TIMINGS RD data BCLK A[23:0] #CEx D[15:0] WR data EPSON A-103...
Page 118: Sram (70Ns
#CEx D[15:0] A-104 Write cycle Read cycle 33MHz Symbol Min. Max. Cycle – – – – – – – – – RD data WR data EPSON Output disable delay time 25MHz 20MHz Time Cycle Time Cycle Time S1C33210 PRODUCT PART...
Page 119 APPENDIX A <REFERENCE> EXTERNAL DEVICE INTERFACE TIMINGS SRAM: 70ns, CPU: 25/20MHz, read cycle BCLK A[23:0] #CEx RD data D[15:0] SRAM: 70ns, CPU: 25/20MHz, write cycle BCLK A[23:0] #CEx D[15:0] WR data EPSON S1C33210 PRODUCT PART A-105...
Page 120: 8255A
Input data hold time 1 The S1C33210 enables up to 7 cycles of wait-cycle insertion. If a number of wait cycles more than 7 cycles needs to be inserted, input the #WAIT signal from external hardware. Note that the interface must be set for SRAM type devices to insert wait cycles using the #WAIT pin.
Page 121 K51/#DMAREQ1 –– K63/AD3 K62/AD2 K61/AD1 K60/AD0 K52/#ADTRG #CE10EX/#CE9&10EX #CE4/#CE11/#CE11&12 #RESET #NMI #CE9/#CE17/#CE17&18 #CE7/#RAS0/#CE13/ #RAS2 OSC2 OSC1 S1C33210 PRODUCT PART I/O cell Characteristic name Input XBH1T CMOS/LVTTL SCHMITT XBH1T CMOS/LVTTL SCHMITT XOB1T XBH1T CMOS/LVTTL SCHMITT XBH1T CMOS/LVTTL SCHMITT XBB1 CMOS/LVTTL XBH1T...
Page 122 2 mA Pull-down Test pin 2 mA 2 mA 2 mA 2 mA 2 mA 2 mA 2 mA 2 mA 2 mA 2 mA 2 mA 2 mA 2 mA 2 mA 2 mA 2 mA S1C33210 PRODUCT PART...
Page 123 Note 1) The voltage applied to this pin must be 0V V Note 2) This pin is set as an input pin during device testing. Normally it is an output pin. Note 3) The XBB1 cell is a fail-safe cell. S1C33210 PRODUCT PART I/O cell Characteristic...
Page 124: Appendix B Pin Characteristics
APPENDIX B PIN CHARACTERISTICS THIS PAGE IS BLANK. EPSON A-110 S1C33210 PRODUCT PART...
Page 125 S1C33210 FUNCTION PART...
Page 127: Ioutline
S1C33210 FUNCTION PART OUTLINE...
Page 129: Introduction
The Function Part gives a detailed description of the various function blocks built into the Seiko Epson original 32-bit microcomputer S1C33210. The S1C33210 employs a RISC type CPU, and has a powerful instruction set capable of compilation into compact code, despite the small CPU core size.
Page 130 I OUTLINE: INTRODUCTION THIS PAGE IS BLANK. EPSON B-I-1-2 S1C33210 FUNCTION PART...
Page 131: Block Diagram
I-2 BLOCK DIAGRAM The S1C33210 consists of five major blocks: C33 Core Block, C33 Peripheral Block, C33 Analog Block, C33 DMA Block and C33 Internal Memory Block. Figure 2.1 shows the configuration of the S1C33 blocks. C33 DMA Block C33_DMA...
Page 132 DMA command information and IDMA (Intelligent DMA) that uses a memory area for storing DMA command information. C33 Memory Block The following internal memory area are provided; 8 KB SRAM For details of the blocks, refer to the respective section in this manual. B-I-2-2 EPSON S1C33210 FUNCTION PART...
Page 133: List Of Pins
– P35: #BUSACK #BUSACK: Bus acknowledge output when CFP35(D5/0x402DC) = "1" S1C33210 FUNCTION PART Function Address bus (A0) when SBUSST(D3/0x4812E) = "0" (default) Bus strobe (low byte) signal when SBUSST(D3/0x4812E) = "1" Area 9 chip enable when CEFUNC[1:0](D[A:9])/0x48130) = "00" (default) Area 17 chip enable when CEFUNC[1:0](D[A:9])/0x48130) = "01"...
Page 134 16-bit timer 5 event counter input when CFP16(D6/0x402D4) = "1" and IOC16(D6/0x402D6) = "0" IOC16(D6/0x402D6) = "1" I/O port when CFP05(D5/0x402D0) = "0" and CFEX5(D5/0x402DF) = "0" (default) Serial I/F Ch. 1 data output when CFP05(D5/0x402D0) = "1" and CFEX5(D5/0x402DF) = "0" EPSON S1C33210 FUNCTION PART...
Page 135 EXCL4 EXCL4: #DMAEND0 #DMAEND0: HSDMA Ch. 0 end-of-transfer signal output when CFP15(D5/0x402D4) = "1" and S1C33210 FUNCTION PART Function Input port when CFK52(D2/0x402C0) = "0" (default) A/D converter trigger input when CFK52(D2/0x402C0) = "1" Input port when CFK60(D0/0x402C3) = "0" (default) A/D converter Ch.
Page 136 TXD output*1 when MSEL pin input is at High level SOUT3 output when MSEL pin input is at Low level RXD input when MSEL pin input is at High level SIN3 input when MSEL pin input is at Low level EPSON S1C33210 FUNCTION PART...
Page 137 #NMI Pull-up NMI request input pin #RESET Pull-up Initial reset input pin Note: "#" in the pin names indicates that the signal is low active. S1C33210 FUNCTION PART Table 3.4 List of Pins for Clock Generator Function PLLS0 fin (f...
Page 138 I OUTLINE: LIST OF PINS THIS PAGE IS BLANK. EPSON B-I-3-6 S1C33210 FUNCTION PART...
Page 139: Core Block
S1C33210 FUNCTION PART CORE BLOCK...
Page 141: Introduction
(Internal Silicon Integration Bus) for interfacing with on-chip Peripheral Macro Cells. C33 DMA Block C33_DMA (IDMA, HSDMA) C33_ADC (A/D converter) C33 Analog Block S1C33210 FUNCTION PART C33 Internal Memory Block Internal RAM (Area 0) C33_CORE (CPU, BCU, ITC, CLG, DBG) C33_SBUS...
Page 142 II CORE BLOCK: INTRODUCTION THIS PAGE IS BLANK. EPSON B-II-1-2 S1C33210 FUNCTION PART...
Page 143: Cpu And Operating Mode
User Logic Block. Refer to the "S1C33000 Core CPU Manual" for details of the S1C33000. EPSON S1C33210 FUNCTION PART B-II-2-1...
Page 144: Standby Mode
Note that SLEEP mode cannot be canceled with an interrupt factor except for reset and NMI if the PSR is set into interrupt disabled status. EPSON B-II-2-2 S1C33210 FUNCTION PART...
Page 145: Notes On Standby Mode
(OSC3) oscillation circuit when using the debugging functions. Furthermore, only the CPU and BCU operate in the debug mode, and other internal peripheral circuits (except the oscillation circuit) stop operating. S1C33210 FUNCTION PART II CORE BLOCK: CPU AND OPERATING MODE for normal operation.
Page 146: Trap Table
Timer 0 underflow Timer 1 underflow Timer 2 underflow Timer 3 underflow EPSON IDMA Priority – High – – – – – – – – – – – – – – – – – – – – – – S1C33210 FUNCTION PART...
Page 147 Port input interrupt 6 71(Base+11C) Port input interrupt 7 Base = Set value in the TTBR register (0x48134 to 0x48137); 0xC00000 by default. S1C33210 FUNCTION PART II CORE BLOCK: CPU AND OPERATING MODE Exception/interrupt factor Receive error Receive buffer full Transmit buffer empty –...
Page 148 II CORE BLOCK: CPU AND OPERATING MODE THIS PAGE IS BLANK. EPSON B-II-2-6 S1C33210 FUNCTION PART...
Page 149: Initial Reset
#NMI #RESET #NMI must be set to high longer than the reset pulse width. (1) Cold start S1C33210 FUNCTION PART Table 3.1 Pins for Initial Reset Function Cold start #RESET = low & #MNI = high The vector at the boot address is loaded to the PC.
Page 150: Power-On Reset
= 3.3 V) (OSC3 oscillation start time) or more STA3 0.5V 0.1V Figure 3.2 Power-on Reset Timing or less (low level) after turning the power on until the supply voltage rises at EPSON or less until the S1C33210 FUNCTION PART...
Page 151: Boot Address
(cold start or hot start). Therefore, it is necessary to set up the peripheral circuit conditions. Refer to the I/O maps or explanation of each peripheral circuit section for initial settings of the peripheral circuits. S1C33210 FUNCTION PART II CORE BLOCK: INITIAL RESET EPSON B-II-3-3...
Page 152 II CORE BLOCK: INITIAL RESET THIS PAGE IS BLANK. EPSON B-II-3-4 S1C33210 FUNCTION PART...
Page 153: Bcu (Bus Control Unit)
#DWE/P21 O DRAM write (Low-byte) / I/O port #X2SPD EA10MD[1:0] S1C33210 FUNCTION PART Table 4.1 I/O Pin List CPU - BCLK clock ratio 1: CPU clock = Bus clock, 0: CPU clock = Bus clock 2 Area 10 boot mode selection...
Page 154 The internal bus signals are available when an internal access area is set using the BCU register. The bus conditions can be programmed using the BCU registers similar to the external bus. B-II-4-2 Table 4.2 List of User Interface Signals Function EPSON S1C33210 FUNCTION PART...
Page 155: Combination Of System Bus Control Signals
1 In the #BSL system, the A0 and #WRH pin functions change according to the endian selected (little endian or big endian). When using DRAM, the #CE output pins in areas 7–8 (areas 13–14) function as the #RAS1–2 (#RAS3–4) pins. S1C33210 FUNCTION PART II CORE BLOCK: BCU (Bus Control Unit) Table 4.3 Interface Selection Interface method A0 system (default) SBUSST(D3/0x4812E) = "0"...
Page 156: Memory Area
0x6FFFFFF External memory (16MB) 0x6000000 0x5FFFFFF 0x5000000 0x4FFFFFF External memory (16MB) 0x4000000 0x3FFFFFF External memory (16MB) 0x3000000 0x2FFFFFF External memory (16MB) 0x2000000 0x1FFFFFF External memory (8MB) 0x1800000 0x17FFFFF External memory (8MB) 0x1000000 0x0FFFFFF External memory (4MB) 0x0C00000 S1C33210 FUNCTION PART...
Page 157: External Memory Map And Chip Enable
0x0200000 Area 4 (#CE4) 0x01FFFFF SRAM type External memory 1 (1MB) 8 or 16 bits 0x0100000 CEFUNC = "00" S1C33210 FUNCTION PART Table 4.5 Switching of #CE Output CEFUNC = "00" CEFUNC = "01" #CE4 #CE11 #CE5 #CE15 #CE6 #CE6...
Page 158 0x2FFFFFF External memory 4 (16MB) 0x2000000 (#CE11+12) 0x1FFFFFF External memory 3 (16MB) 0x1000000 0x0FFFFFF External memory 2 (8MB) 0x0800000 0x07FFFFF External memory 1 (4MB) 0x0400000 CEFUNC = "10" or "11" Figure 4.2 External System Memory Map EPSON S1C33210 FUNCTION PART...
Page 159: Using Internal Memory On External Memory Area
CFEX3 (D3)/Port function extension register (0x402DF) = "1" These signals are common used to all the above areas, so when two or more areas are selected to output the exclusive signal, OR condition is applied. S1C33210 FUNCTION PART #WRH #WRL Figure 4.3 #GAAS and #GARD Signals...
Page 160: Area 10
Table 4.6 Area 10 Boot Mode Selection Area 10 boot mode – – – External ROM boot mode External ROM boot mode 0x0FFFFFF Area 10 External memory is accessed. Set-up example 25 MHz 5 wait 0x0C00000 Figure 4.4 Area 10 Memory Map EPSON S1C33210 FUNCTION PART...
Page 161: Setting External Bus Conditions
8 bits (A10SZ = "1"). For differences in bus operation due to the device size and access data size, refer to "Bus Operation of External Memory". S1C33210 FUNCTION PART Table 4.7 Device Type Burst ROM type A14DRA(D8)/Areas 14–13 set-up register(0x48122)
Page 162: Setting Sram Timing Conditions
Areas 18–15 set-up register(0x48120) A14DF[1:0](D5:4]) Areas 14–13 set-up register(0x48122) A12DF[1:0](D5:4]) Areas 12–11 set-up register(0x48124) A10DF[1:0](D5:4]) Areas 10–9 set-up register(0x48126) A8DF[1:0](D[5:4]) Areas 8–7 set-up register(0x48128) A6DF[1:0](D[D:C]) Areas 6–4 set-up register(0x4812A) A5DF[1:0](D[5:4]) Areas 6–4 set-up register(0x4812A) EPSON Control register S1C33210 FUNCTION PART...
Page 163: Setting Timing Conditions Of Burst Rom
RBST8 (DD) / Bus control register (0x4812E) is used for this selection. The eight-consecutive-burst mode is selected by writing "1" to RBST8 and the four-consecutive-burst mode is selected by setting the bit to "0". At cold start, the four-consecutive-burst mode is set by default. S1C33210 FUNCTION PART II CORE BLOCK: BCU (Bus Control Unit) EPSON...
Page 164: Bus Operation
In little-endian method, the 8-bit device must be connected to the low- order 8 bits of the data bus. In big-endian method, the 8-bit device must be connected to the high-order 8 bits of the data bus. EPSON Remarks S1C33210 FUNCTION PART...
Page 165 Byte 1 Destination (16-bit device) Big-endian Source (general-purpose register) Byte 3 Byte 2 Byte 1 Destination (16-bit device) Figure 4.7 Half-word Data Writing to a 16-bit Device S1C33210 FUNCTION PART Byte 0 #WRH A[1:0]=00 Byte 0 #WRH A[1:0]=10 Byte 0 #WRH...
Page 166 Data retained Byte 1 Data retained Byte 2 Data retained Byte 3 (X: Not connected/Unused) Bus operation Data bus #WRH #WRL Byte 3 Data retained Byte 2 Data retained Byte 1 Data retained Byte 0 Data retained S1C33210 FUNCTION PART...
Page 167 Byte 2 Byte 1 Big-endian Source (general-purpose register) Byte 3 Byte 2 Byte 1 Figure 4.15 Byte Data Writing to an 8-bit Device S1C33210 FUNCTION PART Byte 0 A[1:0]=00 Byte 0 A[1:0]=11 Byte 0 A[1:0]= 0 Byte 0 A[1:0]= 1...
Page 168: Bus Clock
(X: Not connected/Unused) Bus operation Data bus #WRH #WRL Byte 0 Ignored To CPU #X2SPD pin Bus clock BCLKSEL[1:0] BCU_CLK 1/1 or 1/2 1 Access to the internal RAM 2 Access to the external memory S1C33210 FUNCTION PART BCLK pin...
Page 169: Bus Speed Mode
The bus clock is also output from the BCLK pin to an external device. The BCLK output clock can be selected from among four types using BCLKSEL[1:0] (D[1:0]) / BCLK select register (0x4813A). BCLKSEL1 S1C33210 FUNCTION PART Table 4.12 Selection of BCLK Output Clock BCLKSEL0...
Page 170: Bus Cycles In External System Interface
BCLK addr A[23:0] #CExx data D[15:0] #WAIT Figure 4.19 Basic Read Cycle with No Wait addr Figure 4.20 Read Cycle with Wait EPSON S1C33 SRAM A[9:1] A[8:0] D[15:0] I/O[15:0] #WRH #WRL (3) #BSL system (big endian) data S1C33210 FUNCTION PART...
Page 171: Bus Timing
With an output disable cycle, there is normally a gap between one read cycle and the next. Note, however, that this output disable cycle is not inserted in the case of consecutive reads in a memory area for which the same chip enable signal is output. S1C33210 FUNCTION PART II CORE BLOCK: BCU (Bus Control Unit) addr Hazard occurrence.
Page 172: Sram Write Cycles
Figure 4.23 Byte Write Cycle with No Wait (A0 system, little endian) BCLK A[23:0] #CExx #BSH #BSL #WRL D[15:8] D[7:0] Figure 4.24 Byte Write Cycle with No Wait (#BSL system, little endian) B-II-4-20 addr data addr Undefined Valid addr Undefined Valid EPSON Valid Undefined Valid Undefined S1C33210 FUNCTION PART...
Page 173 In this case, the bus write cycle consists of [number of wait cycles + 1], as in the case of read cycles (providing that there is no external wait). S1C33210 FUNCTION PART addr data Figure 4.25 Half-word Write Cycle with Wait...
Page 174: Burst Rom Read Cycles
If area 10 or 9 is set for burst ROM, a SRAM write cycle is executed when a write to that area is attempted. In this case, wait cycles via the #WAIT pin can be inserted. B-II-4-22 addr[23:2] "00" "01" Figure 4.26 Burst Read Cycle EPSON "10" "11" S1C33210 FUNCTION PART...
Page 175: Dram Direct Interface
Table 4.14 DRAM Configuration Example (areas 7 and 8 only) Area 7 1 I/O 2 I/O 3 I/O 4 DRAM (1M) 5 DRAM (4M) 6 DRAM (16M) S1C33210 FUNCTION PART S1C33 4M DRAM (256K x 16) A[9:1] A[8:0] D[15:0] I/O[15:0]...
Page 176: Dram Setting Conditions
RPC2(D9)/Bus control register(0x4812E) CBR refresh RPC1(D8)/Bus control register(0x4812E) RPC0(D7)/Bus control register(0x4812E) 2 cycles RRA[1:0](D[6:5])/Bus control register(0x4812E) 1 cycle RPRC[1:0](D[7:6])/DRAM timing set-up register(0x48130) 1 cycle CASC[1:0](D[4:3])/DRAM timing set-up register(0x48130) 1 cycle RASC[1:0](D[1:0])/DRAM timing set-up register(0x48130) EPSON Control bits S1C33210 FUNCTION PART...
Page 177 If RPC1 is switched over when RPC2 = "1" (refresh enabled), an undesirable self-refresh cycle is generated. So be sure to clear RPC2 to "0" (refresh disabled) before selecting the refresh method. S1C33210 FUNCTION PART II CORE BLOCK: BCU (Bus Control Unit) Table 4.16 Column Address Size...
Page 178 Table 4.19 Number of CAS Cycles CASC1 CASC0 Number of cycles 4 cycles 3 cycles 2 cycles 1 cycle Table 4.20 Number of RAS Cycles RASC1 RASC0 Number of cycles 4 cycles 3 cycles 2 cycles 1 cycle EPSON S1C33210 FUNCTION PART...
Page 179: Dram Read/Write Cycles
#LCAS D[15:0] Figure 4.31 DRAM Read Cycle (EDO page mode) The read timing in EDO page-mode lags 0.5 cycles behind that in fast page mode. S1C33210 FUNCTION PART CAS cycle Figure 4.29 DRAM Random Read Cycle CAS cycle #1 COL #1...
Page 180 CAS cycle write data CAS cycle #1 COL #1 write data CAS cycle #1 Undefined write data EPSON Precharge cycle Precharge CAS cycle #2 cycle COL #2 write data Precharge CAS cycle #2 cycle write data Undefined S1C33210 FUNCTION PART...
Page 181 • relinquishing of bus control is requested by an external bus master. Note: When using the successive RAS mode, always be sure to use #DRD for the read signal and #DWE for the low-byte write signal. S1C33210 FUNCTION PART II CORE BLOCK: BCU (Bus Control Unit) Deassert...
Page 182: Dram Refresh Cycles
6 cycles. B-II-4-30 CAS-before-RAS refresh cycle Fixed at Refresh 1 cycle RPC pulse width Figure 4.36 CAS-Before-RAS Refresh Self-refresh mode Fixed at 1 cycle Figure 4.37 Self-Refresh EPSON Precharge cycle Self-refresh mode deactivation Precharge cycle (6 cycles) S1C33210 FUNCTION PART...
Page 183: Releasing External Bus
The DMA transfer that has been kept pending is restarted when the CPU gains control of the bus ownership. S1C33210 FUNCTION PART The external bus master...
Page 184: Power-Down Control By External Device
#BUSREQ pin is released back high. Unlike in the case of ordinary releasing of the bus by #BUSREQ, the address bus and bus control signals are not placed in high-impedance state. For a DRAM refresh request that may arise in this HALT state, take one of the corrective measures described above. B-II-4-32 EPSON S1C33210 FUNCTION PART...
Page 185: I/O Memory Of Bcu
(HW) A14DRA A13DRA A14SZ A14DF1 A14DF0 – A14WT2 A14WT1 A14WT0 S1C33210 FUNCTION PART Function reserved Areas 18–17 device size selection 1 8 bits Areas 18–17 A18DF[1:0] Number of cycles output disable delay time reserved Areas 18–17 wait control A18WT[2:0] reserved Areas 16–15 device size selection...
Page 186 0 16 bits – Wait cycles – – 0 when being read. – – – 0 when being read. 0 Not used 0 Not used 0 16 bits – – – 0 when being read. Wait cycles S1C33210 FUNCTION PART...
Page 187 RCA0 RPC2 RPC1 RPC0 RRA1 RRA0 – SBUSST SEMAS SEPD SWAITE S1C33210 FUNCTION PART Function reserved Area 6 A6DF[1:0] Number of cycles output disable delay time reserved Area 6 wait control A6WT[2:0] reserved Areas 5–4 device size selection 1 8 bits Areas 5–4...
Page 188 0 when being read. 0 Disabled 0 Disabled – – 0 when being read. 0 Disabled – – 0 when being read. 0 4 cycles x2 speed mode only – – 0 when being read. BCLK PLL_CLK OSC3_CLK BCU_CLK CPU_CLK S1C33210 FUNCTION PART...
Page 189 ROM and the write cycle to the burst ROM area have wait cycles inserted that are set by AxxWT . Wait cycles derived from the #WAIT pin also can be inserted in the cycle for writing to the burst ROM area. S1C33210 FUNCTION PART Table 4.22 Output Disable Delay Time...
Page 190 ROM write cycle. For the burst ROM write cycle, the wait cycles set via the #WAIT pin can also be used. At cold start, A10BW is set to "0" (no wait cycle). At hot start, A10BW retains its status before being initialized. B-II-4-38 EPSON S1C33210 FUNCTION PART...
Page 191 The contents set here are applied to all of areas 14, 13, 8, and 7 that are set for DRAM. At cold start, REDO is set to "0" (fast-page mode). At hot start, REDO retains its status before being initialized. S1C33210 FUNCTION PART II CORE BLOCK: BCU (Bus Control Unit)
Page 192 The contents set here are applied to all of areas 14, 13, 8, and 7 that are set for DRAM. At cold start, RPC0 is set to "0" (1 cycle). At hot start, RPC0 retains its status before being initialized. B-II-4-40 Table 4.23 Column Address Size RCA1 RCA0 Column address size EPSON S1C33210 FUNCTION PART...
Page 193 CPU is placed in a HALT state, allowing for reduction in power consumption. At cold start, SEPD is set to "0" (disabled). At hot start, SEPD retains its status before being initialized. S1C33210 FUNCTION PART II CORE BLOCK: BCU (Bus Control Unit) Table 4.24 Refresh RAS Pulse Width...
Page 194 Table 4.25 #CE Output Assignment CEFUNC = "00" CEFUNC = "01" #CE4 #CE11 #CE5 #CE15 #CE6 #CE6 #CE7/#RAS0 #CE13/#RAS2 #CE8/#RAS1 #CE14/#RAS3 #CE9 #CE17 #CE10EX #CE10EX EPSON CEFUNC = "1x" #CE11+#CE12 #CE15+#CE16 #CE7+#CE8 #CE13/#RAS2 #CE14/#RAS3 #CE17+#CE18 #CE9+#CE10EX (Default: CEFUNC = "00") S1C33210 FUNCTION PART...
Page 195 The contents set here are applied to all of areas 14, 13, 8, and 7 that are set for DRAM. At cold start, RASC is set to "0" (1 cycle). At hot start, RASC retains its status before being initialized. S1C33210 FUNCTION PART II CORE BLOCK: BCU (Bus Control Unit)
Page 196 If AxxAS is set to "0", the signal output is disabled. At cold start, these bits are set to "0" (disabled). At hot start, these bits retain their status before being initialized. B-II-4-44 EPSON S1C33210 FUNCTION PART...
Page 197 4. When the CPU stops by the HALT or SLP instruction, this clock is also stopped. This clock is almost in phase with the bus clock. At initial reset, BCLKSEL is set to "0" (CPU_CLK). S1C33210 FUNCTION PART Table 4.29 Selection of BCLK Output Clock BCLKSEL0...
Page 198 Programming Notes The S1C33210 maps the mobile access interface registers to memory area 5. Accessing these registers therefore requires setting two bits to "1": A5IO, bit 8 in the access control register (0x0048132), and SWAITE, bit 0 in the bus control register (0x0048132).
Page 199: Itc (Interrupt Controller)
44 68(Base+110) Port input interrupt 4 45 69(Base+114) Port input interrupt 5 46 70(Base+118) Port input interrupt 6 47 71(Base+11C) Port input interrupt 7 S1C33210 FUNCTION PART II CORE BLOCK: ITC (Interrupt Controller) Table 5.1 List of Maskable Interrupts Interrupt factor...
Page 200 CPU. The other interrupts with lower priorities are kept pending until the above conditions are met. The PSR and interrupt control register will be detailed later. For details about interrupt factor generating conditions, refer to the description of each peripheral circuit in this manual. B-II-5-2 EPSON S1C33210 FUNCTION PART...
Page 201: Interrupt Factors And Intelligent Dma
If an interrupt to be generated upon completion of IDMA is disabled at the setting of the IDMA side, no interrupt request is signaled to the CPU. Therefore, the CPU remains idle until the next interrupt request is generated. S1C33210 FUNCTION PART II CORE BLOCK: ITC (Interrupt Controller) NMI and all maskable interrupts (except DMA interrupts)
Page 202: Trap Table
However, since an occurrence of NMI or the like between writes of the low-order and high-order half-words would cause a malfunction, it is recommended that the register be written in words. EPSON B-II-5-4 S1C33210 FUNCTION PART...
Page 203: Control Of Maskable Interrupts
IL is rewritten. The IL is restored to its previous status when the interrupt processing routine is terminated by the reti instruction. S1C33210 FUNCTION PART Interrupt factor flag Interrupt enable IDMA request...
Page 204: Interrupt Factor Flag And Interrupt Enable Register
For details about interrupt factor generating conditions, refer to the description of each peripheral circuit in this manual. B-II-5-6 EPSON S1C33210 FUNCTION PART...
Page 205 "0" (interrupts are disabled) or until some other interrupt factor of higher priority occurs. They are not cleared if the CPU simply accepts the interrupt request. S1C33210 FUNCTION PART II CORE BLOCK: ITC (Interrupt Controller)
Page 206: Interrupt Priority Register And Interrupt Levels
However, if the interrupt level of the IL is set below the current level and the IE is set to enable interrupts before resetting the interrupt factor flag after an interrupt has occurred, the same interrupt may occur again. B-II-5-8 EPSON S1C33210 FUNCTION PART...
Page 207: Idma Invocation
An IDMA invocation request is accepted even when the interrupt enable register and PSR of the CPU is set to disable interrupts. It is also necessary that the control information for the IDMA channel has been set. S1C33210 FUNCTION PART II CORE BLOCK: ITC (Interrupt Controller)
Page 208 (reset IDMA enable bit) IDMA request bit IDMA enable bit For details on IDMA, refer to "IDMA (Intelligent DMA)". B-II-5-10 Figure 5.2 Sequence when DINTEN = "1" "1" Figure 5.3 Sequence when DINTEN = "0" EPSON Interrupt request S1C33210 FUNCTION PART...
Page 209: Hsdma Invocation
Before HSDMA can be invoked by the occurrence of an interrupt factor, it is necessary that DMA be enabled on the HSDMA side by setting the control register for HSDMA transfer. For details about HSDMA, refer to "HSDMA (High-Speed DMA)". S1C33210 FUNCTION PART II CORE BLOCK: ITC (Interrupt Controller) Table 5.2 HSDMA Trigger Factor Ch.1 trigger factor...
Page 210: I/O Memory Of Interrupt Controller
0 when being read. 0 to 7 – – – 0 when being read. 0 to 7 – – – 0 when being read. 0 to 7 – – – 0 when being read. 0 to 7 S1C33210 FUNCTION PART...
Page 211 E16TC3 interrupt E16TU3 enable register D5–4 – E16TC2 E16TU2 D1–0 – S1C33210 FUNCTION PART II CORE BLOCK: ITC (Interrupt Controller) Function reserved 16-bit timer 5 interrupt level reserved 16-bit timer 4 interrupt level reserved Serial interface Ch.0 interrupt level reserved 8-bit timer 0–3 interrupt level...
Page 212 0 when being read. 0 No factor is generated – – – 0 when being read. – – – 0 when being read. 0 No factor is generated – – – 0 when being read. 0 No factor is generated S1C33210 FUNCTION PART...
Page 213 DEP6 port input 4–7 DEP5 IDMA enable DEP4 register – DEADE DESTX1 DESRX1 S1C33210 FUNCTION PART II CORE BLOCK: ITC (Interrupt Controller) Function reserved Port input 7 1 Factor is Port input 6 generated Port input 5 Port input 4...
Page 214 IDMA enable register set method 1 Set only selection IDMA request register set method 1 Set only selection Interrupt factor flag reset method 1 Reset only selection EPSON Setting Init. R/W Remarks – – – 0 RD/WR 0 RD/WR 0 RD/WR S1C33210 FUNCTION PART...
Page 215 TTBR27 TTBR26 TTBR25 TTBR24 TTBR23 TTBR22 TTBR21 TTBR20 S1C33210 FUNCTION PART II CORE BLOCK: ITC (Interrupt Controller) Function 8-bit timer 5 underflow 1 T8 Ch.5 UF 0 FP7 SIO Ch.3 transmit buffer empty 1 SIO Ch.3 TXD Emp. 8-bit timer 4 underflow 1 T8 Ch.4 UF 0 FP5...
Page 216 Areas 10–9 wait control A10WT[2:0] EPSON Setting Init. R/W Remarks – – – – 0 when being read. Wait cycles 0 Not used 0 Not used 0 16 bits – Wait cycles – – 0 when being read. S1C33210 FUNCTION PART...
Page 217 DMA transfer, the IDMA request register is reset to "0" and an interrupt request for the interrupt factor that enabled IDMA invoking is generated. After an initial reset, this register is set to "0" (Interrupt is requested). S1C33210 FUNCTION PART II CORE BLOCK: ITC (Interrupt Controller) EPSON...
Page 218 IDMA request bit can be reset by the hardware between the read and the write, so be careful when using this method. After an initial reset, IDMAONLY is set to "1" (set-only method). B-II-5-20 EPSON S1C33210 FUNCTION PART...
Page 219 Valid Set to "1" to use the SIO Ch.3 receive error interrupt. Set to "0" to use the FP2 input interrupt. At power-on, this bit is set to "0". S1C33210 FUNCTION PART II CORE BLOCK: ITC (Interrupt Controller) EPSON B-II-5-21...
Page 220 Write "1": 8-bit timer 5 underflow Write "0": FP7 input Read: Valid Set to "1" to use the 8-bit timer 5 underflow interrupt. Set to "0" to use the FP7 input interrupt. At power-on, this bit is set to "0". B-II-5-22 EPSON S1C33210 FUNCTION PART...
Page 221 Set to "1" to use the SIO Ch.2 receive error interrupt. Set to "0" to use the TM16 Ch.3 compare B interrupt. At power-on, this bit is set to "0". S1C33210 FUNCTION PART II CORE BLOCK: ITC (Interrupt Controller) EPSON...
Page 222 Before writing to the TTBR register, set TBRP to "0x59" to remove the write protection. Then when data is written to the most significant byte (0x48137) of the TTBR, the register once again becomes write-protected. After an initial reset, TBRP is set to "0x0" (write protected). B-II-5-24 EPSON S1C33210 FUNCTION PART...
Page 223: Programming Notes
(5) To prevent another interrupt from being generated for the same factor again after generation of an interrupt, be sure to reset the interrupt factor flag before enabling interrupts and setting the PSR again or executing the reti instruction. S1C33210 FUNCTION PART II CORE BLOCK: ITC (Interrupt Controller) EPSON...
Page 224 II CORE BLOCK: ITC (Interrupt Controller) THIS PAGE IS BLANK. EPSON B-II-5-26 S1C33210 FUNCTION PART...
Page 225: Clg (Clock Generator)
CPU and turn off the high-speed (OSC3) oscillation circuit in order to reduce current consumption. In addition, when SLEEP mode is set, the high-speed (OSC3) oscillation circuit is turned off, greatly reducing current consumption (no internal units except for the clock timer need to be operated). S1C33210 FUNCTION PART CLKDT[1:0] CLKCHG...
Page 226: I/O Pins Of Clock Generator
, respectively. EPSON Device includes built-in ROM Device includes built-in ROM When the PLL is not used, the OSC3 clock is used directly. OSC3 Oscillation circuit control signal SLEEP status (2) External clock input ) between the S1C33210 FUNCTION PART...
Page 227: Pll
(for 3.3-V crystal resonator, this time is 10 ms max.). To prevent the device from operating erratically, do not use the clock until its oscillation has stabilized. The high-speed (OSC3) oscillation circuit turns off when the CPU is set in SLEEP mode. S1C33210 FUNCTION PART Table 6.2 Setting the PLLS[1:0] Pins PLLS0...
Page 228: Setting And Switching Over The Cpu Operating Clock
Note: The operating clock switchover by CLKCHG is effective only when both oscillation circuits are on and the power-control register protection flag is set to "0b10010110". B-II-6-4 Table 6.3 Setting of CPU Operating Clock CLKDT0 Division ratio EPSON fout/8 fout/4 fout/2 fout/1 fout: PLL output S1C33210 FUNCTION PART...
Page 229: Power-Control Register Protection Flag
Note: The function for waiting until the high-speed (OSC3) oscillation is stabilized by 8T1ON is effective only when SLEEP mode is exited. Writing to 8T1ON is effective only when the power-control register protection flag is set to "0b10010110". S1C33210 FUNCTION PART II CORE BLOCK: CLG (Clock Generator) EPSON B-II-6-5...
Page 230: I/O Memory Of Clock Generator
Init. R/W Remarks Division ratio 0 Off – – Writing 1 not allowed. 0 OSC1 0 Off 0 Off – – – 0 when being read. 0 Off 0 On – – Do not write 1. 0 Off S1C33210 FUNCTION PART...
Page 231 "0" is written, the CPU will enter basic mode. Writing to HLT2OP is allowed only when CLGP[7:0] is set to "0b10010110". At initial reset, HLT2OP is set to "0" (basic mode). S1C33210 FUNCTION PART Table 6.5 Setting of CPU Operating Clock CLKDT0...
Page 232 • Reset, NMI • Enabled (not masked) input port interrupt factors • Clock timer interrupt when the low-speed oscillation circuit is being operated S1C33210 FUNCTION PART...
Page 233: Programming Notes
Therefore a restart occurs when the input level from the port is at the active level. Consequently, the system design should assume that a restart by means of port input from the SLEEP state or HALT2 state is performed by level. S1C33210 FUNCTION PART II CORE BLOCK: CLG (Clock Generator) EPSON B-II-6-9...
Page 234 II CORE BLOCK: CLG (Clock Generator) THIS PAGE IS BLANK. EPSON B-II-6-10 S1C33210 FUNCTION PART...
Page 235: Dbg (Debug Unit)
For connecting the S5U1C33000H, refer to the "S1C33 Family In-Circuit Debugger Manual". Furthermore, the pin status is fixed as shown in the above table after a user reset. S1C33210 FUNCTION PART Table 7.1 I/O Pins of Debug Circuit Initial status Voltage level –...
Page 236 II CORE BLOCK: DBG (Debug Unit) THIS PAGE IS BLANK. EPSON B-II-7-2 S1C33210 FUNCTION PART...
Page 237: Peripheral Block
S1C33210 FUNCTION PART PERIPHERAL BLOCK...
Page 239: Introduction
HDLC channel each). C33 DMA Block C33_DMA (IDMA, HSDMA) (CPU, BCU, ITC, CLG, DBG) C33_ADC (A/D converter) C33 Analog Block S1C33210 FUNCTION PART III PERIPHERAL BLOCK: INTRODUCTION C33 Internal Memory Block Internal RAM (Area 0) C33_CORE C33_SBUS C33 Core Block...
Page 240 III PERIPHERAL BLOCK: INTRODUCTION THIS PAGE IS BLANK. EPSON B-III-1-2 S1C33210 FUNCTION PART...
Page 241: Prescaler
PSCON to "0" to reduce current consumption. Note that stopping the prescaler (by setting PSCON to "0") stops the clock (the source clock) supplied to the prescaler. S1C33210 FUNCTION PART 1/16 1/32...
Page 242: Selecting Division Ratio And Output Control For Prescaler
Table 2.2 Division Ratio /256 /1024 /512 /256 EPSON Clock control bit P16TON0 (D3/0x40147) P16TON1 (D3/0x40148) P16TON2 (D3/0x40149) P16TON3 (D3/0x4014A) P16TON4 (D3/0x4014B) P16TON5 (D3/0x4014C) P8TON0 (D3/0x4014D) P8TON1 (D7/0x4014D) P8TON2 (D3/0x4014E) P8TON3 (D7/0x4014E) P8TON4 (D3/0x40145) P8TON5 (D7/0x40145) PSONAD (D3/0x4014F) /128 S1C33210 FUNCTION PART...
Page 243: I/O Memory Of Prescaler
D7–4 – clock control P16TON2 register P16TS22 P16TS21 P16TS20 S1C33210 FUNCTION PART Table 2.3 Control Bits of Prescaler Function reserved 8-bit timer 5 clock selection 8-bit timer 4 clock selection 8-bit timer 5 clock control 1 On 8-bit timer 5...
Page 244 /1024 /512 8-bit timer 1 can /256 generate the OSC3 /128 oscillation-stabilize waiting period. 0 Off Division ratio : selected by /256 Prescaler clock select /128 register (0x40181) 8-bit timer 0 can generate the DRAM refresh clock. S1C33210 FUNCTION PART...
Page 245 PSCON must not be set to "0" (Off) if any of the peripheral circuits (including the serial interface and ports) that use the clock supplied to the prescaler are in use. S1C33210 FUNCTION PART Function 8-bit timer 3 clock control...
Page 246 The desired division ratio can be selected from among the eight ratios shown on the I/O map. Note that the division ratio differs for each peripheral circuit. These bits can also be read out. At initial reset, all of these bits are set to "0b000" (highest frequency available). B-III-2-6 ([D[7:0]) / Power control protection register (0x4019E) EPSON S1C33210 FUNCTION PART...
Page 247: Programming Notes
(3) When the 16-bit and 8-bit programmable timers and the A/D converter do not need to be operated, turn off the clock supply to those peripheral circuits. This helps to reduce current consumption. (4) The peripheral circuits are as follows S1C33210 FUNCTION PART III PERIPHERAL BLOCK: PRESCALER EPSON...
Page 248 Turning off the prescaler turns off the clock signal supplied to the blocks in group 2 above. Also, if only some of the circuits in group 1 above are used, turn off all the other circuits and stop clock supply from the prescaler to those circuits. B-III-2-8 EPSON S1C33210 FUNCTION PART...
Page 249: 8-Bit Programmable Timers
8-bit programmable timer. At cold start, the register is set to input mode. At hot start, the register retains its status from prior to the reset. S1C33210 FUNCTION PART III PERIPHERAL BLOCK: 8-BIT PROGRAMMABLE TIMERS...
Page 250: Uses Of 8-Bit Programmable Timers
CPU can be started up by that underflow signal. To use this function, write "0" to the oscillation circuit control bit 8T1ON (D2) / Clock option register (0x40190) to enable the oscillation stabilization waiting function. B-III-3-2 EPSON S1C33210 FUNCTION PART...
Page 251 This enables the transfer rate of the serial interface to be programmed. Always write "0" to the serial interface control bit SSCK3 (D2) / Serial I/F Ch.3 control register (0x401F8) to select the internal clock. S1C33210 FUNCTION PART III PERIPHERAL BLOCK: 8-BIT PROGRAMMABLE TIMERS EPSON B-III-3-3...
Page 252: Control And Operation Of 8-Bit Programmable Timer
P8TSx = 1 P8TSx = 0 P8TCPK = 1 PSCIN PSCIN PSCIN /128 PSCIN PSCIN PSCIN PSCIN PSCIN PSCIN PSCIN PSCIN PSCIN PSCIN PSCIN PSCIN PSCIN PSCIN : Prescaler input clock frequency PSCIN S1C33210 FUNCTION PART PSCIN PSCIN PSCIN PSCIN PSCIN PSCIN...
Page 253 When the terminal count is reached and the counter underflows, the initial value is reloaded from the reload data register into the counter. S1C33210 FUNCTION PART III PERIPHERAL BLOCK: 8-BIT PROGRAMMABLE TIMERS [sec.]...
Page 254 Timer 3 data: PTD3[7:0] (D[7:0]) / 8-bit timer 3 counter data register (0x4016E) Timer 4 data: PTD4[7:0] (D[7:0]) / 8-bit timer 4 counter data register (0x40176) Timer 5 data: PTD5[7:0] (D[7:0]) / 8-bit timer 5 counter data register (0x4017A) B-III-3-6 0xA6 EPSON 0xF3 Reload and interrupt S1C33210 FUNCTION PART...
Page 255: Control Of Clock Output
3) The timer output is left as "0" when the timer output is turned on after setting the input clock and timer initial value. 4) When an underflow occurs after starting the timer, the port outputs a pulse with the same width as the 8-bit timer input clock pulse (prescaler's output). S1C33210 FUNCTION PART III PERIPHERAL BLOCK: 8-BIT PROGRAMMABLE TIMERS EPSON B-III-3-7...
Page 256: 8-Bit Programmable Timer Interrupts And Dma
For details on IDMA transfers and interrupt control upon completion of IDMA transfer, refer to "IDMA (Intelligent DMA)". B-III-3-8 Interrupt enable register E8TU0(D0/0x40275) E8TU1(D1/0x40275) E8TU2(D2/0x40275) E8TU3(D3/0x40275) Table 3.4 Control Bits for IDMA Transfer IDMA request bit IDMA enable bit DE8TU0(D2/0x40296) DE8TU1(D3/0x40296) DE8TU2(D4/0x40296) DE8TU3(D5/0x40296) EPSON Interrupt priority register P8TM[2:0](D[2:0]/0x40269) S1C33210 FUNCTION PART...
Page 257 Timer 2 underflow interrupt: 0x0C000D8 Timer 3 underflow interrupt: 0x0C000DC The base address of the trap table can be changed using the TTBR register (0x48134 to 0x48137). S1C33210 FUNCTION PART III PERIPHERAL BLOCK: 8-BIT PROGRAMMABLE TIMERS Table 3.5 HSDMA Trigger Set-up Bits Trigger set-up bits HSD0S[3:0] (D[3:0]) / HSDMA Ch.0/1 trigger set-up register (0x40298)
Page 258: I/O Memory Of 8-Bit Programmable Timers
0 Stop – – – 0 when being read. 0 Off 0 Invalid – 0 when being read. 0 Stop – – – 0 when being read. 0 Off 0 Invalid – 0 when being read. 0 Stop S1C33210 FUNCTION PART...
Page 259 PSIO02 interrupt PSIO01 priority register PSIO00 – P8TM2 P8TM1 P8TM0 S1C33210 FUNCTION PART III PERIPHERAL BLOCK: 8-BIT PROGRAMMABLE TIMERS Function Setting reserved 8-bit timer 3 clock output control 1 On 8-bit timer 3 preset 1 Preset 8-bit timer 3 Run/Stop control...
Page 260 – – Undefined when read. 0 P05, etc. Always set to 0. 0 P04, etc. Always set to 0. 0 P31, etc. 0 P21, etc. 0 P10, etc. P11, etc. P13, etc. 0 P12, etc. P14, etc. S1C33210 FUNCTION PART...
Page 261 There are two cases in which the reload data is loaded into the counter: when data is preset after "1" is written to PSETx, or when data is automatically reloaded upon counter underflow. At initial reset, RLD is not initialized. S1C33210 FUNCTION PART III PERIPHERAL BLOCK: 8-BIT PROGRAMMABLE TIMERS EPSON...
Page 262 While in a STOP state, the counter retains its count until it is preset with reload data or placed in a RUN state. When the state is changed from STOP to RUN, the counter can restart counting beginning with the retained count. At initial reset, PTRUNx is set to "0" (STOP). B-III-3-14 EPSON S1C33210 FUNCTION PART...
Page 263 When written using the reset-only method (default) Write "1": Interrupt factor flag is reset Write "0": Invalid When written using the read/write method Write "1": Interrupt flag is set Write "0": Interrupt flag is reset S1C33210 FUNCTION PART III PERIPHERAL BLOCK: 8-BIT PROGRAMMABLE TIMERS EPSON B-III-3-15...
Page 264 If the bit is set to "0", normal interrupt processing is performed and IDMA is not invoked. For details on IDMA, refer to "IDMA (Intelligent DMA)". At initial reset, R8TUx is set to "0" (interrupt request). B-III-3-16 EPSON S1C33210 FUNCTION PART...
Page 265: Programming Notes
(6) To prevent another interrupt from being generated again by the same factor after an interrupt has occurred, be sure to reset the interrupt factor flag (F8TUx) before setting the PSR again or executing the reti instruction. S1C33210 FUNCTION PART III PERIPHERAL BLOCK: 8-BIT PROGRAMMABLE TIMERS...
Page 266 III PERIPHERAL BLOCK: 8-BIT PROGRAMMABLE TIMERS THIS PAGE IS BLANK. EPSON B-III-3-18 S1C33210 FUNCTION PART...
Page 267: 16-Bit Programmable Timers
Thus the registers allow interrupt generating intervals and the timer's output clock frequency and duty ratio to be programmed. S1C33210 FUNCTION PART III PERIPHERAL BLOCK: 16-BIT PROGRAMMABLE TIMERS Comparison register A buffer (CRBxA)
Page 268: I/O Pins Of 16-Bit Programmable Timers
CFP22(D2)/P2 function select register(0x402D8) CFP23(D3)/P2 function select register(0x402D8) CFP24(D4)/P2 function select register(0x402D8) CFP25(D5)/P2 function select register(0x402D8) CFP26(D6)/P2 function select register(0x402D8) CFP27(D7)/P2 function select register(0x402D8) (I): Input mode, (O): Output mode, (Ex): Extended function EPSON Function select bit S1C33210 FUNCTION PART...
Page 269: Uses Of 16-Bit Programmable Timers
To use this function, write "1" to the watchdog timer control bit EWD (D1) / Watchdog timer enable register (0x40171) to enable the NMI. For details on how to control the watchdog timer, refer to "Watchdog Timer". S1C33210 FUNCTION PART III PERIPHERAL BLOCK: 16-BIT PROGRAMMABLE TIMERS...
Page 270: Control And Operation Of 16-Bit Programmable Timer
P16TS = 2 /256 PSCIN PSCIN PSCIN EPSON Clock control bit P16TON0 (D3) P16TON1 (D3) P16TON2 (D3) P16TON3 (D3) P16TON4 (D3) P16TON5 (D3) P16TS = 1 P16TS = 0 PSCIN PSCIN PSCIN : Prescaler input clock frequency S1C33210 FUNCTION PART...
Page 271 This comparison match signal controls the clock output (TMx signal) to external devices, in addition to generating an interrupt. The comparison data B is also used to reset the counter. S1C33210 FUNCTION PART III PERIPHERAL BLOCK: 16-BIT PROGRAMMABLE TIMERS EPSON...
Page 272 Timer 4 counter data: TC4[15:0] (D[F:0]) / 16-bit timer 4 counter data register (0x481A4) Timer 5 counter data: TC5[15:0] (D[F:0]) / 16-bit timer 5 counter data register (0x481AC) B-III-4-6 Comparison A Reset and Comparison A interrupt Comparison B interrupt EPSON Reset and interrupt Comparison B interrupt S1C33210 FUNCTION PART...
Page 273: Controlling Clock Output
Comparison match A signal Comparison match B signal TMx output (when OUTINVx = "0") TMx output (when OUTINVx = "1") Figure 4.3 Waveform of 16-Bit Programmable Timer Output S1C33210 FUNCTION PART III PERIPHERAL BLOCK: 16-BIT PROGRAMMABLE TIMERS PRUNx CRxA CRxB...
Page 274 0 1 2 3 4 5 0 1 2 3 4 5 0 1 Figure 4.4 Clock Output in Fine Mode - 1 = 32,767 and the range of CRxA that can be set is 0 to (2 EPSON 0 and B 1. The minimum settings 1/2. S1C33210 FUNCTION PART...
Page 275: 16-Bit Programmable Timer Interrupts And Dma
Timer 1 comparison B: Timer 2 comparison B: 0x0B Timer 3 comparison B: 0x0D Timer 4 comparison B: Timer 5 comparison B: S1C33210 FUNCTION PART III PERIPHERAL BLOCK: 16-BIT PROGRAMMABLE TIMERS Interrupt enable register E16TC0 (D3/0x40272) E16TU0 (D2/0x40272) E16TC1 (D7/0x40272)
Page 276 HSD3S[3:0] (D[7:4]) / HSDMA Ch.2/3 trigger set-up register (0x40299) = "1001" HSD1S[3:0] (D[7:4]) / HSDMA Ch.0/1 trigger set-up register (0x40298) = "1000" HSD3S[3:0] (D[7:4]) / HSDMA Ch.2/3 trigger set-up register (0x40299) = "1000" EPSON IDMA enable bit S1C33210 FUNCTION PART...
Page 277 Serial interface Ch.2 and Ch.3 share interrupt signals with the 16-bit timers. A register setting determined which is used. The initial setting is for use of the 16-bit timers. Refer to Section III-8, "Serial Interface", for details of the settings. S1C33210 FUNCTION PART III PERIPHERAL BLOCK: 16-BIT PROGRAMMABLE TIMERS 0x0C00078...
Page 278: I/O Memory Of 16-Bit Programmable Timers
0 when being read. 0 No factor is generated – – – 0 when being read. 0 No factor is generated – – – 0 when being read. 0 No factor is generated – – – 0 when being read. S1C33210 FUNCTION PART...
Page 279 CFP27 select register CFP26 CFP25 CFP24 CFP23 CFP22 CFP21 CFP20 S1C33210 FUNCTION PART III PERIPHERAL BLOCK: 16-BIT PROGRAMMABLE TIMERS Function Setting 16-bit timer 0 comparison A 1 IDMA 16-bit timer 0 comparison B request High-speed DMA Ch.1 High-speed DMA Ch.0...
Page 280 0 P21, etc. 0 P10, etc. P11, etc. P13, etc. 0 P12, etc. P14, etc. – – 0 when being read. 0 Normal 0 Disabled 0 Normal 0 Off 0 Invalid 0 when being read. 0 Stop S1C33210 FUNCTION PART...
Page 281 CR2A7 CR2A6 CR2A5 CR2A4 CR2A3 CR2A2 CR2A1 CR2A0 S1C33210 FUNCTION PART III PERIPHERAL BLOCK: 16-BIT PROGRAMMABLE TIMERS Function Setting 16-bit timer 1 comparison data A 0 to 65535 CR1A15 = MSB CR1A0 = LSB 16-bit timer 1 comparison data B...
Page 282 16-bit timer 3 comparison data B 0 to 65535 CR3B15 = MSB CR3B0 = LSB EPSON Init. R/W Remarks – – 0 when being read. 0 Normal 0 Disabled 0 Normal 0 Off 0 Invalid 0 when being read. 0 Stop S1C33210 FUNCTION PART...
Page 283 TC48 TC47 TC46 TC45 TC44 TC43 TC42 TC41 TC40 S1C33210 FUNCTION PART III PERIPHERAL BLOCK: 16-BIT PROGRAMMABLE TIMERS Function Setting 16-bit timer 3 counter data 0 to 65535 TC315 = MSB TC30 = LSB reserved 16-bit timer 3 fine mode selection...
Page 284 0 Normal 0 Disabled 0 Normal 0 Off 0 Invalid 0 when being read. 0 Stop – – 0 when being read. 0 Normal 0 Disabled 0 Normal 0 Off 0 Invalid 0 when being read. 0 Stop S1C33210 FUNCTION PART...
Page 285 8-bit programmable timer and cannot be used to receive an external clock. At cold start, all IOC1x is set to "0" (input mode). At hot start, IOC1x retains its state from prior to the initial reset. S1C33210 FUNCTION PART III PERIPHERAL BLOCK: 16-BIT PROGRAMMABLE TIMERS...
Page 286 By writing "1" to OUTINVx, an active-low signal (off level = high) is generated for the TMx output. When OUTINVx is set to "0", an active-high signal (off level = low) is generated. At initial reset, OUTINVx is set to "0" (active high). B-III-4-20 EPSON S1C33210 FUNCTION PART...
Page 287 The counter of timer x is reset by writing "1" to PRESETx. Writing "0" results in No Operation. Since PRESETx is a write-only bit, its content when read is always "0". S1C33210 FUNCTION PART III PERIPHERAL BLOCK: 16-BIT PROGRAMMABLE TIMERS EPSON...
Page 288 The data set in this register is compared with each corresponding counter data. When the contents match, a comparison B interrupt is generated and the output signal falls (OUTINVx = "0") or rises (OUTINVx = "1"). Furthermore, the counter is reset to "0". At initial reset, CRxB is not initialized. B-III-4-22 EPSON S1C33210 FUNCTION PART...
Page 289 When written using the reset-only method (default) Write "1": Interrupt factor flag is reset Write "0": Invalid When written using the read/write method Write "1": Interrupt flag is set Write "0": Interrupt flag is reset S1C33210 FUNCTION PART III PERIPHERAL BLOCK: 16-BIT PROGRAMMABLE TIMERS EPSON B-III-4-23...
Page 290 When the register is set to "0", normal interrupt processing is performed and IDMA is not invoked. For details on IDMA, refer to "IDMA (Intelligent DMA)". At initial reset, these bits are set to "0" (interrupt request). B-III-4-24 EPSON S1C33210 FUNCTION PART...
Page 291: Programming Notes
"0" is written to PTMx before setting the port to low. It can be prevented by writing "0" to PTMx after setting the port to low. S1C33210 FUNCTION PART III PERIPHERAL BLOCK: 16-BIT PROGRAMMABLE TIMERS 0 and B 1. The minimum settings are A 1/2.
Page 292 III PERIPHERAL BLOCK: 16-BIT PROGRAMMABLE TIMERS THIS PAGE IS BLANK. EPSON B-III-4-26 S1C33210 FUNCTION PART...
Page 293: Watchdog Timer
For the 16-bit programmable timer 0, set an appropriate comparison B value to make it start operating. If the watchdog timer function is not to be used, set EWD to "0" and do not change it. S1C33210 FUNCTION PART III PERIPHERAL BLOCK: WATCHDOG TIMER...
Page 294: Operation In Standby Modes
In SLEEP mode, the prescaler is turned off. Therefore, the watchdog timer also stops operating. To prevent generation of an unwanted NMI after clearing SLEEP mode, reset the 16-bit programmable timer 0 before executing the slp instruction. In addition, disable generation of the NMI by EWD as necessary. B-III-5-2 EPSON S1C33210 FUNCTION PART...
Page 295: I/O Memory Of Watchdog Timer
(2) Even when EWD is set to "0", the 16-bit programmable timer 0 does not stop counting. Therefore, if the NMI has been temporarily disabled, be sure to reset the 16-bit programmable timer 0 before setting EWD back to "1". S1C33210 FUNCTION PART III PERIPHERAL BLOCK: WATCHDOG TIMER Table 5.1 Control Bits of Watchdog Timer...
Page 296 III PERIPHERAL BLOCK: WATCHDOG TIMER THIS PAGE IS BLANK. EPSON B-III-5-4 S1C33210 FUNCTION PART...
Page 297: Low-Speed (Osc1) Oscillation Circuit
Low-speed (OSC1) oscillation output pin Crystal oscillation (open when external clock is used) P14/FOSC1/DCLK I/O I/O port / Low-speed (OSC1) oscillation clock output / DCLK signal output S1C33210 FUNCTION PART III PERIPHERAL BLOCK: LOW-SPEED (OSC1) OSCILLATION CIRCUIT OSC3/PLL clock PF1ON Clock timer Figure 6.1 Configuration of Clock System...
Page 298: Oscillator Types
OSC2 OSC1 Oscillation circuit OSC2 control signal (3) When not used EPSON OSC1 Oscillation circuit control signal (2) External clock input Low level ) between the OSC1 pin and V and leave the OSC2 pin open. S1C33210 FUNCTION PART...
Page 299: Controlling Oscillation
3. Switch over the CPU operating clock (by writing "1" to CLKCHG). Note: The operating clock switchover by CLKCHG is effective only when both oscillation circuits are on and the power-control register protection flag is set to "0b10010110". S1C33210 FUNCTION PART III PERIPHERAL BLOCK: LOW-SPEED (OSC1) OSCILLATION CIRCUIT EPSON...
Page 300: Power-Control Register Protection Flag
At initial reset, PF1ON is set to "0" (output disabled). PF1ON register FOSC1(P14) pin output B-III-6-4 Table 6.2 OSC1 Clock Output Pin CFP14(D4) / P1 function select register (0x402D4) CFEX0 (D0) / Port function extension register (0x402DF) Figure 6.3 OSC1 Clock Output EPSON Function select bit S1C33210 FUNCTION PART...
Page 301: I/O Memory Of Clock Generator
D7-6 – extension CFEX5 register CFEX4 CFEX3 CFEX2 CFEX1 CFEX0 S1C33210 FUNCTION PART III PERIPHERAL BLOCK: LOW-SPEED (OSC1) OSCILLATION CIRCUIT Table 6.3 Control Bits of Clock Generator Function System clock division ratio CLKDT[1:0] selection Prescaler On/Off control 1 On reserved...
Page 302 When "1" is written to HLT2OP, the CPU will enter HALT2 mode when the HALT instruction is executed. When "0" is written, the CPU will enter basic mode. Writing to HLT2OP is allowed only when CLGP[7:0] is set to "0b10010110". At initial reset, HLT2OP is set to "0" (basic mode). B-III-6-6 EPSON S1C33210 FUNCTION PART...
Page 303 "0b00000000" by one writing. Therefore, CLGP[7:0] must be set each time the protected address is written to. At initial reset, CLGP is set to "0b00000000" (write-protected). S1C33210 FUNCTION PART III PERIPHERAL BLOCK: LOW-SPEED (OSC1) OSCILLATION CIRCUIT Table 6.4 Operating Status in Standby Mode...
Page 304 This helps reduce current consumption. (6) When the P14/FOSC1/DCLK pin is used as the FOSC1 output pin, set IOC14 (D4/0x402D6) to "1" (output) in addition to the CFP14 (D4/0x402D4) and CFEX0 (D0/0x402DF) settings. B-III-6-8 EPSON S1C33210 FUNCTION PART...
Page 305: Clock Timer
OSC1 256 Hz OSC1 Divider oscillation circuit 32.768 kHz Clock timer Run/Stop Clock timer reset Interrupt request (to interrupt controller) S1C33210 FUNCTION PART Internal data bus 6-bit seconds counter Interrupt generation control circuit Interrupt/alarm select circuit Alarm generation control circuit Figure 7.1 Structure of Clock Timer...
Page 306: Control And Operation Of The Clock Timer
For the day counter, set a number of days starting from the reference day (e.g., January 1, 1990). B-III-7-2 Table 7.1 Presetting the Counters Data register (D[7:0]) / Clock timer day (low-order) register (0x40157) EPSON Preset value 0 to 59 0 to 23 0 to 65535 S1C33210 FUNCTION PART...
Page 307 8-bit binary counter was read. To prevent this problem, try reading out each counter several times and make sure data has not been modified. S1C33210 FUNCTION PART III PERIPHERAL BLOCK: CLOCK TIMER Table 7.2 Reading Out Counter Data...
Page 308: Interrupt Function
Table 7.4 Selecting Interrupt Factor TCISE2 TCISE1 TCISE0 Interrupt factor None 1 day 1 hour 1 minute 1 Hz 2 Hz 8 Hz 32 Hz EPSON 0 to 59 minutes* 0 to 23 hours* 0 to 31 days after S1C33210 FUNCTION PART...
Page 309 Trap vectors The trap vector addresses for the clock-timer interrupt by default are set to 0x0C00104. The trap table base address can be changed using the TTBR registers (0x48134 to 0x48137). S1C33210 FUNCTION PART III PERIPHERAL BLOCK: CLOCK TIMER EPSON...
Page 310: Examples Of Use Of Clock Timer
TCIF and alarm factor generation flag TCAF. If TCAF is set to 1, the interrupt has been caused by an alarm. If you select an interrupt factor (other than a 1-day factor) along with the hour-specified alarm, the selected interrupt factor occurs at the same time as the alarm factor. B-III-7-6 EPSON S1C33210 FUNCTION PART...
Page 311: I/O Memory Of Clock Timer
TCND15 day (high- TCND14 order) register TCND13 TCND12 TCND11 TCND10 TCND9 TCND8 S1C33210 FUNCTION PART Table 7.5 Control Bits of Clock Timer Function Setting reserved Clock timer reset 1 Reset Clock timer Run/Stop control 1 Run Clock timer interrupt factor...
Page 312 0 when being read. Compared with TCND[4:0]. – – – Writing 1 not allowed. 0 to 7 – – – 0 when being read. 0 Disabled – – – 0 when being read. 0 No factor is generated S1C33210 FUNCTION PART...
Page 313 If you the interrupt caused by these factors is not be used set TCISE to "111". TCISE is not initialized at initial reset. S1C33210 FUNCTION PART (D[7:0]) / Clock timer day (low-order) register (0x40157) Table 7.6 Selecting Interrupt Factor...
Page 314 Sets the priority level of the clock timer interrupt between 0 and 7. At initial reset, PCTM becomes indeterminate. B-III-7-10 Table 7.7 Selecting Alarm Factor TCASE2 TCASE1 TCASE0 Alarm factor Minute alarm Hour alarm Day alarm None EPSON S1C33210 FUNCTION PART...
Page 315 (RSTONLY = "1") is used, and "0" when the read/write method (RSTONLY = "0") is used. The FCTM flag becomes indeterminate at initial reset, so be sure to reset it in the software. S1C33210 FUNCTION PART III PERIPHERAL BLOCK: CLOCK TIMER...
Page 316: Programming Notes
(7) To prevent regeneration of interrupts with the same factor after an interrupt has occurred, be sure to reset the interrupt factor flag (FCTM) before setting the PSR again or executing the reti instruction. B-III-7-12 EPSON S1C33210 FUNCTION PART...
Page 317: Serial Interface
0 to 3. In this manual, however, channel numbers 0 to 3 are replaced with "x" unless discrimination is necessary, because explanations are common to all four channels. S1C33210 FUNCTION PART III PERIPHERAL BLOCK: SERIAL INTERFACE Internal data bus...
Page 318: I/O Pins Of Serial Interface
SSIN2(D[0:1])/Function select register(0x402DB) CFP26(D[6:0])/Function select register(0x402D8) SSOUT2(D[1:1])/Function select register(0x402DB) SSCLK2(D[2:1])/Function select register(0x402DB) CFP24(D[4:0])/Function select register(0x402D8) SSTDY2(D[3:1])/Function select register(0x402DB) When MSEL pin input is at Low level When MSEL pin input is at Low level EPSON Function select bit S1C33210 FUNCTION PART...
Page 319: Setting Transfer Mode
0x401E4, Ch.1: 0x401E9, Ch.2: 0x401F4, Ch.3: 0x401F9) is provided. Since these bits become indeterminate at initial reset, be sure to initialize them by writing "00" when using as the normal interface or "10" when using as the IrDA interface. S1C33210 FUNCTION PART III PERIPHERAL BLOCK: SERIAL INTERFACE Table 8.2 Transfer Mode...
Page 320: Clock-Synchronized Interface
Data input SINx Data output SOUTx Clock input #SCLKx Ready output #SRDYx D0 D1 D2 D3 D4 D5 D6 D7 EPSON External serial device Data input Data output Clock output Ready input (2) Slave mode S1C33210 FUNCTION PART...
Page 321: Setting Clock-Synchronized Interface
To ensure that the duty ratio of the clock to be fed to the serial interface is 50%, the 8-bit programmable timer further divides the underflow signal frequency by 2 internally. This 1/2 frequency division is factored into Eq. S1C33210 FUNCTION PART III PERIPHERAL BLOCK: SERIAL INTERFACE...
Page 322 Therefore, there is no need to control the prescaler or 8-bit programmable timer. Initialize SSCKx by writing "1" (#SCLKx). Note: SSCK11 and SSCK31 must be "0" because Ch. 1 and Ch. 3 support only asynchronous operation. B-III-8-6 (Eq. 1) EPSON S1C33210 FUNCTION PART...
Page 323: Control And Operation Of Clock-Synchronized Transfer
When data is transmitted successively in clock-synchronized master mode, TENDx maintains "1" until all data is transmitted (Figure 8.4). In slave mode, TENDx goes "0" every time 1-byte data is transmitted (Figure 8.5). Following explains transmit operation in both the master and slave modes. S1C33210 FUNCTION PART III PERIPHERAL BLOCK: SERIAL INTERFACE EPSON...
Page 324 SOUTx pin. B-III-8-8 Transmit-buffer empty interrupt request First data is written. Next data is written. Transmit-buffer empty interrupt request First data is written. Next data is written. EPSON S1C33210 FUNCTION PART...
Page 325 Ch.3 receive data: RXD3[7:0] (D[7:0]) / Serial I/F Ch.3 receive data register (0x401F6) The receive data can be read out from this register. A status bit is also provided that indicates the status of the receive data register. S1C33210 FUNCTION PART III PERIPHERAL BLOCK: SERIAL INTERFACE EPSON...
Page 326 B-III-8-10 1st data Receive-buffer full interrupt request A First data is read. 1st data Receive-buffer full Receive-buffer full interrupt request interrupt request EPSON 2nd data Receive-buffer full interrupt request 2nd data 3rd data Receive-buffer full interrupt request S1C33210 FUNCTION PART...
Page 327 (5) Terminating receive operation Upon completion of a data receive operation, write "0" to the receive-enable bit RXENx to disable receive operations. S1C33210 FUNCTION PART III PERIPHERAL BLOCK: SERIAL INTERFACE EPSON B-III-8-11...
Page 328: Asynchronous Interface
Serial data is transmitted and received, starting with the LSB. B-III-8-12 External S1C33 serial device Data input SINx Data output SOUTx (2) When internal clock is used s1: start bit, s2 & s3: stop bit, p: parity bit EPSON External serial device Data input Data output S1C33210 FUNCTION PART...
Page 329: Setting Asynchronous Interface
Therefore, before the internal clock can be used, the following conditions must be met: 1. The prescaler is outputting a clock to the 8-bit programmable timer 2 (or 3). 2. The 8-bit programmable timer 2 (or 3) is outputting a clock. S1C33210 FUNCTION PART III PERIPHERAL BLOCK: SERIAL INTERFACE EPSON...
Page 330 Error (%) 0.16025 1/16 0.16025 0.16025 0.16025 -1.35732 -1.35732 -1.35732 -1 } 100 [%] EPSON = 33 MHz PSCIN Error (%) Error (%) -0.14698 1/16 0.00640 -0.14698 0.00640 -0.14698 0.00640 -0.46939 -0.45234 -0.75584 0.46939 -3.11880 0.46939 -3.11880 0.46939 S1C33210 FUNCTION PART...
Page 331 When transmitting data, a sampling clock of a 50% duty cycle is generated from TCLK by dividing it by 16 (or 8), and each bit of data is output synchronously with this clock. S1C33210 FUNCTION PART III PERIPHERAL BLOCK: SERIAL INTERFACE...
Page 332: Control And Operation Of Asynchronous Transfer
Stop bit 2 bits 2 bits 2 bits 1 bit 1 bit 1 bit Setting PMDx is invalid when EPRx = "0". EPSON Ch.3 (Serial I/F Ch.3 control register) STPB3(D3/0x401F8) EPR3(D5/0x401F8) PMD3(D4/0x401F8) Parity bit Even None Even None S1C33210 FUNCTION PART...
Page 333 For details on how to control interrupts and IDMA requests, refer to "Serial Interface Interrupts and DMA". (3) Terminating transmit operations When data transmission is completed, write "0" to the transmit-enable bit TXENx to disable transmit operations. S1C33210 FUNCTION PART III PERIPHERAL BLOCK: SERIAL INTERFACE Start bit First data is written.
Page 334 The parity is checked when data is transferred to the receive data register (if EPRx = "1"). B-III-8-18 Parity bit First data is read. EPSON 1st data Receive-buffer full interrupt request S1C33210 FUNCTION PART...
Page 335 However, the content of the received data for which a framing error is flagged cannot be guaranteed, even if no framing error is found in the following data received. The FERx flag is reset to "0" by writing "0". S1C33210 FUNCTION PART III PERIPHERAL BLOCK: SERIAL INTERFACE EPSON...
Page 336 The OERx flag is reset to "0" by writing "0". (4) Terminating receive operation When a data receive operation is completed, write "0" to the receive-enable bit RXENx to disable receive operations. B-III-8-20 EPSON S1C33210 FUNCTION PART...
Page 337: Irda Interface
"0"), as a change in settings during operation could cause a malfunction. In addition, be sure to set the transfer mode in (3) and the following items before selecting the IrDA interface function in (2). S1C33210 FUNCTION PART III PERIPHERAL BLOCK: SERIAL INTERFACE Infrared communication module...
Page 338 Do not set. (reserved) Normal interface Ch.1 (Serial I/F Ch.1 Ch.2 (Serial I/F Ch.2 control register) IRRL1(D2/0x401E9) IRTL1(D3/0x401E9) Figure 8.15 IRRLx and IRTLx Settings EPSON Ch.3 (Serial I/F Ch.3 control register) control register) IRRL2(D2/0x401F4) IRRL3(D2/0x401F9) IRTL2(D3/0x401F4) IRTL3(D3/0x401F9) S1C33210 FUNCTION PART...
Page 339: Control And Operation Of Irda Interface
PPM modulator output (I/F input) Note: When using the IrDA interface, set the internal division ratio of the serial interface 1/16 (DIVMDx = "1"), rather than 1/8 (DIVMDx = "0"). S1C33210 FUNCTION PART III PERIPHERAL BLOCK: SERIAL INTERFACE TCLK 1 2 3 Figure 8.16 Data Modulation by PPM Circuit...
Page 340: Serial Interface Interrupts And Dma
(even if it is set to "0"). B-III-8-24 Interrupt factor flag Interrupt enable register FSERR0(D0/0x40286) ESERR0(D0/0x40276) FSRX0(D1/0x40286) ESRX0(D1/0x40276) FSTX0(D2/0x40286) ESTX0(D2/0x40276) FSERR1(D3/0x40286) ESERR1(D3/0x40276) FSRX1(D4/0x40286) ESRX1(D4/0x40276) FSTX1(D5/0x40286) ESTX1(D5/0x40276) EPSON Interrupt priority register PSIO0[2:0](D[6:4]/0x40269) PSIO1[2:0](D[2:0]/0x4026A) S1C33210 FUNCTION PART...
Page 341 IDMA side must also be set in advance. Channel Interrupt factor Ch.0 Receive-buffer full Transmit-buffer empty Ch.1 Receive-buffer full Transmit-buffer empty S1C33210 FUNCTION PART III PERIPHERAL BLOCK: SERIAL INTERFACE Port input interrupt factor FPT7 FPT5 FPT6 FPT4 FPT2...
Page 342 HSD0S[3:0] (D[3:0]) / HSDMA Ch.0/1 trigger set-up register (0x40298) HSD1S[3:0] (D[7:4]) / HSDMA Ch.0/1 trigger set-up register (0x40298) HSD2S[3:0] (D[3:0]) / HSDMA Ch.2/3 trigger set-up register (0x40299) HSD3S[3:0] (D[7:4]) / HSDMA Ch.2/3 trigger set-up register (0x40299) EPSON IDMA Ch. S1C33210 FUNCTION PART...
Page 343 Ch.2 and Ch.3 do not have dedicated interrupt signals. Either a port input interrupt or 16-bit timer interrupt is selected, and interrupt handling is performed accordingly. For details, refer to the "Trap Vector" subsection in the "16-Bit Programmable Timers" or "Input/Output Ports" section. S1C33210 FUNCTION PART III PERIPHERAL BLOCK: SERIAL INTERFACE 0x0C000E0 0x0C000E4...
Page 344: I/O Memory Of Serial Interface
0 1/16 0 Direct Valid only in 0 Direct asynchronous mode. I/F mode reserved IrDA 1.0 reserved General I/F R/W 7-bit asynchronous mode does not use TXD17. 7-bit asynchronous mode does not use RXD17 (fixed at 0). S1C33210 FUNCTION PART...
Page 345 Serial I/F Ch.2 00401F4 D7–5 – IrDA register DIVMD2 IRTL2 IRRL2 IRMD21 IRMD20 S1C33210 FUNCTION PART III PERIPHERAL BLOCK: SERIAL INTERFACE Function – Ch.1 transmit-completion flag 1 Transmitting 0 End Ch.1 flaming error flag 1 Error Ch.1 parity error flag 1 Error Ch.1 overrun error flag...
Page 346 – 0 when being read. 0 to 7 – – – 0 when being read. 0 to 7 – – – 0 when being read. 0 to 7 – – – 0 when being read. 0 Disabled S1C33210 FUNCTION PART...
Page 347 TM16 function switching T8CH4S1 register SIO3ES1 SIO2ES1 SIO3TS1 SIO3RS1 SIO2TS1 SIO2RS1 S1C33210 FUNCTION PART III PERIPHERAL BLOCK: SERIAL INTERFACE Function Setting reserved SIF Ch.1 transmit buffer empty 1 Factor is SIF Ch.1 receive buffer full generated SIF Ch.1 receive error SIF Ch.0 transmit buffer empty...
Page 348 0 P27/TM5 – Undefined when read. 0 P05, etc. Always set to 0. 0 P04, etc. Always set to 0. 0 P31, etc. 0 P21, etc. 0 P10, etc. P11, etc. P13, etc. 0 P12, etc. P14, etc. S1C33210 FUNCTION PART...
Page 349 To use the pin as SOUT2, set SSOUT2 (D1 / 0x402DB) to "1" and CFP26 (D6 / 0x402D8) to "0". To use the pin as P26 or TM4, set this bit to "0". At power-on, this bit is set to "0". S1C33210 FUNCTION PART III PERIPHERAL BLOCK: SERIAL INTERFACE EPSON...
Page 350 The serial-converted data is output from the SOUT pin beginning with the LSB, in which the bits set to "1" are output as high-level signals and those set to "0" output as low-level signals. This register can be read as well as written. At initial reset, the content of TXDx becomes indeterminate. B-III-8-34 EPSON S1C33210 FUNCTION PART...
Page 351 The FERx flag is reset by writing "0". At initial reset, as well as when RXENx and TXENx both are set to "0", the FERx flag is set to "0" (no error). S1C33210 FUNCTION PART III PERIPHERAL BLOCK: SERIAL INTERFACE...
Page 352 TDBEx is set to "0" when transmit data is written to the transmit data register, and is set to "1" when this data is transferred to the shift register (transmit operation started). Transmit data is written to the transmit data register when this bit = "1". At initial reset, TDBEx is set to "1" (buffer empty). B-III-8-36 EPSON S1C33210 FUNCTION PART...
Page 353 Always make sure the RXENx = "0" before setting the transfer mode and other conditions. At initial reset, RXENx is set to "0" (receive disabled). S1C33210 FUNCTION PART III PERIPHERAL BLOCK: SERIAL INTERFACE EPSON...
Page 354 STPBx is only valid in an asynchronous transfer. Two stop bits are selected by writing "1" to STPBx , and one stop bit is selected by writing "0". The start bit is fixed at 1 bit. Settings of STPBx are ignored during the performance of a clock-synchronized transfer. At initial reset, STPBx becomes indeterminate. B-III-8-38 EPSON S1C33210 FUNCTION PART...
Page 355 #SCLKx) by dividing it by 8. When DIVMDx is set to "0", the input clock is divided by 16. At initial reset, DIVMDx becomes indeterminate. S1C33210 FUNCTION PART III PERIPHERAL BLOCK: SERIAL INTERFACE Table 8.15 Setting of Transfer Mode...
Page 356 The interrupt priority level can be set for each channel in the range of 0 to 7. At initial reset, PSIOx becomes indeterminate. B-III-8-40 Table 8.16 IrDA Interface Setting IRMDx0 Interface mode Do not set. (reserved) IrDA 1.0 interface Do not set. (reserved) Normal interface EPSON S1C33210 FUNCTION PART...
Page 357 (RSTONLY = "1") is used, and "0" when the read/write method (RSTONLY = "0") is used. At initial reset, all of these flags become indeterminate, so be sure to reset them in the software. S1C33210 FUNCTION PART III PERIPHERAL BLOCK: SERIAL INTERFACE...
Page 358 Write "1": SIO Ch.2 receive error Write "0": FP0 input Read: Valid Set to "1" to use the SIO Ch.2 receive error interrupt. Set to "0" to use the FP0 input interrupt. At power-on, this bit is set to "0". B-III-8-42 EPSON S1C33210 FUNCTION PART...
Page 359 Read: Valid Set to "1" to use the 8-bit timer 4 underflow interrupt. Set to "0" to use the FP5 input interrupt. At power-on, this bit is set to "0". S1C33210 FUNCTION PART III PERIPHERAL BLOCK: SERIAL INTERFACE EPSON B-III-8-43...
Page 360 Write "0": TM16 Ch.4 compare B Read: Valid Set to "1" to use the SIO Ch.3 receive-buffer full interrupt. Set to "0" to use the TM16 Ch.4 compare B interrupt. At power-on, this bit is set to "0". B-III-8-44 EPSON S1C33210 FUNCTION PART...
Page 361 Set to "1" to use the 8-bit timer 5 underflow interrupt. Set to "0" to use the TM16 Ch.2 compare A interrupt. At power-on, this bit is set to "0". S1C33210 FUNCTION PART III PERIPHERAL BLOCK: SERIAL INTERFACE EPSON B-III-8-45...
Page 362: Programming Notes
(11) Serial interface operation requires that the prescaler be operating. B-III-8-46 "00"(normal I/F) or "10"(IrDA I/F) Transfer mode setting Data format and clock selection Internal division ratio, IrDA I/O logic and other settings Enable transmitting, receiving or both EPSON S1C33210 FUNCTION PART...
Page 363: Input/Output Ports
If there is a potential difference between AV may flow in the input buffer (when AV these ports are not used, when the input level is fixed externally, it should be fixed at V S1C33210 FUNCTION PART III PERIPHERAL BLOCK: INPUT/OUTPUT PORTS Input interrupt...
Page 364: Input-Port Pins
CFK50(D0)/K5 function select register(0x402C0) CFK51(D1)/K5 function select register(0x402C0) CFK52(D2)/K5 function select register(0x402C0) CFK60(D0)/K6 function select register(0x402C3) CFK61(D1)/K6 function select register(0x402C3) CFK62(D2)/K6 function select register(0x402C3) CFK63(D3)/K6 function select register(0x402C3) . If the input level is higher than power supply. or AV S1C33210 FUNCTION PART...
Page 365: I/O Memory Of Input Ports
) respectively. Since this register is a read-only register, writing to the register is ignored. When the ports set for A/D converter input are read, the value obtained is always "0". S1C33210 FUNCTION PART III PERIPHERAL BLOCK: INPUT/OUTPUT PORTS Table 9.2...
Page 366: I/O Ports (P Ports)
CFP13(D3)/P1 function select register(0x402D4) CFEX1(D1)/Port function extension register(0x402DF) CFP14(D4)/P1 function select register(0x402D4) CFEX0(D0)/Port function extension register(0x402DF) CFP15(D5)/P1 function select register(0x402D4) CFP16(D6)/P1 function select register(0x402D4) (I): Input mode, (O): Output mode, (Ex): Extended function EPSON Function select bit S1C33210 FUNCTION PART...
Page 367: I/O Control Register And I/O Modes
At hot start, the pins retain their state from prior to the reset. Note: If pins P10–P14, P15–P16, P30 and P34 are set for use with peripheral circuits, their pin functions vary depending on the input/output direction control by the IOC1x register. S1C33210 FUNCTION PART III PERIPHERAL BLOCK: INPUT/OUTPUT PORTS Function...
Page 368: I/O Memory Of I/O Ports
0 when being read. 0 P16 0 P15 0 P14 Extended functions (0x402DF) 0 P13 0 P12 0 P11 0 P10 – – – 0 when being read. 0 Low – – – 0 when being read. 0 Input S1C33210 FUNCTION PART...
Page 369 P3 I/O control 00402DE D7–6 – register IOC35 IOC34 IOC33 IOC32 IOC31 IOC30 S1C33210 FUNCTION PART III PERIPHERAL BLOCK: INPUT/OUTPUT PORTS Function Setting reserved P32 function selection 2 – P15 function selection 2 – P16 function selection 2 – P33 function selection 2 –...
Page 370 Always set to 0. 0 P04, etc. Always set to 0. 0 P31, etc. 0 P21, etc. 0 P10, etc. P11, etc. P13, etc. 0 P12, etc. P14, etc. level). level), "0" is read out as input S1C33210 FUNCTION PART...
Page 371 To use the pin as #SRDY2, set SSRDY2 (D3 / 0x402DB) to "1" and CFP24 (D4 / 0x402D8) to "0". To use the pin as P24 or TM2, set this bit to "0". At power-on, this bit is set to "0". S1C33210 FUNCTION PART III PERIPHERAL BLOCK: INPUT/OUTPUT PORTS EPSON...
Page 372 At cold start, CFEX0 and CFEX1 are set to "1" (function-extended pin) and other bits are set to "0" (I/O- port/peripheral-circuit pin). At hot start, CFEX retains its state from prior to the initial reset. B-III-9-10 EPSON S1C33210 FUNCTION PART...
Page 373: Input Interrupt
SPT2[1:0] (D[5:4])/Port input interrupt select register 1 (0x402C6) FPT1 SPT1[1:0] (D[3:2])/Port input interrupt select register 1 (0x402C6) FPT0 SPT0[1:0] (D[1:0])/Port input interrupt select register 1 (0x402C6) S1C33210 FUNCTION PART III PERIPHERAL BLOCK: INPUT/OUTPUT PORTS Interrupt signal generation Control bit EPSON...
Page 374 When the input signal goes to the selected status, the interrupt factor flag FP is set to "1" and, if other interrupt conditions set by the interrupt controller are met, an interrupt is generated. B-III-9-12 Table 9.6 Port Input Interrupt Condition SPPTx FPTx interrupt condition Rising edge Falling edge High level Low level EPSON S1C33210 FUNCTION PART...
Page 375: Key Input Interrupt
Address K60, CP0, P04, P24 K61, CP1, P05, P25 K62, CP2, P06, P26 K63, CP3, P07, P27 Figure 9.4 Configuration of Key Input Interrupt Circuit S1C33210 FUNCTION PART III PERIPHERAL BLOCK: INPUT/OUTPUT PORTS Interrupt signal generation Interrupt signal generation EPSON...
Page 376 K50, interrupt will be generated when non- conformity occurs between the contents of the four bits K51, K52, CP4 and the four bits input comparison register SCPK0[4:1]. EPSON SPPK settings P2[7:4] P0[5:4] CP[3:0] K6[3:0] P2[4:0] P0[4:0] K6[3:0] K5[2:0] S1C33210 FUNCTION PART...
Page 377: Control Registers Of The Interrupt Controller
For IDMA to be invoked, the IDMA request and IDMA enable bits shown in Table 9.9 must be set to "1" in advance. Transfer conditions, etc. must also be set on the IDMA side in advance. S1C33210 FUNCTION PART III PERIPHERAL BLOCK: INPUT/OUTPUT PORTS...
Page 378 Table 9.9 Control Bits for IDMA Transfer IDMA request bit IDMA enable bit RP7(D7/0x40293) DEP7(D7/0x40297) RP6(D6/0x40293) DEP6(D6/0x40297) RP5(D5/0x40293) DEP5(D5/0x40297) RP4(D4/0x40293) DEP4(D4/0x40297) RP3(D3/0x40290) DEP3(D3/0x40294) RP2(D2/0x40290) DEP2(D2/0x40294) RP1(D1/0x40290) DEP1(D1/0x40294) RP0(D0/0x40290) DEP0(D0/0x40294) 0x0C00040 0x0C00044 0x0C00048 0x0C0004C 0x0C00050 0x0C00054 0x0C00110 0x0C00114 0x0C00118 0x0C0011C EPSON S1C33210 FUNCTION PART...
Page 379: I/O Memory For Input Interrupts
Key input, 0040280 D7–6 – port input 0–3 interrupt factor flag register S1C33210 FUNCTION PART III PERIPHERAL BLOCK: INPUT/OUTPUT PORTS Table 9.10 Control Bits for Input Interrupts Function reserved Port input 1 interrupt level reserved Port input 0 interrupt level...
Page 380 0 Interrupt request – – – 0 when being read. 0 Interrupt request 0 IDMA disabled 0 IDMA disabled – – – 0 when being read. 0 IDMA disabled – Low level Falling edge 0 Level S1C33210 FUNCTION PART...
Page 381 Select an input pin for port interrupt generation. Table 9.11 Selecting Pins for Port Input Interrupts At cold start, SPT is set to "00". At hot start, SPT retains its state from prior to the initial reset. S1C33210 FUNCTION PART III PERIPHERAL BLOCK: INPUT/OUTPUT PORTS Function...
Page 382 At cold start, SCPK is set to "0" (rising edge). At hot start, SCPK retains its state from prior to the initial reset. B-III-9-20 Interrupt SPPK settings system FPK1 P2[7:4] P0[5:4] CP[3:0] K6[3:0] FPK0 P2[4:0] P0[4:0] K6[3:0] EPSON K5[2:0] S1C33210 FUNCTION PART...
Page 383 Interrupts for input systems set to "1" are enabled, and interrupts for input systems set to "0" are disabled. At initial reset, these bits are set to "0" (interrupt disabled). S1C33210 FUNCTION PART III PERIPHERAL BLOCK: INPUT/OUTPUT PORTS EPSON...
Page 384 Note also that the value to be written to reset the flag is "1" when the reset-only method (RSTONLY = "1") is used, and "0" when the read/write method (RSTONLY = "0") is used. At initial reset, all the flags become indeterminate, so be sure to reset them in the software. B-III-9-22 EPSON S1C33210 FUNCTION PART...
Page 385: Programming Notes
PSR or executing the reti instruction. (3) The S1C33210 maps the mobile access interface interrupt request outputs CP[4:0] to port interrupt requests. To use these interrupts, select them in port input interrupt select registers 1 and 2 (0x00402C6 and 0x00402C7) and configure them for High level active operation by setting the corresponding bits in the port input interrupt input polarity input select (0x00402C8) and port input interrupt edge/level select (0x00402C9) registers to "1"...
Page 386 (5) When a port input interrupt is used to trigger a restart from HALT2 mode or SLEEP mode, the interrupt will be generated by level detection, even if edge detection is set up. See the "Programming Notes" in the Core Block CLG section for details. B-III-9-24 EPSON S1C33210 FUNCTION PART...
Page 387: Mobile Access Interfaces
PDC processor: Packet processor: Data buffer: Figure 10.1 Mobile Access Interface Components S1C33210 FUNCTION PART III PERIPHERAL BLOCK: MONITORED MOBILE ACCESS INTERFACES ARQ frame processing for high-speed communications mode HDLC (packet) frame processing PIAFS frame processing for beara transfers at 32 kbps or 64 kbps UART communications using serial interface Ch.
Page 388: I/O Pins For Mobile Access Interfaces
MSEL pin input is at High level * MSEL pin input is at High level * MSEL pin input is at High level * MSEL pin input is at High level * MSEL pin input is at High level * EPSON Function Selection Bit S1C33210 FUNCTION PART...
Page 389 If the GOUTE bit in the communications block input port data register (D7/0x020000C) is "1," this output pin tracks the RI input pin. Otherwise, the output is fixed at High level. S1C33210 FUNCTION PART III PERIPHERAL BLOCK: MONITORED MOBILE ACCESS INTERFACES...
Page 390: Basic Settings For Mobile Access Interfaces
MOPORT2 MOPORT3 MOPORT3 PDCUPD PHSUPD MIPORT0 MIPORT0 PDCCLK PHSCLK PDCFRM PHSFRM MIPORT1 MIPORT1 PDCDWD PHSDWD CNT1 CNT1 CNT2 CNT2 GOUT GOUT fout/16 fout/15 fout/14 fout/13 fout/12 fout/11 fout/10 fout/9 fout/8 fout/7 fout/6 fout/5 fout/4 fout/3 fout/2 fout/2 S1C33210 FUNCTION PART...
Page 391 BHALF FMODE PIAFS frame period 5 ms Frame signal period DCD (frame signal) CTS (bit clock, 32 kHz) TXD and RXD (data signals) S1C33210 FUNCTION PART III PERIPHERAL BLOCK: MONITORED MOBILE ACCESS INTERFACES Table 10.4 Communications Mode Mode communications communications HDLC...
Page 392 Figure 10.3 PHS Signal Format (2) 32 kbps: 20 ms 125 s Figure 10.4 PHS Signal Format (3) 64 kbps: 10 ms 125 s Figure 10.5 PHS Signal Format (4) EPSON 125 s (Total 640 bits) 125 s (Total 640 bits) S1C33210 FUNCTION PART...
Page 393: Uart Communications Mode
In this mode as in others, setting the GOUTE bit in the communications block input port data register (D7/0x020000C) to "1" connects the RI input to the GOUT output pin. S1C33210 FUNCTION PART III PERIPHERAL BLOCK: MONITORED MOBILE ACCESS INTERFACES...
Page 394: Pdc Communications Mode
Although the device size is eight bytes, all reads and writes are in halfwords, so use only even addresses as shown in the next Figure. B-III-10-8 20 ms Transmit interval Receive interval Transmit data (224 bits) (224 bits) Receive data 0 1 2 3 4 5 6 7 EPSON (Total 224 bits) S1C33210 FUNCTION PART...
Page 395: Output Port Control
Note: Bits in the communications block modem status register (0x020002A) also track the input levels for the DSR and RI pins as well as transitions for triggering interrupt requests with changes in pin states. S1C33210 FUNCTION PART III PERIPHERAL BLOCK: MONITORED MOBILE ACCESS INTERFACES bit 7 ¥¥¥¥¥¥¥¥¥¥¥¥¥¥¥¥¥¥¥¥...
Page 396: Pdc Communications Control And Operation
PDC interrupt register (D1/0x0200100) is "1," this transition sends a PDC interrupt request to the CPU. The interrupt handler then checks the PDC command register for updates and the PDC status register. Note that the PDCINT bit remains "1" until the software writes "1" to it to clear it. B-III-10-10 EPSON S1C33210 FUNCTION PART...
Page 397: Phs Communications Mode
FI codes and SYNC patterns at the positions shown in the following Tables. Synchronization frame Negotiation frame Negotiation frame including synchronization frame functions SYNC Pattern S1C33210 FUNCTION PART III PERIPHERAL BLOCK: MONITORED MOBILE ACCESS INTERFACES 32 kbps: 20 ms 64 kbps: 10 ms 0 1 2 3 4 5 6 7 Table 10.6 FI Code Types...
Page 398 B-III-10-12 bit 15 ¥¥¥¥¥¥¥¥¥¥¥¥¥¥¥¥¥¥¥¥¥¥¥¥¥¥¥¥¥¥¥¥¥¥¥¥¥ Receive Buffer B (80 bytes) Receive Buffer A (80 bytes) Transmit Buffer B (80 bytes) Transmit Buffer A (80 bytes) PHS Communications Mode Data Buffers Serial data (608 bits) EPSON CRC-32 (32 bits) S1C33210 FUNCTION PART...
Page 399: Phs Communications Control And Operation
640-bit PIAFS frame and sets the RXINT bit in the PHS receive status register (D7/0x0200206). Note that the TXINT and RXINT bits remain "1" until the software writes "1" to the bit to clear it. S1C33210 FUNCTION PART III PERIPHERAL BLOCK: MONITORED MOBILE ACCESS INTERFACES EPSON...
Page 400: Hdlc Communications Mode
Note: Bits in the communications block modem status register (0x020002A) also track the input levels for the DSR and RI pins as well as transitions for triggering interrupt requests with changes in pin states. B-III-10-14 Control Field Data field 8 bits (arbitrary length) EPSON FCS (CRC) Flag 16 bits '01111110' S1C33210 FUNCTION PART...
Page 401: Hdlc Communications Control And Operation
Establishing Receive Address If the byte immediately following the opening flag pattern establishing flag synchronization is not a closing flag pattern, it is processed as the address field. S1C33210 FUNCTION PART III PERIPHERAL BLOCK: MONITORED MOBILE ACCESS INTERFACES EPSON B-III-10-15...
Page 402 CRC byte produces a back-to-back transmit sequence and further interrupt requests when the data level once again reaches the transmit queue threshold. Otherwise, the hardware issues a transmit interrupt and follows the CRC with a closing flag pattern. B-III-10-16 EPSON S1C33210 FUNCTION PART...
Page 403 Release the lock with an error reset command. Note that the software must read the HDLC Sp INT receive status register before the receive data register because reading the latter updates the former. S1C33210 FUNCTION PART III PERIPHERAL BLOCK: MONITORED MOBILE ACCESS INTERFACES EPSON...
Page 404: Mobile Access Interface Interrupts
Write "1" to the reset Tx INT bit B-III-10-18 Table 10.8 Interrupt Types Interrupt Types PDC interrupt PHS receive interrupt PHS transmit interrupt HDLC receive interrupt HDLC transmit interrupt HDLC Sp interrupt HDLC E/S interrupt Modem status change interrupt EPSON S1C33210 FUNCTION PART...
Page 405 3. Abort pattern detected A "0" in this bit indicates 1. Flag received in idle interval 2. Frame being received To clear Reset E/S INT command S1C33210 FUNCTION PART III PERIPHERAL BLOCK: MONITORED MOBILE ACCESS INTERFACES EPSON Error reset command B-III-10-19...
Page 406: Mobile Access Interface Interrupt Outputs
– – RXINT – – TXINT – – SPINT – – ESINT MSINT MSINT SPT setting – – – <CP4> EPSON communications communications PDCINT PRINT – PTINT – – – – MSINT MSINT <CP3> <CP2> <CP1> <CP0> S1C33210 FUNCTION PART...
Page 407: I/O Memory For Mobile Access Interfaces
D15–5 – block CP2 (HW) CP2EN4 interrupt select CP2EN3 register CP2EN2 CP2EN1 CP2EN0 S1C33210 FUNCTION PART III PERIPHERAL BLOCK: MONITORED MOBILE ACCESS INTERFACES Function – Communications macro select MCRS[1:0] – PHS block reset 1 Reset PDC block reset 1 Reset...
Page 408 0 Disable – – – 0 when being read. Write "1" to clear – – – 0 when being read. – – – 0 when being read. 0 Disable – – – 0 when being read. 0 Disable S1C33210 FUNCTION PART...
Page 409 – queue interrupt (HW) RXFTH2 threshold RXFTH1 register RXFTH0 S1C33210 FUNCTION PART III PERIPHERAL BLOCK: MONITORED MOBILE ACCESS INTERFACES Function – PHS receive interrupt flag 1 Request pending 0 No interrupts – PHS receive data CRC-32 error flag 1 CRC error...
Page 410 – 0 when being read. 0 Not detected 0 Not detected – – – 0 when being read. 0 Not detected – – – 0 when being read. 0 Not detected 0 Not available 0 Not detected S1C33210 FUNCTION PART...
Page 411 These bits, together with the MSEL external pin input, specify the communications mode and thus configures the I/O pin the I/O signals to match the target mobile device. U_OUTCNT(MSEL) S1C33210 FUNCTION PART III PERIPHERAL BLOCK: MONITORED MOBILE ACCESS INTERFACES Function –...
Page 412 PHS/PDC/HDLC block reset (D[2:0]) / Software reset register (0x0200002) Output pins Output level EPSON Data Transfer Figure Rate 32 kbps Figure 10.2 64 kbps Figure 10.3 32 kbps Figure 10.4 64 kbps Figure 10.5 32 kbps Figure 10.6 High High S1C33210 FUNCTION PART...
Page 413 Writes to these bits are ignored. Table 10.19 Communications Block Modem Status Input pin S1C33210 FUNCTION PART III PERIPHERAL BLOCK: MONITORED MOBILE ACCESS INTERFACES Output pins Output level...
Page 414 RI status hasn't changed from "0" to "1" SDRI status is reset Invalid SURI status is reset Invalid Bit Setting Output Pin Output Level RTS = 1 RTS = 0 DTR = 1 DTR = 0 EPSON High High S1C33210 FUNCTION PART...
Page 415 RXBB and RXBA indicate the buffer holding the data for the last receive operation completed. During normal, continuous operation, the "1" alternates between the two. Read "1": The buffer holds the data Read "0": The buffer holds no data S1C33210 FUNCTION PART III PERIPHERAL BLOCK: MONITORED MOBILE ACCESS INTERFACES EPSON B-III-10-29...
Page 416 Write "1": Interrupt enabled Write "0": Interrupt disabled Setting RXEN to "1" starts data storage in the currently selected receive buffer when hardware detects the FI code and SYNC pattern. Write "1": Receive enabled Write "0": Receive disabled B-III-10-30 EPSON S1C33210 FUNCTION PART...
Page 417 CRC byte. If not, the Tx INT is right after the transmission. Otherwise, the Tx INT is when the data level once again reaches the transmit queue threshold. S1C33210 FUNCTION PART III PERIPHERAL BLOCK: MONITORED MOBILE ACCESS INTERFACES EPSON...
Page 418 Read "0": Interrupt disabled Setting IDLDIES to "1" produces an E/S INT interrupt when the idle detect bit changes from "0" to "1." Write "1": Interrupt enabled Write "0": Invalid Read "1": Interrupt enabled Read "0": Interrupt disabled B-III-10-32 EPSON S1C33210 FUNCTION PART...
Page 419 Writing "1" to IDLDIEC disables E/S INT interrupts when the idle detect bit changes from "0" to "1." Write "1": Interrupt disabled Write "0": Invalid Read "1": Interrupt enabled Read "0": Interrupt disabled S1C33210 FUNCTION PART III PERIPHERAL BLOCK: MONITORED MOBILE ACCESS INTERFACES EPSON B-III-10-33...
Page 420 Read "0": Interrupt disabled Setting TXIES to "1" produces Tx INT interrupts when the transmit queue exceeds the threshold setting. Write "1": Interrupt disabled Write "0": Invalid Read "1": Interrupt enabled Read "0": Interrupt disabled B-III-10-34 EPSON S1C33210 FUNCTION PART...
Page 421 MRKFLG specifies the output pattern while transmit operation is disabled: flag ("0") or mark ("1"). The mark pattern fixes the output at High level. Write "1": Mark Write "0": Flag S1C33210 FUNCTION PART III PERIPHERAL BLOCK: MONITORED MOBILE ACCESS INTERFACES EPSON B-III-10-35...
Page 422 TXUDR goes to "1" when the hardware reads from an empty queue. It differs from TXUE above in that it merely indicates the status and does not trigger an interrupt request. To clear this bit, write "1" to RTXU in the HDLC transmit control register (D0/0x020031C). B-III-10-36 EPSON S1C33210 FUNCTION PART...
Page 423 These bits specify the queue level for triggering receive queue interrupts: 0 for the first byte entering the queue (receive character available), 3 for the fourth (half full), 7 for the eighth (full), etc. S1C33210 FUNCTION PART III PERIPHERAL BLOCK: MONITORED MOBILE ACCESS INTERFACES EPSON B-III-10-37...
Page 424 This command is only valid for the Rx INT and Sp INT on first receive character setting in RXINTS (D[1:0]/0x0200310). Write "1": Rx INT interrupt when the next byte enters the empty receive queue Write "0": Invalid B-III-10-38 EPSON S1C33210 FUNCTION PART...
Page 425 The software must read these bits by the end of the next frame because the hardware updates them at the end of each frame regardless of the RESID contents. S1C33210 FUNCTION PART III PERIPHERAL BLOCK: MONITORED MOBILE ACCESS INTERFACES Table 10.21 Residue Bits...
Page 426 Otherwise, the transition from "0" to "1" produces an E/S INT interrupt request and latches the bit until the next reset E/S INT command. If the idle state is still in effect, however, there is then another E/S INT interrupt request. Note that idle detection includes abort detection. B-III-10-40 EPSON S1C33210 FUNCTION PART...
Page 427 RXINT monitors the status of the Rx INT interrupt. TXINT monitors the status of the Tx INT interrupt. Reading this register returns the interrupt status at the time of the read. Writes to these bits are ignored. S1C33210 FUNCTION PART III PERIPHERAL BLOCK: MONITORED MOBILE ACCESS INTERFACES EPSON...
Page 428: Important Notes On Debugging
Communications therefore stops in a state that appears equivalent to stopping the clock. Setting the STOP bit to "0" produces normal communications interface operation even in ICD33 debugging mode. Note that the only inputs that the STOP bit controls this way are the three given above. EPSON B-III-10-42 S1C33210 FUNCTION PART...
Page 429: Analog Block
S1C33210 FUNCTION PART ANALOG BLOCK...
Page 431: Introduction
The analog block consists of a 10-bit A/D converter with 4 input channels. C33 DMA Block C33_DMA (IDMA, HSDMA) (CPU, BCU, ITC, CLG, DBG) C33_ADC (A/D converter) C33 Analog Block S1C33210 FUNCTION PART IV ANALOG BLOCK: INTRODUCTION C33 Internal Memory Block Internal RAM (Area 0) C33_CORE C33_SBUS C33 Core Block...
Page 432 IV ANALOG BLOCK: INTRODUCTION THIS PAGE IS BLANK. EPSON B-IV-1-2 S1C33210 FUNCTION PART...
Page 433: A/D Converter
• An interrupt is generated upon completion of A/D conversion. Figure 2.1 shows the structure of the A/D converter. Analog input decoder #ADTRG 8-bit timer 0 16-bit timer 0 S1C33210 FUNCTION PART and AV Successive Analog approximation block block Clock generator Figure 2.1 Structure of A/D Converter...
Page 434: I/O Pins Of A/D Converter
CFK52(D2)/K5 function select register(0x402C0) CFK60(D0)/K6 function select register(0x402C3) CFK61(D1)/K6 function select register(0x402C3) CFK62(D2)/K6 function select register(0x402C3) CFK63(D3)/K6 function select register(0x402C3) can be input in the range of V EPSON Function select bit – and V , and power S1C33210 FUNCTION PART...
Page 435: Setting A/D Converter
Conversion start channel: CS[2:0] (D[2:0]) / A/D channel register (0x40243) Conversion end channel: CE[2:0] (D[5:3]) / A/D channel register (0x40243) S1C33210 FUNCTION PART Table 2.2 Input Clock Selection PSAD1...
Page 436 However, this register should be used as set by default (ST = "11"; x9 clock periods). B-IV-2-4 CS1/CE1 CS0/CE0 Channel selected Table 2.4 Trigger Selection Trigger External trigger (K52/#ADTRG) 8-bit programmable timer 0 16-bit programmable timer 0 Software EPSON S1C33210 FUNCTION PART...
Page 437: Control And Operation Of A/D Conversion
A/D conversion is started by writing "1" to ADST (D1) / A/D enable register (0x40244). Only the trigger selected using TS[1:0] (D[4:3]) / A/D trigger register (0x40242) are valid; no other trigger is accepted. S1C33210 FUNCTION PART (When AD0 to AD2 are converted) Conversion...
Page 438 Note that A/D conversion cannot be stopped by writing "0" to ADE during a conversion (when ADST is "1"). Note: Once A/D conversion ends, further A/D conversion will not be performed correctly if restarted within an interval shorter than one cycle of the A/D converter operating clock set by the prescaler. B-IV-2-6 EPSON S1C33210 FUNCTION PART...
Page 439: A/D Converter Interrupt And Dma
If the A/D interrupt factor is selected as the HSDMA trigger, the HSDMA channel is invoked through generation of the interrupt factor. For details on HSDMA transfer, refer to "HSDMA (High-Speed DMA)". S1C33210 FUNCTION PART Table 2.5 HSDMA Trigger Set-up Bits Trigger set-up bits...
Page 440 IV ANALOG BLOCK: A/D CONVERTER Trap vector The A/D converter's interrupt trap-vector default address is set to 0x0C00100. The base address of the trap table can be changed using the TTBR register (0x48134 to 0x48137). B-IV-2-8 EPSON S1C33210 FUNCTION PART...
Page 441: I/O Memory Of A/D Converter
D7–4 – register ADST A/D sampling 0040245 D7–2 – register S1C33210 FUNCTION PART Table 2.6 Control Bits of A/D Converter Function A/D converted data 0x0 to 0x3FF (low-order 8 bits) (low-order 8 bits) ADD0 = LSB – A/D converted data...
Page 442 0 IDMA disabled – – – Undefined when read. Always set to 0. 0 CP4 0 K52 0 CP3 Always set to 0. 0 CP2 0 CP1 0 CP0 0 K63 0 K62 0 K61 0 K60 S1C33210 FUNCTION PART...
Page 443 If only one channel is to be A/D converted, set the same channel number in both the CS and CE bits. At initial reset, CS is set to "0" (AD0). S1C33210 FUNCTION PART (D[7:0]) / A/D conversion result (low-order) register (0x40240) Table 2.7 Trigger Selection...
Page 444 OWE is not set. Once OWE is set to "1", it remains set until it is reset by writing "0" in the software. At initial reset, OWE is set to "0" (normal). B-IV-2-12 EPSON S1C33210 FUNCTION PART...
Page 445 CPU is generated for the interrupt factor that has occurred. If interrupts are enabled at the setting of IDMA, an interrupt is generated under the above conditions after the data transfer by IDMA is completed. S1C33210 FUNCTION PART Table 2.8 Sampling Time Sampling Time...
Page 446 If DEADE is set to "1", the IDMA request by the interrupt factor is enabled. If this bit is set to "0", the IDMA request is disabled. After an initial reset, DEADE is set to "0" (IDMA disabled). B-IV-2-14 EPSON S1C33210 FUNCTION PART...
Page 447: Programming Notes
(readout in the state where the conversion completion flag, ADF, is "0"), OWE will not be set to "1" when ADD[9:0] is overwritten between the two read operations. S1C33210 FUNCTION PART IV ANALOG BLOCK: A/D CONVERTER and V...
Page 448 IV ANALOG BLOCK: A/D CONVERTER THIS PAGE IS BLANK. EPSON B-IV-2-16 S1C33210 FUNCTION PART...
Page 449: Dma Block
S1C33210 FUNCTION PART DMA BLOCK...
Page 451: Introduction
DMA command information. C33 DMA Block C33_DMA (IDMA, HSDMA) (CPU, BCU, ITC, CLG, DBG) C33_ADC (A/D converter) C33 Analog Block S1C33210 FUNCTION PART C33 Internal Memory Block Internal RAM (Area 0) C33_CORE C33_SBUS C33 Core Block C33_PERI (Prescaler, 8-bit timer, 16-bit timer,...
Page 452 V DMA BLOCK: INTRODUCTION THIS PAGE IS BLANK. EPSON B-V-1-2 S1C33210 FUNCTION PART...
Page 453: Hsdma (High-Speed Dma)
0 to 3 to distinguish them from other channels. In this manual, however, channel numbers 0 to 3 are designated with an "x" except where they must be distinguished, as the explanation is the same for all channels. S1C33210 FUNCTION PART Address bus Data bus...
Page 454: I/O Pins Of Hsdma
CFK50(D0)/K5 function select register(0x402C0) CFK51(D1)/K5 function select register(0x402C0) CFP15(D5)/P1 function select register(0x402D4) CFP16(D6)/P1 function select register(0x402D4) CFP32(D2)/P3 function select register(0x402DC) CFP33(D3)/P3 function select register(0x402DC) (I): Input mode, (O): Output mode, (Ex): Extended function EPSON Function select bit S1C33210 FUNCTION PART...
Page 455: Programming Control Information
Ch. 2 transfer data size (DE) / HSDMA Ch. 2 high-order source address set-up register (0x48246) DATSIZE3: Ch. 3 transfer data size (DE) / HSDMA Ch. 3 high-order source address set-up register (0x48256) S1C33210 FUNCTION PART V DMA BLOCK: HSDMA (High-Speed DMA) EPSON...
Page 456 Ch. 1 source address [27:16] (D[B:0]) / Ch. 1 high-order source address set-up register (0x48236) S2ADRH[11:0]: Ch. 2 source address [27:16] (D[B:0]) / Ch. 2 high-order source address set-up register (0x48246) S3ADRH[11:0]: Ch. 3 source address [27:16] (D[B:0]) / Ch. 3 high-order source address set-up register (0x48256) B-V-2-4 EPSON S1C33210 FUNCTION PART...
Page 457 The address is incremented by an amount equal to the data size set by DATSIZEx when one data transfer is completed. The address that has been incremented during transfer does not return to the initial value. S1C33210 FUNCTION PART V DMA BLOCK: HSDMA (High-Speed DMA)
Page 458: Setting The Registers In Single-Address Mode
In single-address mode, data transfer is performed between the memory connected to the system interface and an external I/O device. The I/O device is accessed directly by the #DMAACKx signal, so it is unnecessary to specify an address. DxADRL[15:0] and DxADRH[11:0] are not used in single-address mode. B-V-2-6 EPSON S1C33210 FUNCTION PART...
Page 459: Enabling/Disabling Dma Transfer
When HSx_EN is set to "0", HSDMA requests are no longer accepted. When a DMA transfer is completed (transfer counter = 0), HSx_EN is reset to "0" to disable the following trigger inputs. S1C33210 FUNCTION PART V DMA BLOCK: HSDMA (High-Speed DMA) EPSON...
Page 460: Trigger Factor
Port 3 input Port 7 input 8-bit timer 3 underflow 16-bit timer 3 compare B 16-bit timer 3 compare A 16-bit timer 5 compare B 16-bit timer 5 compare A Serial I/F Ch.1 Rx buffer full A/D conversion completion S1C33210 FUNCTION PART...
Page 461: Operation Of Hsdma
(4) The transfer counter is decremented. (5) The HSDMA enable bit HSx_EN is cleared and HSDMA interrupt factor flag in ITC is set when the transfer counter reaches 0 (when DINTENx = "1"). S1C33210 FUNCTION PART V DMA BLOCK: HSDMA (High-Speed DMA) START...
Page 462 (1 byte or 1 half word) Data write to destination (1 byte or 1 half word) : according to SxIN/DxIN Increments/decrements settings address Transfer counter - 1 Transfer counter = 0 Clear HSDMA enable bit HSx_EN Set interrupt factor flag FHDMx EPSON S1C33210 FUNCTION PART...
Page 463 (6) The transfer counter is decremented. (7) The HSDMA enable bit HSx_EN is cleared and HSDMA interrupt factor flag in ITC is set when the transfer counter reaches 0 (when DINTENx = "1"). S1C33210 FUNCTION PART V DMA BLOCK: HSDMA (High-Speed DMA) START...
Page 464: Operation In Single-Address Mode
When the transfer counter reaches 0, the end-of-transfer signal is output from the #DMAENDx pin indicating that a specified number of transfers has been completed. At the same time, the interrupt factor for the completion of HSDMA is generated. B-V-2-12 EPSON S1C33210 FUNCTION PART...
Page 465: Timing Chart
Read cycle BCLK COL #1 A[11:0] #RASx #HCAS/ #LCAS #DMAEND Figure 2.7 #DMAEND Signal Output Timing (DRAM) S1C33210 FUNCTION PART V DMA BLOCK: HSDMA (High-Speed DMA) destination address COL #2 COL #1 EPSON Write cycle Write cycle COL #2 B-V-2-13...
Page 466 Example: Page mode, RAS: 1 cycle; CAS: 2 cycles; Precharge: 1 cycle BCLK A[11:0] #RASx #CAS #DMAACK #DMAEND Figure 2.10 #DMAACK/#DMAEND Signal Output Timing (DRAM) B-V-2-14 addr addr[23:2] "00" "01" COL #1 EPSON "10" "11" COL #2 S1C33210 FUNCTION PART...
Page 467: Interrupt Function Of Hsdma
CPU actually accepts a HSDMA interrupt. For details about the interrupt control register and for the device operation when an interrupt occurs, refer to "ITC (Interrupt Controller)". S1C33210 FUNCTION PART V DMA BLOCK: HSDMA (High-Speed DMA)
Page 468 Note that the trap table base address can be modified using the TTBR registers (0x48134 to 0x48137). B-V-2-16 IDMA channel Table 2.4 Control Bits for IDMA Transfer IDMA request bit IDMA enable bit RHDM0(D4/0x40290) DEHDM0(D4/0x40294) RHDM1(D5/0x40290) DEHDM1(D5/0x40294) EPSON S1C33210 FUNCTION PART...
Page 469: I/O Memory Of Hsdma
DMA Ch. 0/1, DEHDM1 16-bit timer 0 DEHDM0 IDMA enable DEP3 register DEP2 DEP1 DEP0 S1C33210 FUNCTION PART V DMA BLOCK: HSDMA (High-Speed DMA) Table 2.5 Control Bits of HSDMA Function Setting reserved High-speed DMA Ch.1 interrupt level reserved High-speed DMA Ch.0...
Page 470 1 #DMAREQ1 0 K51 K50 function selection 1 #DMAREQ0 0 K50 EPSON Init. R/W Remarks – – – 0 when being read. 0 Invalid – – – Undefined when read. Always set to 0. 0 CP4 0 K52 S1C33210 FUNCTION PART...
Page 471 TC0_L2 TC0_L1 TC0_L0 BLKLEN07 BLKLEN06 BLKLEN05 BLKLEN04 BLKLEN03 BLKLEN02 BLKLEN01 BLKLEN00 S1C33210 FUNCTION PART V DMA BLOCK: HSDMA (High-Speed DMA) Function Setting reserved P16 function selection 1 1 EXCL5 #DMAEND1 P15 function selection 1 1 EXCL4 #DMAEND0 P14 function selection...
Page 472 S) Ch.0 memory address[27:16] D) Ch.0 destination address[15:0] S) Invalid EPSON Init. R/W Remarks 0 Single addr – – – – – – Undefined in read. – – – 0 Byte Inc/dec Inc.(no init) Inc.(init) Dec.(no init) Fixed S1C33210 FUNCTION PART...
Page 473 D) Dual address TC1_H6 mode TC1_H5 S) Single TC1_H4 address TC1_H3 mode TC1_H2 TC1_H1 TC1_H0 S1C33210 FUNCTION PART V DMA BLOCK: HSDMA (High-Speed DMA) Function Setting Ch.0 transfer mode D0MOD[1:0] D) Ch.0 destination address D0IN[1:0] control S) Invalid D) Ch.0 destination address[27:16]...
Page 474 D) Ch.1 source address control S1IN[1:0] S) Ch.1 memory address control D) Ch.1 source address[27:16] S) Ch.1 memory address[27:16] D) Ch.1 destination address[15:0] S) Invalid EPSON Init. R/W Remarks – – – 0 Byte Inc/dec Inc.(no init) Inc.(init) Dec.(no init) Fixed S1C33210 FUNCTION PART...
Page 475 D) Dual address TC2_H6 mode TC2_H5 S) Single TC2_H4 address TC2_H3 mode TC2_H2 TC2_H1 TC2_H0 S1C33210 FUNCTION PART V DMA BLOCK: HSDMA (High-Speed DMA) Function Setting Ch.1 transfer mode D1MOD[1:0] D) Ch.1 destination address D1IN[1:0] control S) Invalid D) Ch.1 destination address[27:16]...
Page 476 D) Ch.2 source address control S2IN[1:0] S) Ch.2 memory address control D) Ch.2 source address[27:16] S) Ch.2 memory address[27:16] D) Ch.2 destination address[15:0] S) Invalid EPSON Init. R/W Remarks – – – 0 Byte Inc/dec Inc.(no init) Inc.(init) Dec.(no init) Fixed S1C33210 FUNCTION PART...
Page 477 D) Dual address TC3_H6 mode TC3_H5 S) Single TC3_H4 address TC3_H3 mode TC3_H2 TC3_H1 TC3_H0 S1C33210 FUNCTION PART V DMA BLOCK: HSDMA (High-Speed DMA) Function Setting Ch.2 transfer mode D2MOD[1:0] D) Ch.2 destination address D2IN[1:0] control S) Invalid D) Ch.2 destination address[27:16]...
Page 478 D) Ch.3 source address control S3IN[1:0] S) Ch.3 memory address control D) Ch.3 source address[27:16] S) Ch.3 memory address[27:16] D) Ch.3 destination address[15:0] S) Invalid EPSON Init. R/W Remarks – – – 0 Byte Inc/dec Inc.(no init) Inc.(init) Dec.(no init) Fixed S1C33210 FUNCTION PART...
Page 479 If CFP1x is set to "0", the pin is set for an I/O port. At cold start, CFP1x is set to "0" (I/O port). At hot start, CFP1x retains the previous status before an initial reset. S1C33210 FUNCTION PART V DMA BLOCK: HSDMA (High-Speed DMA)
Page 480 When CFEXx is set to "0", the corresponding CFP bit becomes effective. At cold start, these bits are set to "0" (I/O-port/serial interface I/O pin). At hot start, these bits retain the previous status before an initial reset. B-V-2-28 EPSON S1C33210 FUNCTION PART...
Page 481 By reading HSx_TF, the flag status can be checked. Writing "1" to HSx_TF clears the trigger flag if the DMA transfer has not been started. At initial reset, HSx_TF is set to "0". S1C33210 FUNCTION PART V DMA BLOCK: HSDMA (High-Speed DMA) Table 2.6 HSDMA Trigger Factor Ch.1 trigger factor...
Page 482 Data transfer from an external I/O device to external memory is performed by writing "1" to DxDIR. Data transfer from external memory to an external I/O is performed by writing "0". At initial reset, DxDIR is set to "0" (memory to I/O). This bit is effective only in single-address mode. B-V-2-30 EPSON S1C33210 FUNCTION PART...
Page 483 However, if SxIN is set to "10", the source address that has been incremented during a block transfer recycles back to the initial value when the block transfer is completed. At initial reset, SxIN is set to "00" (Fixed). S1C33210 FUNCTION PART V DMA BLOCK: HSDMA (High-Speed DMA) Table 2.7 Transfer Mode...
Page 484 Be sure to disable DMA transfers (HSx_EN = "0") before writing and reading to and from the counter. At initial reset, these bits are not initialized. B-V-2-32 Table 2.9 Address Control DxIN0 Address control Increment without initialization Increment with initialization Decrement without initialization Fixed EPSON S1C33210 FUNCTION PART...
Page 485 PHSD3L2–PHSD3L0: Ch. 3 interrupt level (D[6:4]) / HSDMA Ch. 2/3 interrupt priority register (0x40264) Set the priority level of an end-of-DMA interrupt in the range of 0 to 7. At initial reset, these registers become indeterminate. S1C33210 FUNCTION PART V DMA BLOCK: HSDMA (High-Speed DMA) EPSON...
Page 486 (RSTONLY = "1") and "0" when using the read/write method (RSTONLY = "0"). Be careful not to confuse these two cases. The FHDMx flag becomes indeterminate when initially reset, so be sure to reset the flag in the software application. B-V-2-34 EPSON S1C33210 FUNCTION PART...
Page 487 "1", the IDMA request by the interrupt factor is enabled. If the bit is set to "0", the IDMA request is disabled. At initial reset, DEHDMx is set to "0" (IDMA disabled). S1C33210 FUNCTION PART V DMA BLOCK: HSDMA (High-Speed DMA)
Page 488: Programming Notes
If a DMA trigger occurs and DMA is invoked while the CPU is stopped after HALT mode execution, erroneous operation will result. Ensure that DMA is not invoked in HALT mode. In HALT2 mode, DMA is not invoked since the DMA and BCU clocks are stopped. B-V-2-36 EPSON S1C33210 FUNCTION PART...
Page 489: Idma (Intelligent Dma)
Note: The control information must be written only when the channel to be set does not start a DMA transfer. If a DMA transfer starts when the control information is being written to the RAM, proper transfer cannot performed. Reading the control information can always be done. S1C33210 FUNCTION PART V DMA BLOCK: IDMA (Intelligent DMA) 12 [bytes])
Page 490 Address decremented (In block transfer mode, the transfer address is updated without reset using the initial value.) Address fixed EPSON "1" = Enabled, "0" = Disabled "1" = Enabled, "0" = Disabled "1" = Half-word, "0" = Byte S1C33210 FUNCTION PART...
Page 491 BLKLEN. If a block transfer need to be performed a number of times as set by the transfer counter, an equal number of triggers are required. S1C33210 FUNCTION PART V DMA BLOCK: IDMA (Intelligent DMA) EPSON...
Page 492 Since the control information is placed in RAM, it can be rewritten. However, before rewriting the content of this information, make sure that no DMA transfer is generated in the channel whose information you are going to rewrite. B-V-3-4 EPSON S1C33210 FUNCTION PART...
Page 493: Idma Invocation
A/D converter End of A/D conversion Ports Port input 4 Port input 5 Port input 6 Port input 7 S1C33210 FUNCTION PART V DMA BLOCK: IDMA (Intelligent DMA) IDMA Ch. IDMA request bit RP0 (D0/0x40290) DEP0 (D0/0x40294) RP1 (D1/0x40290) DEP1 (D1/0x40294)
Page 494 To generate an interrupt at the end of an IDMA transfer, the DINTEN (end-of-transfer interrupt enable) bits in the IDMA control information for the first IDMA channel to be invoked and all the channels to be linked must be set to "1". B-V-3-6 DSTART (D7) / IDMA start register (0x48204) EPSON S1C33210 FUNCTION PART...
Page 495 IDMA transfer. The IDMA transfer by the hardware trigger is not executed since the interrupt factor is reset when the DMA transfer is completed. However, an operation like this cannot be recommended. S1C33210 FUNCTION PART V DMA BLOCK: IDMA (Intelligent DMA) EPSON...
Page 496: Operation Of Idma
B1 B2 B3 C E F1 F2 F3 Interrupt factor flag Reset ("0") Not changed ("1") Reset ("0") Not changed ("1") EPSON IDMA request bit IDMA enable bit Not changed ("1") Reset ("0") Not changed ("1") Reset ("0") S1C33210 FUNCTION PART...
Page 497 Condition Transfer counter "0": Transfer counter = "0", DINTEN = "1": Not changed ("1") Transfer counter = "0", DINTEN = "0": S1C33210 FUNCTION PART Base address + (Channel number B (3 words) C (Data read from source of transfer) D (Data write to destination of transfer)
Page 498 Interrupt factor flag Reset ("0") Not changed ("1") Reset ("0") Not changed ("1") EPSON 1-block transfer Cn Dn En H1 H2 H3 IDMA request bit IDMA enable bit Not changed ("1") Reset ("0") Not changed ("1") Reset ("0") S1C33210 FUNCTION PART...
Page 499 DMA transfer by the interrupt factor flag. Software trigger Data transfer Transfer counter DINTEN FIDMA (D4/0x40281) Interrupt request Figure 3.5 Operation when Invoked by Software Trigger S1C33210 FUNCTION PART V DMA BLOCK: IDMA (Intelligent DMA) EPSON B-V-3-11...
Page 500: Linking
TC = 1024 TC = 8 TC = 0 TC = 7 Figure 3.6 Example of Link Setting EPSON Ch.7 LNKEN = 0 LNKCHN = 9 DMOD = 10 DINTEN = 1 TC = 1 TC = 0 S1C33210 FUNCTION PART...
Page 501: Interrupt Function Of Intelligent Dma
IDMA interrupt level which is set by the interrupt priority register that the CPU actually accepts an IDMA interrupt request. For details about these interrupt control registers, and for information on device operation when an interrupt occurs, refer to "ITC (Interrupt Controller)". S1C33210 FUNCTION PART V DMA BLOCK: IDMA (Intelligent DMA) EPSON B-V-3-13...
Page 502: I/O Memory Of Intelligent Dma
0 to 7 – – – 0 when being read. 0 Disabled – – – 0 when being read. 0 No factor is generated – – – Undefined in read. 0 Stop – – – 0 Disabled S1C33210 FUNCTION PART...
Page 503 This bit controls the interrupt generated upon completion of IDMA transfer. The interrupt is enabled by setting this bit to "1" and disabled by setting this bit to "0". At initial reset, EIDMA is set to "0" (interrupt disable). S1C33210 FUNCTION PART V DMA BLOCK: IDMA (Intelligent DMA) EPSON...
Page 504 (RSTONLY = "1") and "0" when using the read/write method (RSTONLY = "0"). Be careful not to confuse these two cases. This flag becomes indeterminate when initially reset, so be sure to reset it in the software application. B-V-3-16 EPSON S1C33210 FUNCTION PART...
Page 505: Programming Notes
If a DMA trigger occurs and DMA is invoked while the CPU is stopped after HALT mode execution, erroneous operation will result. Ensure that DMA is not invoked in HALT mode. In HALT2 mode, DMA is not invoked since the DMA and BCU clocks are stopped. S1C33210 FUNCTION PART V DMA BLOCK: IDMA (Intelligent DMA) EPSON...
Page 506 V DMA BLOCK: IDMA (Intelligent DMA) THIS PAGE IS BLANK. EPSON B-V-3-18 S1C33210 FUNCTION PART...
Page 507: Appendix I/O Map
S1C33210 FUNCTION PART I/O MAP Appendix...
Page 509 0, 1: Initial values that are set at initial reset. (However, the registers for the bus and input/output ports are not initialized at hot start.) Not initialized at initial reset. –: Not set in the circuit. S1C33210 FUNCTION PART Function Setting reserved 8-bit timer 5 clock selection...
Page 510 /1024 /512 8-bit timer 1 can /256 generate the OSC3 /128 oscillation-stabilize waiting period. 0 Off Division ratio : selected by /256 Prescaler clock select /128 register (0x40181) 8-bit timer 0 can generate the DRAM refresh clock. S1C33210 FUNCTION PART...
Page 511 D7–6 – second TCMD5 register TCMD4 TCMD3 TCMD2 TCMD1 TCMD0 S1C33210 FUNCTION PART Function 8-bit timer 3 clock control 1 On 8-bit timer 3 P8TS3[2:0] clock division ratio selection 8-bit timer 2 clock control 1 On 8-bit timer 2 P8TS2[2:0]...
Page 512 – – 0 when being read. – – – 0 when being read. – – – 0 when being read. – – – 0 when being read. – – – 0 when being read. Compared with TCND[4:0]. S1C33210 FUNCTION PART...
Page 513 PTD26 register PTD25 PTD24 PTD23 PTD22 PTD21 PTD20 S1C33210 FUNCTION PART Function reserved 8-bit timer 0 clock output control 1 On 8-bit timer 0 preset 1 Preset 8-bit timer 0 Run/Stop control 1 Run 8-bit timer 0 reload data...
Page 514 – 0 when being read. 0 Stop 0 to 255 0 to 255 – – – 0 when being read. 0 Off 0 Invalid – 0 when being read. 0 Stop 0 to 255 0 to 255 S1C33210 FUNCTION PART...
Page 515 D6–0 – protect register Watchdog 0040171 D7–2 – timer enable register – S1C33210 FUNCTION PART Function EWD write protection 1 Write enabled 0 Write-protect – – Watchdog timer enable 1 NMI enabled 0 NMI disabled – EPSON APPENDIX: I/O MAP Setting Init.
Page 516 0 Off – – Writing 1 not allowed. 0 OSC1 0 Off 0 Off – – 0 OSC3/PLL – – – 0 when being read. 0 Off 0 On – – Do not write 1. 0 Off S1C33210 FUNCTION PART...
Page 517 00401E4 D7–5 – IrDA register DIVMD0 IRTL0 IRRL0 IRMD01 IRMD00 S1C33210 FUNCTION PART Function Serial I/F Ch.0 transmit data 0x0 to 0xFF(0x7F) TXD07(06) = MSB TXD00 = LSB Serial I/F Ch.0 receive data 0x0 to 0xFF(0x7F) RXD07(06) = MSB RXD00 = LSB –...
Page 518 I/F mode reserved IrDA 1.0 reserved General I/F – – – 0 when being read. 0 Normal Reset by writing 0. 0 Normal Reset by writing 0. 0 Normal Reset by writing 0. 0 Buffer full 0 Empty S1C33210 FUNCTION PART...
Page 519 Serial I/F Ch.3 00401F9 D7–5 – IrDA register DIVMD3 IRTL3 IRRL3 IRMD31 IRMD30 S1C33210 FUNCTION PART Function Ch.2 transmit enable 1 Enabled Ch.2 receive enable 1 Enabled Ch.2 parity enable 1 With parity Ch.2 parity mode selection 1 Odd Ch.2 stop bit selection 1 2 bits Ch.2 input clock selection...
Page 520 0 when being read. Reset when ADD is read. 0 Disabled 0 Stop 0 Normal Reset by writing 0. – – – 0 when being read. Sampring time Use with 9 clocks. 9 clocks 7 clocks 5 clocks 3 clocks S1C33210 FUNCTION PART...
Page 521 – interrupt P16T52 priority register P16T51 P16T50 – P16T42 P16T41 P16T40 S1C33210 FUNCTION PART Function reserved Port input 1 interrupt level reserved Port input 0 interrupt level reserved Port input 3 interrupt level reserved Port input 2 interrupt level reserved...
Page 522 0 when being read. 0 to 7 – – – 0 when being read. 0 to 7 – – – 0 when being read. 0 to 7 – – – 0 when being read. 0 to 7 S1C33210 FUNCTION PART...
Page 523 ESERR0 Port input 4–7, 0040277 D7–6 – clock timer, A/D interrupt enable register ECTM EADE S1C33210 FUNCTION PART Function reserved Key input 1 1 Enabled Key input 0 Port input 3 Port input 2 Port input 1 Port input 0...
Page 524 0 when being read. – – – 0 when being read. 0 No factor is generated – – – 0 when being read. 0 No factor is generated – – – 0 when being read. 0 No factor is generated S1C33210 FUNCTION PART...
Page 525 4–7 DEP5 IDMA enable DEP4 register – DEADE DESTX1 DESRX1 S1C33210 FUNCTION PART Function 16-bit timer 0 comparison A 1 IDMA 16-bit timer 0 comparison B request High-speed DMA Ch.1 High-speed DMA Ch.0 Port input 3 Port input 2...
Page 526 IDMA request register set method 1 Set only selection Interrupt factor flag reset method 1 Reset only selection EPSON Setting Init. R/W Remarks – – – 0 when being read. 0 Invalid – – – 0 RD/WR 0 RD/WR 0 RD/WR S1C33210 FUNCTION PART...
Page 527 K6 input port 00402C4 CP3D data register CP2D CP1D CP0D K63D K62D K61D K60D S1C33210 FUNCTION PART Function reserved 1 – K52 function selection 1 #ADTRG K51 function selection 1 #DMAREQ1 0 K51 K50 function selection 1 #DMAREQ0 0 K50 reserved –...
Page 528 0 Level – – – 0 when being read. K5[2:0] comp.A comp.B 0 TM16 Ch.3 comp.A 0 TM16 Ch.3 comp.B 0 TM16 Ch.4 comp.A 0 TM16 Ch.4 comp.B 0 TM16 Ch.5 comp.A 0 TM16 Ch.5 comp.B S1C33210 FUNCTION PART...
Page 529 P1 I/O port data 00402D5 – register P16D P15D P14D P13D P12D P11D P10D S1C33210 FUNCTION PART Function reserved FPK04 input comparison 1 High FPK03 input comparison FPK02 input comparison FPK01 input comparison FPK00 input comparison reserved FPK13 input comparison...
Page 530 0 P27/TM5 – – – 0 when being read. 0 P35 0 P34 0 P31 Ext. func.(0x402DF) 0 P30 – – – 0 when being read. 0 Low – – – 0 when being read. 0 Input S1C33210 FUNCTION PART...
Page 531 (HW) A14DRA A13DRA A14SZ A14DF1 A14DF0 – A14WT2 A14WT1 A14WT0 S1C33210 FUNCTION PART Function reserved P05 port extended function – P04 port extended function – P31 port extended function 1 #GARD P21 port extended function 1 #GAAS P10, P11, P13 port extended...
Page 532 0 16 bits – Wait cycles – – 0 when being read. – – – 0 when being read. 0 Not used 0 Not used 0 16 bits – – – 0 when being read. Wait cycles S1C33210 FUNCTION PART...
Page 533 RCA0 RPC2 RPC1 RPC0 RRA1 RRA0 – SBUSST SEMAS SEPD SWAITE S1C33210 FUNCTION PART Function reserved Area 6 A6DF[1:0] Number of cycles output disable delay time reserved Area 6 wait control A6WT[2:0] reserved Areas 5–4 device size selection 1 8 bits Areas 5–4...
Page 534 – 0 when being read. 0 External access – – 0 when being read. 0 External access 0 Little endian 0 when being read. Writing 1 not allowed. 0 when being read. Writing 1 not allowed. 0x0C0 S1C33210 FUNCTION PART...
Page 535 004813A D7–4 – register A1X1MD – BCLKSEL1 BCLKSEL0 S1C33210 FUNCTION PART Function Area 18, 17 address strobe signal 1 Enabled Area 16, 15 address strobe signal Area 14, 13 address strobe signal Area 12, 11 address strobe signal reserved Area 8, 7 address strobe signal...
Page 536 16-bit timer 0 reset 1 Reset 16-bit timer 0 Run/Stop control 1 Run EPSON Setting Init. R/W Remarks – – 0 when being read. 0 Normal 0 Disabled 0 Normal 0 Off 0 Invalid 0 when being read. 0 Stop S1C33210 FUNCTION PART...
Page 537 SELFM1 SELCRB1 OUTINV1 CKSL1 PTM1 PRESET1 PRUN1 S1C33210 FUNCTION PART Function 16-bit timer 1 comparison data A 0 to 65535 CR1A15 = MSB CR1A0 = LSB 16-bit timer 1 comparison data B 0 to 65535 CR1B15 = MSB...
Page 538 16-bit timer 2 reset 1 Reset 16-bit timer 2 Run/Stop control 1 Run EPSON Setting Init. R/W Remarks – – 0 when being read. 0 Normal 0 Disabled 0 Normal 0 Off 0 Invalid 0 when being read. 0 Stop S1C33210 FUNCTION PART...
Page 539 SELFM3 SELCRB3 OUTINV3 CKSL3 PTM3 PRESET3 PRUN3 S1C33210 FUNCTION PART Function 16-bit timer 3 comparison data A 0 to 65535 CR3A15 = MSB CR3A0 = LSB 16-bit timer 3 comparison data B 0 to 65535 CR3B15 = MSB...
Page 540 16-bit timer 4 reset 1 Reset 16-bit timer 4 Run/Stop control 1 Run EPSON Setting Init. R/W Remarks – – 0 when being read. 0 Normal 0 Disabled 0 Normal 0 Off 0 Invalid 0 when being read. 0 Stop S1C33210 FUNCTION PART...
Page 541 SELFM5 SELCRB5 OUTINV5 CKSL5 PTM5 PRESET5 PRUN5 S1C33210 FUNCTION PART Function 16-bit timer 5 comparison data A 0 to 65535 CR5A15 = MSB CR5A0 = LSB 16-bit timer 5 comparison data B 0 to 65535 CR5B15 = MSB...
Page 542 (Initial value: 0x0C003A0) IDMA start 1 IDMA start IDMA channel number reserved IDMA enable 1 Enabled EPSON Setting Init. R/W Remarks – – – Undefined in read. 0 Stop 0 to 127 – – – 0 Disabled S1C33210 FUNCTION PART...
Page 543 S0ADRH8 mode S0ADRH7 S0ADRH6 S0ADRH5 S0ADRH4 S0ADRH3 S0ADRH2 S0ADRH1 S0ADRH0 S1C33210 FUNCTION PART Function Ch.0 transfer counter[7:0] (block transfer mode) Ch.0 transfer counter[15:8] (single/successive transfer mode) Ch.0 block length (block transfer mode) Ch.0 transfer counter[7:0] (single/successive transfer mode) Ch.0 address mode selection...
Page 544 1 Set EPSON Setting Init. R/W Remarks Mode Invalid Block Successive Single Inc/dec Inc.(no init) Inc.(init) Dec.(no init) Fixed – – – Undefined in read. 0 Disable – – – Undefined in read. 0 No operation 0 Cleared S1C33210 FUNCTION PART...
Page 545 S1ADRH8 mode S1ADRH7 S1ADRH6 S1ADRH5 S1ADRH4 S1ADRH3 S1ADRH2 S1ADRH1 S1ADRH0 S1C33210 FUNCTION PART Function Ch.1 transfer counter[7:0] (block transfer mode) Ch.1 transfer counter[15:8] (single/successive transfer mode) Ch.1 block length (block transfer mode) Ch.1 transfer counter[7:0] (single/successive transfer mode) Ch.1 address mode selection...
Page 546 1 Set EPSON Setting Init. R/W Remarks Mode Invalid Block Successive Single Inc/dec Inc.(no init) Inc.(init) Dec.(no init) Fixed – – – Undefined in read. 0 Disable – – – Undefined in read. 0 No operation 0 Cleared S1C33210 FUNCTION PART...
Page 547 S2ADRH8 mode S2ADRH7 S2ADRH6 S2ADRH5 S2ADRH4 S2ADRH3 S2ADRH2 S2ADRH1 S2ADRH0 S1C33210 FUNCTION PART Function Ch.2 transfer counter[7:0] (block transfer mode) Ch.2 transfer counter[15:8] (single/successive transfer mode) Ch.2 block length (block transfer mode) Ch.2 transfer counter[7:0] (single/successive transfer mode) Ch.2 address mode selection...
Page 548 1 Set EPSON Setting Init. R/W Remarks Mode Invalid Block Successive Single Inc/dec Inc.(no init) Inc.(init) Dec.(no init) Fixed – – – Undefined in read. 0 Disable – – – Undefined in read. 0 No operation 0 Cleared S1C33210 FUNCTION PART...
Page 549 S3ADRH8 mode S3ADRH7 S3ADRH6 S3ADRH5 S3ADRH4 S3ADRH3 S3ADRH2 S3ADRH1 S3ADRH0 S1C33210 FUNCTION PART Function Ch.3 transfer counter[7:0] (block transfer mode) Ch.3 transfer counter[15:8] (single/successive transfer mode) Ch.3 block length (block transfer mode) Ch.3 transfer counter[7:0] (single/successive transfer mode) Ch.3 address mode selection...
Page 550 1 Set EPSON Setting Init. R/W Remarks Mode Invalid Block Successive Single Inc/dec Inc.(no init) Inc.(init) Dec.(no init) Fixed – – – Undefined in read. 0 Disable – – – Undefined in read. 0 No operation 0 Cleared S1C33210 FUNCTION PART...
Page 551 D15–5 – block CP3 (HW) CP3EN4 interrupt select CP3EN3 register CP3EN2 CP3EN1 CP3EN0 S1C33210 FUNCTION PART Function – Master configuration selection MCRS[1:0] – Reset PHS communications block 1 Reset Reset PDC communications block 1 Reset Reset HDLC communications block 1 Reset –...
Page 552 0 when being read. 0 Disable – – – 0 when being read. Write "1" to clear – – – 0 when being read. 0 No error 0 Buffer A – – – 0 when being read. S1C33210 FUNCTION PART...
Page 553 HDLC receive 0200310 D15–3 – queue interrupt (HW) RXFTH2 threshold RXFTH1 register RXFTH0 S1C33210 FUNCTION PART Function – HDLC error reset 1 Reset HDLC E/S interrupt reset 1 Reset – HDLC receive interrupt reset 1 Reset HDLC transmit interrupt reset 1 Reset –...
Page 554 – 0 when being read. 0 Not detected 0 Not detected – – – 0 when being read. 0 Not detected – – – 0 when being read. 0 Not detected 0 Not available 0 Not detected S1C33210 FUNCTION PART...
Page 555 HDLC monitor 0200336 D15–8 – register (HW) ESINT SPINT RXINT TXINT D3–0 – S1C33210 FUNCTION PART Function – Residue Code RCODE[7:0] Number of valid bits in excess 11111110 residue code bits at end of frame 11111100 11111000 11110000 11100000 11000000 10000000 –...
Page 556 EPSON HONG KONG LTD. 20/F., Harbour Centre, 25 Harbour Road Wanchai, Hong Kong Phone: +852-2585-4600 Fax: +852-2827-4346 Telex: 65542 EPSCO HX EPSON TAIWAN TECHNOLOGY & TRADING LTD. 10F, No. 287, Nanking East Road, Sec. 3 Taipei Phone: 02-2717-7360 Fax: 02-2712-9164 Telex: 24444 EPSONTB HSINCHU OFFICE 13F-3, No.
Page 558 In pursuit of “Saving” Technology, Epson electronic devices. Our lineup of semiconductors, displays and quartz devices assists in creating the products of our customers’ dreams. Epson IS energy savings.
Page 559 S1C33210 Technical Manual ELECTRONIC DEVICES MARKETING DIVISION EPSON Electronic Devices Website http://www.epsondevice.com Issue December, 2002 Printed in Japan...

Epson S1C33210 Technical Manual

Outline

Power Supply

Internal Memory

Peripheral Circuits

Power-Down Control

Basic External Wiring Diagram

Precautions on Mounting

Electrical Characteristics

Package

Pad Layout

Appendix A <Reference> External Device Interface Timings

Appendix B Pin Characteristics

Ioutline

Introduction

Block Diagram

List of Pins

Core Block

Introduction

Cpu and Operating Mode

Initial Reset

Bcu (Bus Control Unit)

ITC (Interrupt Controller)

CLG (Clock Generator)

DBG (Debug Unit)

Peripheral Block

Introduction

Prescaler

8-Bit Programmable Timers

16-Bit Programmable Timers

Watchdog Timer

Low-Speed (Osc1) Oscillation Circuit

Clock Timer

Serial Interface

Input/Output Ports

Mobile Access Interfaces

Analog Block

Introduction

A/D Converter

Dma Block

Introduction

Hsdma (High-Speed Dma)

IDMA (Intelligent DMA)

Appendix I/O Map

Quick Links

Related Manuals for Epson S1C33210

Summary of Contents for Epson S1C33210