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V DMA BLOCK: HSDMA (High-Speed DMA)
HS0_EN: Ch. 0 enable (D0) / HSDMA Ch. 0 enable register (0x4822C)
HS1_EN: Ch. 1 enable (D1) / HSDMA Ch. 1 enable register (0x4823C)
HS2_EN: Ch. 2 enable (D2) / HSDMA Ch. 2 enable register (0x4824C)
HS3_EN: Ch. 3 enable (D3) / HSDMA Ch. 3 enable register (0x4825C)
Enable a DMA transfer.
Write "1": Enabled
Write "0": Disabled
Read: Valid
DMA transfer is enabled by writing "1" to this bit.
HSDMA is placed in a state ready to accept a DMA request from the #DMAREQx pin or by the selected trigger
factor.
DMA transfer is disabled by writing "0" to this bit.
When DMA transfers are completed (transfer counter = 0), HSx_EN is cleared by the hardware.
Be sure to disable DMA transfers (HSx_EN = "0") before setting the transfer condition.
At initial reset, HSx_EN is set to "0" (disabled).
DUALM0: Ch. 0 address mode selection (DF) / HSDMA Ch. 0 control register (0x48222)
DUALM1: Ch. 1 address mode selection (DF) / HSDMA Ch. 1 control register (0x48232)
DUALM2: Ch. 2 address mode selection (DF) / HSDMA Ch. 2 control register (0x48242)
DUALM3: Ch. 3 address mode selection (DF) / HSDMA Ch. 3 control register (0x48252)
Select an address mode.
Write "1": Dual-address mode
Write "0": Single-address mode
Read: Valid
When "1" is written to DUALMx, the HSDMA channel enters dual-address mode that allows specification of source
and destination addresses. When "0" is written, the HSDMA channel enters single-address mode for high-speed data
transfer between the external memory and an I/O device.
At initial reset, DUALMx is set to "0" (single-address mode).
D0DIR: Ch. 0 transfer direction control (DE) / HSDMA Ch.0 control register (0x48222)
D1DIR: Ch. 1 transfer direction control (DE) / HSDMA Ch.1 control register (0x48232)
D2DIR: Ch. 2 transfer direction control (DE) / HSDMA Ch.2 control register (0x48242)
D3DIR: Ch. 3 transfer direction control (DE) / HSDMA Ch.3 control register (0x48252)
Control the direction of data transfer in single-address mode.
Write "1": Memory write (I/O to memory)
Write "0": Memory read (memory to I/O)
Read: Valid
Data transfer from an external I/O device to external memory is performed by writing "1" to DxDIR. Data transfer
from external memory to an external I/O is performed by writing "0".
At initial reset, DxDIR is set to "0" (memory to I/O).
This bit is effective only in single-address mode.
B-V-2-30
EPSON
S1C33210 FUNCTION PART
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