Phs Communications Control And Operation - Epson S1C33210 Technical Manual

PHS Communications Control and Operation

Transmit Control
(1) Enabling transmit operation
Setting the transmit enable (TXEN) bit in the PHS command register (D0/0x0200200) to "1" enables transmit
operation, starting transmission from the start of the specified transmit buffer using the PHS clock timing.
(2) Procedure
There are two 80-byte transmit data buffers. The transmit buffer select (TXBS) bit in the PHS command
register (D1/0x0200200) specifies which one contains the data to transmit: A ("0") or B ("1").
Before enabling the transmit operation, therefore, write the transmit data to buffer A, buffer B, or both and then
specify the buffer (TXBS) in the write (0x0200200) setting the transmit enable (TXEN) bit. For the next
transmit operation, write the data to the buffer not currently in use and then switch buffers (TXBS) in the write
(0x0200200) for starting the next transmit operation. Repeat as needed.
Note that the hardware does not automatically switch buffers.
(3) Ending transmit operation
To terminate transmit operation, set the TXEN bit to "0." Transmitting stops after the current 640 bits.
Note: Failing to write the data to the buffer before the transmit operation starts or overwriting buffer
contents during a transmit operation does not trigger an underrun error, overrun error, or other
warning.
Receive Control
(1) Enabling receive operation
Setting the receive enable (RXEN) bit in the PHS command register (D0/0x0200204) to "1" enables receive
operation, starting data storage in the currently selected receive buffer when hardware detects the FI code and
SYNC pattern.
(2) Procedure
When synchronization starts receive operation, the hardware starts converting the incoming serial data into
16-bit parallel data and storing it in a data buffer. It also starts the FCS(CRC) calculations.
When the hardware has received the 640 bits for a frame, it sets the RXBS bit in the PHS receive status register
(D1/0x0200206) to indicate which buffer contains the data and automatically switches to the other buffer.
The hardware also sets the CRCER bit in the PHS receive status register (D2/0x0200206) to the result of the
CRC-32 check. The data remains in the buffer regardless of any errors.
(3) Ending receive operation
To terminate receive operation, set the RXEN bit to "0."
Note: Failing to read the data from a buffer before the next receive operation for that buffer or reading from
a buffer while it is receiving data does not trigger an underrun error, overrun error, or other warning.
Interrupt Outputs
PHS communications uses two independent interrupts: PHS transmit and PHS receive.
Setting the TXINTE bit in the PHS transmit control register (D7/0x0200200) to "1" produces a PHS transmit
interrupt every time the hardware finishes sending a 640-bit PIAFS frame and sets the TXINT bit in the PHS
transmit status register (D7/0x0200202).
Setting the RXINTE bit in the PHS receive control register (D7/0x0200204) to "1" produces a PHS receive
interrupt every time the hardware finishes receiving a 640-bit PIAFS frame and sets the RXINT bit in the PHS
receive status register (D7/0x0200206).
Note that the TXINT and RXINT bits remain "1" until the software writes "1" to the bit to clear it.
S1C33210 FUNCTION PART
III PERIPHERAL BLOCK: MONITORED MOBILE ACCESS INTERFACES
EPSON
B-III-10-13