Epson S1C33210 Technical Manual page 95

DRAM random access cycle (basic cycle)
BCLK
A[23:0]
#RAS
#HCAS/
#LCAS
#RD
D[15:0]
#WE
D[15:0]
t
1 is measured with respect to the first signal change (negation) of either the #RD or the A[23:0] signals.
RDH
DRAM fast-page access cycle
RAS1
BCLK
t
AD
A[23:0]
#RAS
#HCAS/
#LCAS
#RD
D[15:0]
#WE
D[15:0]
t
1 is measured with respect to the first signal change (negation) of either the #RD or the A[23:0] signals.
RDH
S1C33210 PRODUCT PART
Data transfer #1
RAS1 CAS1
t t
AD AD
t
RASD1
t
RASW
t
CASD1
t
RDD1
t
RDW2
t
RACF
t
ACCF
t
WRD1
t
WRW2
t
WDD1
Data transfer #1
CAS1
t
AD
t
RASD1
t
CASD1
t
CASW
t
RDD1
t
t
RACF
t
ACCF
t
RDS
t
WRD1
t
WDD1
PRE1
(precharge)
t
AD
t
RASD2
t
CASD2
t
CASW
t
RDD3
t
CACF
1
t t
RDS RDH
t
WRD3
t
WDD2
Data transfer #2
CAS2 PRE1
t
AD
t
RASW
t
CASD2
t
RDW2
t
CACF ACCF
1
t t
RDH RDS
t
WRW2
t
WDD2
EPSON
8 ELECTRICAL CHARACTERISTICS
Next data transfer
RAS1' CAS1'
Next data transfer
RAS1'
(precharge)
t
RASD2
t
RDD3
1
t
RDH
t
WRD3
t
WDD2
A-81