Epson S1C33210 Technical Manual page 111

DRAM: 60ns, CPU: 33MHz, random read/write cycle
BCLK
A[11:0]
t
ASR
#RAS
#CAS
#RD
D[15:0](RD)
#WE
D[15:0](WR)
DRAM: 60ns, CPU: 33MHz, page-mode read/write cycle
BCLK
A[11:0]
#RAS
#CAS
#RD
D[15:0](RD)
#WE
D[15:0](WR)
DRAM: 60ns, CPU: 33MHz, CAS-before-RAS refresh cycle
RPC delay
BCLK
#RAS
#CAS
S1C33210 PRODUCT PART
APPENDIX A <REFERENCE> EXTERNAL DEVICE INTERFACE TIMINGS
RAS cycle
2
ROW #1
t
RAD
t
RAH
t
RCD
t
RAC
t
OAC
t
DS
WR data
RAS cycle
2
ROW #1
WR data
Fixed Refresh RAS pulse width
1 1
t t
RPC CSR
t
RC
CAS cycle RAS precharge
2
COL #1
t
ASC
t
RAS
t
CAS
t
AA
t
CAC
RD data
t
WP
t
DH
CAS cycle CAS cycle
2
COL #1 COL #2
t
RAS
t
CP
t
ACP
RD data
WR data
3
t
RAS
t
CHR
EPSON
2
ROW #2
t
RP
t
OFF
t
PC
RAS precharge
2 2
RD data
RAS precharge
2
A-97