Sram (55Ns - Epson S1C33210 Technical Manual

APPENDIX A <REFERENCE> EXTERNAL DEVICE INTERFACE TIMINGS
A.4 SRAM (55ns)
SRAM interface setup examples – 55ns
Operating
frequency Wait cycle
20MHz
25MHz
33MHz
SRAM interface timing – 55ns
SRAM interface
Parameter
<Read cycle>
Read cycle time
Address access time
#CE access time
#OE access time
Output disable delay time
<Write cycle>
Write cycle time
Address enable time
Write pulse width
Input data setup time
Input data hold time
SRAM: 55ns, CPU: 33/25MHz, read cycle
BCLK
A[23:0]
#CEx
D[15:0]
SRAM: 55ns, CPU: 33/25MHz, write cycle
A-102
Read cycle
Read cycle
1 2
2 3
2 3
Symbol Min.
t
RC
t
ACC
t
ACS
t
OE
t
OHZ
t
WC
t
AW
t
WP
t
DW
t
DH
t
RC
t
ACC
t
ACS
#RD
t
OE
BCLK
A[23:0]
#CEx
#WP
D[15:0]
Write cycle
2
3
3
33MHz
Max. Cycle Time
55 – 3
– 55 3
– 55 3
– 30 2.5
0 30 1.5
55 – 3
50 – 2.5
45 – 2
30 – 2
0 – 0.5
t
OHZ
RD data
t
WC
t
AW
t
WP
t t
DW
WR data
EPSON
Output disable
delay time
1.5
1.5
1.5
25MHz
Cycle Time Cycle
90 3 120
90 3 120
90 3 120
75 2.5 100
45 1.5 60
90 3 120
75 2.5 100
60 2 80
60 2 80
15 0.5 20
DH
S1C33210 PRODUCT PART
20MHz
Time
2 100
2 100
2 100
1.5 75
1.5 75
2 100
1.5 75
1 50
1 50
0.5 25