Epson S1C33210 Technical Manual page 398

III PERIPHERAL BLOCK: MONITORED MOBILE ACCESS INTERFACES
Data Buffers
PHS communications uses two 80-byte buffers each for transmitting and receiving. Transmit operation uses only
the 76 bytes at the start of a buffer; receive operation, all 80.
The transmit buffers are write only; the receive buffers, read only.
FCS (CRC) Checking
PHS communications uses the following CRC polynomial for validating frame data integrity.
CRC-32: G( )=1+
Figure 10.12 shows the range of application.
Serial data
Input for CRC-32 calculation (608 bits)
Frame data (640 bits)
Output Port Control
For communications macro select(MCRS) register(D[1:0]/0x200000) setings other than 00-that is,HDLC,
PDC,and PHS communications modes-the MOPORT3 and MOPORT2 bits in the communications block
output port data register(D[3:0]/0x020000A) drive the RTS and DTR pins using negative logic.
Input Port Monitoring
The MIPORT[1:0] bits in the communications block input port data register (D[1:0]/0x020000C) track the
input levels for the DSR and RI pins. Note that the block does not store these values internally.
In this mode as in others, setting the GOUTE bit in the communications block input port data register
(D7/0x020000C) to "1" connects the RI input to the GOUT output pin.
Note: Bits in the communications block modem status register (0x020002A) also track the input levels for
the DSR and RI pins as well as transitions for triggering interrupt requests with changes in pin
states.
B-III-10-12
bit 15 ¥¥¥¥¥¥¥¥¥¥¥¥¥¥¥¥¥¥¥¥¥¥¥¥¥¥¥¥¥¥¥¥¥¥¥¥¥
0x02007A0
0x020079F
0x0200750
0x020074F
0x0200700
0x02006FF
0x02006A0
0x020069F
0x0200650
0x020064F
0x0200600
Figure 10.11 PHS Communications Mode Data Buffers
1 2 4 5 7 8
+ + + + + +
Figure 10.12 PHS Communications Mode FCS (CRC) Position
Receive Buffer B
(80 bytes)
Receive Buffer A
(80 bytes)
Transmit Buffer B
(80 bytes)
Transmit Buffer A
(80 bytes)
10 11 12 16 22 23
+ + + + +
Serial data (608 bits)
EPSON
26 32
+ +
CRC-32 (32 bits)
S1C33210 FUNCTION PART