Sram Write Cycles - Epson S1C33210 Technical Manual

II CORE BLOCK: BCU (Bus Control Unit)

SRAM Write Cycles

Basic write cycle with no wait mode
BCLK
A[23:0]
#CExx
#WRH
#WRL
D[15:8]
D[7:0]
Figure 4.23 Byte Write Cycle with No Wait (A0 system, little endian)
BCLK
A[23:0]
#CExx
#BSH
#BSL
#WRL
D[15:8]
D[7:0]
Figure 4.24 Byte Write Cycle with No Wait (#BSL system, little endian)
B-II-4-20
C1
BCLK
A[23:0]
#CExx
D[15:0]
#WRH/#WRL
#WAIT
#WR
#BSL/#BSH
Figure 4.22 Half-word Write Cycle with No Wait
C1 C2
Undefined
Valid
C1 C2
Undefined
Valid
EPSON
C2
addr
data
C3 C4
addr
Valid
Undefined
C3 C4
addr
Valid
Undefined
S1C33210 FUNCTION PART