Epson S1C33210 Technical Manual page 494

V DMA BLOCK: IDMA (Intelligent DMA)
These interrupt factors are used in common for interrupt requests and IDMA invocation requests.
To invoke IDMA upon the occurrence of an interrupt factor, set the corresponding bits of the IDMA request
and IDMA enable registers shown in the table by writing "1". Then when an interrupt factor occurs, an interrupt
request to the CPU is kept pending and the corresponding IDMA channel is invoked.
The interrupt factor flag that has been set to "1" remains set until the DMA transfer invoked by it is completed.
If the following two conditions are met when one DMA transfer is completed, an interrupt request is generated
without resetting the interrupt factor flag.
• The transfer counter has reached 0.
• DINTEN in control information is set to "1" (interrupt enabled).
In this case, the IDMA request register is cleared to "0". Therefore, if IDMA needs to be invoked when an
interrupt factor occurs next time, this register must be set up again. To prevent unwanted IDMA requests from
being generated, this setting must be performed before enabling interrupts and after resetting the interrupt
factor flag. The IDMA enable bit is not cleared and remains set to "1".
If the transfer counter is not 0, the interrupt factor flag is reset when the DMA transfer is completed, so that no
interrupt is generated. In this case, the IDMA request bit and IDMA enable bit are not cleared and remain set to
"1".
When DINTEN in control information has been set to "0", the interrupt factor flag is reset even if the transfer
counter reaches 0, so that no interrupt is generated. In this case, the IDMA request bit is not cleared but the
IDMA enable bit is cleared.
If the IDMA request register bit is left reset to "0", the relevant interrupt factor generates an interrupt request
and not a IDMA request.
The control registers (interrupt enable register and interrupt priority register) corresponding to the interrupt
factor do not affect IDMA invocation. IDMA can be invoked even if the interrupt enable bit in ITC is set to "0"
(interrupt disabled). However, these register must be set to enable the interrupt when generating the interrupt
after completing the DMA transfer.
IDMA invocation by a trigger in the software application
All IDMA channels for which control information is set, including those corresponding to interrupt factors
described above, can be invoked by a trigger in the software application.
The following bits are used for this control:
IDMA channel number set-up: DCHN[6:0] (D[6:0]) / IDMA start register (0x48204)
IDMA start control:
When the IDMA channel number to be invoked (0 to 127) is written to DCHN and DSTART is set to "1", the
specified IDMA channel starts a DMA transfer.
DSTART remains set (= "1") during a DMA transfer and is reset to "0" in hardware when one DMA transfer
operation is completed.
Do not modify these bits during a DMA transfer.
If DINTEN is set to "1" (interrupt enabled), an interrupt factor for the completion of IDMA transfer is
generated when one DMA transfer is completed.
IDMA invocation by link setting
If LNKEN in the control information is set to "1" (link enabled), the IDMA channel that is set in the IDMA
link field "LNKCHN" is invoked successively after a DMA transfer in the link-enabled channel is completed.
The interrupt request by the first channel is generated after transfers in all linked channels are completed if the
interrupt conditions are met.
To generate an interrupt at the end of an IDMA transfer, the DINTEN (end-of-transfer interrupt enable) bits in
the IDMA control information for the first IDMA channel to be invoked and all the channels to be linked must
be set to "1".
B-V-3-6
DSTART (D7) / IDMA start register (0x48204)
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S1C33210 FUNCTION PART