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HSD0S3–HSD0S0: Ch. 0 trigger set-up (D[3:0]) / HSDMA Ch. 0/1 trigger set-up register (0x40298)
HSD1S3–HSD1S0: Ch. 1 trigger set-up (D[7:4]) / HSDMA Ch. 0/1 trigger set-up register (0x40298)
HSD2S3–HSD2S0: Ch. 2 trigger set-up (D[3:0]) / HSDMA Ch. 2/3 trigger set-up register (0x40299)
HSD3S3–HSD3S0: Ch. 3 trigger set-up (D[7:4]) / HSDMA Ch. 2/3 trigger set-up register (0x40299)
Select a trigger factor for each HSDMA channel.
Value
Ch.0 trigger factor
0000
Software trigger
0001
K50 port input (falling edge)
0010
K50 port input (rising edge)
0011
Port 0 input
0100
Port 4 input
0101
8-bit timer 0 underflow
0110
16-bit timer 0 compare B
0111
16-bit timer 0 compare A
1000
16-bit timer 4 compare B
1001
16-bit timer 4 compare A
1010
Serial I/F Ch.0 Rx buffer full
1011
Serial I/F Ch.0 Tx buffer empty Serial I/F Ch.1 Tx buffer empty Serial I/F Ch.0 Tx buffer empty Serial I/F Ch.1 Tx buffer empty
1100
A/D conversion completion
At initial reset, HSDxS is set to "0000" (software trigger).
HST0: Ch. 0 software trigger (D0) / HSDMA software trigger register (0x4029A)
HST1: Ch. 1 software trigger (D1) / HSDMA software trigger register (0x4029A)
HST2: Ch. 2 software trigger (D2) / HSDMA software trigger register (0x4029A)
HST3: Ch. 3 software trigger (D3) / HSDMA software trigger register (0x4029A)
Start a DMA transfer.
Write "1": Trigger
Write "0": Invalid
Read: Invalid
Writing "1" to HSTx generates a trigger pulse that starts a DMA transfer.
HSTx is effective only when software trigger is selected as the trigger factor of the HSDMA channel by the HSDxS
bits.
At initial reset, HSTx is set to "0".
HS0_TF: Ch. 0 trigger flag clear/status (D0) / HSDMA Ch. 0 trigger flag register (0x4022E)
HS1_TF: Ch. 1 trigger flag clear/status (D0) / HSDMA Ch. 1 trigger flag register (0x4023E)
HS2_TF: Ch. 2 trigger flag clear/status (D0) / HSDMA Ch. 2 trigger flag register (0x4024E)
HS3_TF: Ch. 3 trigger flag clear/status (D0) / HSDMA Ch. 3 trigger flag register (0x4025E)
These bits are used to check and clear the trigger flag status.
Write "1": Trigger flag clear
Write "0": Invalid
Read "1": Trigger flag has been set
Read "0": Trigger flag has been cleared
The trigger flag is set when the trigger factor is input to the HSDMA channel and is cleared when the HSDMA
channel starts a data transfer. By reading HSx_TF, the flag status can be checked. Writing "1" to HSx_TF clears the
trigger flag if the DMA transfer has not been started.
At initial reset, HSx_TF is set to "0".
S1C33210 FUNCTION PART
Table 2.6 HSDMA Trigger Factor
Ch.1 trigger factor
Software trigger
K51 port input (falling edge)
K51 port input (rising edge)
Port 1 input
Port 5 input
8-bit timer 1 underflow
16-bit timer 1 compare B
16-bit timer 1 compare A
16-bit timer 5 compare B
16-bit timer 5 compare A
Serial I/F Ch.1 Rx buffer full
A/D conversion completion
EPSON
V DMA BLOCK: HSDMA (High-Speed DMA)
Ch.2 trigger factor
Software trigger
–
–
Port 2 input
Port 6 input
8-bit timer 2 underflow
16-bit timer 2 compare B
16-bit timer 2 compare A
16-bit timer 4 compare B
16-bit timer 4 compare A
Serial I/F Ch.0 Rx buffer full
A/D conversion completion
Ch.3 trigger factor
Software trigger
–
–
Port 3 input
Port 7 input
8-bit timer 3 underflow
16-bit timer 3 compare B
16-bit timer 3 compare A
16-bit timer 5 compare B
16-bit timer 5 compare A
Serial I/F Ch.1 Rx buffer full
A/D conversion completion
B-V-2-29
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