I/O Memory Of Hsdma - Epson S1C33210 Technical Manual

I/O Memory of HSDMA

Table 2.5 shows the control bits of HSDMA.
Register name Address Bit
High-speed 0040263 D7
DMA Ch.0/1 (B) D6
interrupt D5
priority register D4
D3
D2
D1
D0
High-speed 0040264 D7
DMA Ch.2/3 (B) D6
interrupt D5
priority register D4
D3
D2
D1
D0
DMA interrupt 0040271 D7–5
enable register (B) D4
D3
D2
D1
D0
DMA interrupt 0040281 D7–5
factor flag (B) D4
register D3
D2
D1
D0
Port input 0–3, 0040290 D7
high-speed (B) D6
DMA Ch. 0/1, D5
16-bit timer 0 D4
IDMA request D3
register D2
D1
D0
Port input 0–3, 0040294 D7
high-speed (B) D6
DMA Ch. 0/1, D5
16-bit timer 0 D4
IDMA enable D3
register D2
D1
D0
S1C33210 FUNCTION PART
Table 2.5 Control Bits of HSDMA
Name Function
– reserved
PHSD1L2 High-speed DMA Ch.1
PHSD1L1 interrupt level
PHSD1L0
– reserved
PHSD0L2 High-speed DMA Ch.0
PHSD0L1 interrupt level
PHSD0L0
– reserved
PHSD3L2 High-speed DMA Ch.3
PHSD3L1 interrupt level
PHSD3L0
– reserved
PHSD2L2 High-speed DMA Ch.2
PHSD2L1 interrupt level
PHSD2L0
– reserved
EIDMA IDMA
EHDM3 High-speed DMA Ch.3
EHDM2 High-speed DMA Ch.2
EHDM1 High-speed DMA Ch.1
EHDM0 High-speed DMA Ch.0
– reserved
FIDMA IDMA
FHDM3 High-speed DMA Ch.3
FHDM2 High-speed DMA Ch.2
FHDM1 High-speed DMA Ch.1
FHDM0 High-speed DMA Ch.0
R16TC0 16-bit timer 0 comparison A
R16TU0 16-bit timer 0 comparison B
RHDM1 High-speed DMA Ch.1
RHDM0 High-speed DMA Ch.0
RP3 Port input 3
RP2 Port input 2
RP1 Port input 1
RP0 Port input 0
DE16TC0 16-bit timer 0 comparison A
DE16TU0 16-bit timer 0 comparison B
DEHDM1 High-speed DMA Ch.1
DEHDM0 High-speed DMA Ch.0
DEP3 Port input 3
DEP2 Port input 2
DEP1 Port input 1
DEP0 Port input 0
V DMA BLOCK: HSDMA (High-Speed DMA)
Setting
–
0 to 7
–
0 to 7
–
0 to 7
–
0 to 7
–
1 Enabled 0 Disabled
–
1 Factor is 0 No factor is
generated generated
1 IDMA 0 Interrupt
request request
1 IDMA 0 IDMA
enabled disabled
EPSON
Init. R/W Remarks
– – 0 when being read.
X R/W
X
X
– – 0 when being read.
X R/W
X
X
– – 0 when being read.
X R/W
X
X
– – 0 when being read.
X R/W
X
X
– – 0 when being read.
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
– – 0 when being read.
X R/W
X R/W
X R/W
X R/W
X R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
B-V-2-17