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Register name
Address
Bit
High-speed
0048230
DF
DMA Ch.1
(HW)
DE
transfer
DD
counter
DC
register
DB
DA
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
High-speed
0048232
DF
DMA Ch.1
(HW)
DE
control register
DD–8
Note:
D7
D) Dual address
D6
mode
D5
S) Single
D4
address
D3
mode
D2
D1
D0
High-speed
0048234
DF
DMA Ch.1
(HW)
DE
low-order
DD
source address
DC
set-up register
DB
DA
Note:
D9
D) Dual address
A8
mode
D7
S) Single
D6
address
D5
mode
D4
D3
D2
D1
D0
High-speed
0048236
DF
DMA Ch.1
(HW)
DE
high-order
DD
source address
DC
set-up register
Note:
D) Dual address
DB
mode
DA
S) Single
D9
address
A8
mode
D7
D6
D5
D4
D3
D2
D1
D0
S1C33210 FUNCTION PART
Name
Function
TC1_L7
Ch.1 transfer counter[7:0]
TC1_L6
(block transfer mode)
TC1_L5
TC1_L4
Ch.1 transfer counter[15:8]
TC1_L3
(single/successive transfer mode)
TC1_L2
TC1_L1
TC1_L0
BLKLEN17
Ch.1 block length
BLKLEN16
(block transfer mode)
BLKLEN15
BLKLEN14
Ch.1 transfer counter[7:0]
BLKLEN13
(single/successive transfer mode)
BLKLEN12
BLKLEN11
BLKLEN10
DUALM1
Ch.1 address mode selection
D1DIR
D) Invalid
S) Ch.1 transfer direction control
–
reserved
TC1_H7
Ch.1 transfer counter[15:8]
TC1_H6
(block transfer mode)
TC1_H5
TC1_H4
Ch.1 transfer counter[23:16]
TC1_H3
(single/successive transfer mode)
TC1_H2
TC1_H1
TC1_H0
S1ADRL15
D) Ch.1 source address[15:0]
S1ADRL14
S) Ch.1 memory address[15:0]
S1ADRL13
S1ADRL12
S1ADRL11
S1ADRL10
S1ADRL9
S1ADRL8
S1ADRL7
S1ADRL6
S1ADRL5
S1ADRL4
S1ADRL3
S1ADRL2
S1ADRL1
S1ADRL0
–
reserved
DATSIZE1
Ch.1 transfer data size
S1IN1
D) Ch.1 source address control
S1IN0
S) Ch.1 memory address control
S1ADRH11
D) Ch.1 source address[27:16]
S1ADRH10
S) Ch.1 memory address[27:16]
S1ADRH9
S1ADRH8
S1ADRH7
S1ADRH6
S1ADRH5
S1ADRH4
S1ADRH3
S1ADRH2
S1ADRH1
S1ADRH0
Setting
1 Dual addr
0 Single addr
–
1 Memory WR 0 Memory RD
–
–
1 Half word
0 Byte
S1IN[1:0]
Inc/dec
1
1
Inc.(no init)
1
0
Inc.(init)
0
1
Dec.(no init)
0
0
EPSON
APPENDIX: I/O MAP
Init. R/W
Remarks
X
R/W
X
X
X
X
X
X
X
X
R/W
X
X
X
X
X
X
X
0
R/W
–
–
0
R/W
–
–
Undefined in read.
X
R/W
X
X
X
X
X
X
X
X
R/W
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
–
–
0
R/W
0
R/W
0
Fixed
X
R/W
X
X
X
X
X
X
X
X
X
X
X
B-APPENDIX-37
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