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5.6 Target Interrupt and Break
When an interrupt in the target program and a break are simultaneously occurred, the target interrupt is prioritized.
The break occurs after completing the stack operation of the interrupt. The program counter at the break shows the
top address of the interrupt handler routine. When the target program is restarted, it executes from the top address
of the interrupt handler routine.
If an interrupt and a break are simultaneously occurred when "I" (interrupt flag) = "1" is set as a break condition by
BR command, a break occurs when the "I" flag goes "1." However, the flags after the break occurred are displayed
as "EICZ: 0000" (the "I" flag is reset) because of the prioritized interrupt process.
5.7 Trace Function
During running in emulation mode, information of the S1C63000 CPU (program counter, instruction code, data
RAM address, data content and CPU register values) is stored into the trace memory at every CPU bus cycle. The
trace memory has a capacity of 8,192 cycles, which can store the latest instructions up to 4,096 in 2 bus-cycle in-
struction and 2,048 in 4 bus-cycle instruction.
Trace memory
Effective trace
Execution of
a program
Free space
Figure 5.7.1 shows the trace function. When the trace memory becomes full, old information is erased and new
information is overwritten. TP, which is called trace pointer, shows that the point of 0 means the earliest instruction
and the break point means the latest information. The maximum value of the TP is 8,191.
Trace information
TP = 0
TP = 8,191
S5U1C63000H6 ManUal
(S1C63 Family In-Circuit Emulator)
5 OPERaTIOnS anD FUnCTIOnS OF THE S5U1C63000H6
Earliest instruction
(TP = 0)
Instruction just before
break (TP = 700)
Figure 5.7.1 Trace Function
Earliest
instruction
Trace information at any point can be displayed
by the TD command.
Latest
instruction
Figure 5.7.2 Trace Pointer
EPSOn
Trace memory
Effective trace
(TP = 8,191)
Instruction just before break
Earliest instruction
(TP = 0)
Effective trace
11
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