Epson S1C33210 Technical Manual page 112

Cmos 32-bit single chip microcomputer
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APPENDIX A <REFERENCE> EXTERNAL DEVICE INTERFACE TIMINGS
DRAM: 60ns, CPU: 25MHz, random read/write cycle
BCLK
A[11:0]
#RAS
#CAS
#RD
D[15:0](RD)
#WE
D[15:0](WR)
DRAM: 60ns, CPU: 25MHz, page-mode read/write cycle
BCLK
A[11:0]
#RAS
#CAS
#RD
D[15:0](RD)
#WE
D[15:0](WR)
DRAM: 60ns, CPU: 25MHz, CAS-before-RAS refresh cycle
BCLK
#RAS
#CAS
A-98
RAS cycle
1
ROW #1
WR data
RAS cycle
CAS cycle
1
2
ROW #1
COL #1
WR data
RPC delay
Fixed
Refresh RAS pulse width
1
1
t
t
RPC
CSR
CAS cycle
RAS precharge
2
COL #1
t
RAS
RD data
CAS cycle
2
COL #2
t
RAS
RD data
WR data
RAS precharge
2
t
RAS
t
CHR
EPSON
2
ROW #2
RAS precharge
2
RD data
2
S1C33210 PRODUCT PART

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