Epson S1C33210 Technical Manual page 389

CTS (CTS input pin)
The function of this input pin depends on the communications mode.
UART communications interprets this input as the CTS signal from the mobile device. A bit in the
communications block modem status register (0x020002A) tracks the input level. Note that there is no
hardware flow control.
HDLC communications feeds this bit clock signal to the packet processor block. A bit in the communications
block modem status register (0x020002A) tracks the input level.
PDC communications feeds this PDC bit clock signal to the PDC processor block. A bit in the communications
block modem status register (0x020002A) tracks the input level.
PHS communications feeds this PHS bit clock signal to the PIAFS processor block. A bit in the communications
block modem status register (0x020002A) tracks the input level.
DSR (DSR input pin)
The function of this input pin is independent of the communications mode. A bit in the communications block
modem status register (0x020002A) tracks the input level. This level is also available by reading the MIPORT1
bit in the communications block input port data register (D1/0x020000C).
RI (RI input pin)
The function of this input pin is independent of the communications mode. A bit in the communications block
modem status register (0x020002A) tracks the input level. This level is also available by reading the MIPORT0
bit in the communications block input port data register (D0/0x020000C). The GOUTE bit in the same register
(D7/0x020000C) enables the connection of this input to the GOUT output pin.
RTS (RTS output pin)
The function of this output pin depends on the communications mode.
UART communications drives this output pin using the RTS bit in the communications block modem control
register (D0/0x020002E).
In HDLC, PDC, and PHS communications modes, the MOPORT3 bit in the communications block output port
data register (D3/0x020000A) drives this output pin using negative logic.
DTR (DTR output pin)
The function of this output pin depends on the communications mode.
UART communications drives this output pin using the DTR bit in the communications block modem control
register (D1/0x020002E).
In HDLC, PDC, and PHS communications modes, the MOPORT2 bit in the communications block output port
data register (D2/0x020000A) drives this output pin using negative logic.
CNT2 (Mobile access control output #2 pin)
The function of this output pin is independent of the communications mode. The output level tracks, using
negative logic, the CNT2 bit in the communications block output port data register (D1/0x020000A).
CNT1 (Mobile access control output #1 pin)
The function of this output pin is independent of the communications mode. The output level tracks, using
negative logic, the CNT1 bit in the communications block output port data register (D0/0x020000A).
GOUT (GOUT output pin)
If the GOUTE bit in the communications block input port data register (D7/0x020000C) is "1," this output pin
tracks the RI input pin. Otherwise, the output is fixed at High level.
S1C33210 FUNCTION PART
III PERIPHERAL BLOCK: MONITORED MOBILE ACCESS INTERFACES
EPSON
B-III-10-3