Epson S1C33210 Technical Manual page 93

Cmos 32-bit single chip microcomputer
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SRAM read cycle (basic cycle: 1 cycle)
BCLK
A[23:0]
#CEx
#RD
D[15:0]
#WAIT
t
*1
is measured with respect to the first signal change (negation) from among the #RD, #CEx and A[23:0]
RDH
signals.
SRAM read cycle (when a wait cycle is inserted)
BCLK
t
AD
A[23:0]
t
CE1
#CEx
#RD
D[15:0]
t
WTS
#WAIT
t
*1
is measured with respect to the first signal change (negation) from among the #RD, #CEx and A[23:0]
RDH
signals.
S1C33210 PRODUCT PART
t
C3
t
AD
t
CE1
t
CEAC1
t
ACC1
t
WTS
C1
Cw
t
(C1 only)
RDD1
t
t
WTH
WTS
8 ELECTRICAL CHARACTERISTICS
t
RDD1
t
RDW
t
RDAC1
t
RDS
t
WTH
Cn
(wait cycle)
t
RDW
t
CEAC1
t
ACC1
t
RDAC1
t
t
WTH
WTS
EPSON
t
AD
t
CE2
t
RDD2
1
t
RDH
(last cycle)
t
AD
t
CE2
t
RDD2
t
WTH
t
t
RDS
RDH
1
A-79

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