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Register name
Address
Bit
Areas 6–4
004812A
DF–E
set-up register
(HW)
DD
DC
DB
DA
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Bus control
004812E
DF
register
(HW)
DE
DD
DC
DB
DA
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
S1C33210 FUNCTION PART
Name
Function
–
reserved
A6DF1
Area 6
A6DF0
output disable delay time
–
reserved
A6WT2
Area 6 wait control
A6WT1
A6WT0
–
reserved
A5SZ
Areas 5–4 device size selection
A5DF1
Areas 5–4
A5DF0
output disable delay time
–
reserved
A5WT2
Areas 5–4 wait control
A5WT1
A5WT0
RBCLK
BCLK output control
–
reserved
RBST8
Burst ROM burst mode selection
REDO
DRAM page mode selection
RCA1
Column address size selection
RCA0
RPC2
Refresh enable
RPC1
Refresh method selection
RPC0
Refresh RPC delay setup
RRA1
Refresh RAS pulse width
RRA0
selection
–
reserved
SBUSST
External interface method selection
SEMAS
External bus master setup
SEPD
External power-down control
SWAITE
#WAIT enable
II CORE BLOCK: BCU (Bus Control Unit)
Setting
–
A6DF[1:0] Number of cycles
1
1
1
0
0
1
0
0
–
A6WT[2:0]
Wait cycles
1
1
1
1
1
0
1
0
1
1
0
0
0
1
1
0
1
0
0
0
1
0
0
0
–
1 8 bits
0 16 bits
A5DF[1:0] Number of cycles
1
1
1
0
0
1
0
0
A5WT[2:0]
Wait cycles
1
1
1
1
1
0
1
0
1
1
0
0
0
1
1
0
1
0
0
0
1
0
0
0
1 Fixed at H
0 Enabled
–
1 8-successive 0 4-successive
1 EDO
0 Fast page
RCA[1:0]
1
1
1
0
0
1
0
0
1 Enabled
0 Disabled
1 Self-refresh 0 CBR-refresh
1 2.0
0 1.0
RRA[1:0]
Number of cycles
1
1
1
0
0
1
0
0
–
1 #BSL
0 A0
1 Existing
0 Nonexistent
1 Enabled
0 Disabled
1 Enabled
0 Disabled
EPSON
Init. R/W
Remarks
–
–
0 when being read.
1
R/W
3.5
1
2.5
1.5
0.5
–
–
0 when being read.
1
R/W
7
1
6
1
5
4
3
2
1
0
–
–
0 when being read.
0
R/W
1
R/W
3.5
1
2.5
1.5
0.5
–
–
0 when being read.
1
R/W
7
1
6
1
5
4
3
2
1
0
0
R/W
0
–
Writing 1 not allowed.
0
R/W
0
R/W
Size
0
R/W
11
0
10
9
8
0
R/W
0
R/W
0
R/W
0
R/W
5
0
4
3
2
0
–
Writing 1 not allowed.
0
R/W
0
R/W
0
R/W
0
R/W
B-II-4-35
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