Epson S1C33210 Technical Manual page 378

III PERIPHERAL BLOCK: INPUT/OUTPUT PORTS
If the IDMA request and enable bits are set to "1", IDMA is invoked through generation of an interrupt factor.
No interrupt request is generated at that point. An interrupt request is generated after the DMA transfer is
completed. The registers can also be set so as not to generate an interrupt, with only DMA transfers performed.
For details on IDMA transfers and interrupt control upon completion of IDMA transfer, refer to "IDMA
(Intelligent DMA)".
Trap vectors
The trap-vector address of each input default interrupt factor is set as follows:
FPT0 input interrupt:
FPT1 input interrupt:
FPT2 input interrupt:
FPT3 input interrupt:
FPK0 input interrupt:
FPK1 input interrupt:
FPT4 input interrupt:
FPT5 input interrupt:
FPT6 input interrupt:
FPT7 input interrupt:
The base address of the trap table can be changed using the TTBR register (0x48134 to 0x48137).
B-III-9-16
Table 9.9 Control Bits for IDMA Transfer
System IDMA request bit
FPT7 RP7(D7/0x40293)
FPT6 RP6(D6/0x40293)
FPT5 RP5(D5/0x40293)
FPT4 RP4(D4/0x40293)
FPT3 RP3(D3/0x40290)
FPT2 RP2(D2/0x40290)
FPT1 RP1(D1/0x40290)
FPT0 RP0(D0/0x40290)
0x0C00040
0x0C00044
0x0C00048
0x0C0004C
0x0C00050
0x0C00054
0x0C00110
0x0C00114
0x0C00118
0x0C0011C
EPSON
IDMA enable bit
DEP7(D7/0x40297)
DEP6(D6/0x40297)
DEP5(D5/0x40297)
DEP4(D4/0x40297)
DEP3(D3/0x40294)
DEP2(D2/0x40294)
DEP1(D1/0x40294)
DEP0(D0/0x40294)
S1C33210 FUNCTION PART