Epson S1C33210 Technical Manual page 341

The interrupt priority register sets the interrupt priority level of each interrupt source in a range between 0 and
7. An interrupt request to the CPU is accepted only when no other interrupt request of a higher priority has
been generated.
In addition, only when the PSR's IE bit = "1" (interrupts enabled) and the set value of the IL is smaller than the
input interrupt level set by the interrupt priority register, will the input interrupt request actually be accepted by
the CPU.
For details on these interrupt control registers, as well as the device operation when an interrupt has occurred,
refer to "ITC (Interrupt Controller)".
• Ch.2 and Ch.3
Ch.2 and Ch.3 do not have dedicated interrupt signals. Either a port input interrupt or 16-bit timer interrupt is
selected, and interrupt handling is performed accordingly.
The correspondence between port input interrupt factors and 16-bit timer interrupt factors is shown in
Table.8.10.
Serial I/F Ch.2, Ch.3/
T8-Ch.4, Ch.5 interrupt factor
T8 Ch.5 UF
T8 Ch.4 UF
SIO Ch.3 TXD Emp.
SIO Ch.3 RXD Full
SIO Ch.3 RXD Err.
SIO Ch.2 TXD Emp.
SIO Ch.2 RXD Full
SIO Ch.2 RXD Err.
Switching between the above interrupt factors is performed by means of the interrupt factor FP function
switching register (0x402C5) and the interrupt factor TM16 function switching register (0x402CB).
For the setting of the interrupt controller in the CPU-core, the setting for the selected interrupt factor is used.
Refer to the "ITC (Interrupt Controller)" section in the Core Block Manual for details of interrupts, and the
"Input/Output Ports" and "16-Bit Timers" sections in the Peripheral Circuit Block Manual for details of port
input interrupt factor and 16-bit timer interrupt factor settings.
Intelligent DMA
• Ch.0 and Ch.1
The receive-buffer full interrupt and transmit-buffer empty interrupt factors can be used to invoke intelligent
DMA (IDMA). This enables successive transmit/receive operations between memory and the
transmit/receive-buffer to be performed by means of a DAM transfer.
The following shows the IDMA channel numbers set for each interrupt factor:
Ch.0 receive-buffer full interrupt:
Ch.0 transmit-buffer empty interrupt: 0x18
Ch.1 receive-buffer full interrupt:
Ch.1 transmit-buffer empty interrupt: 0x1A
The IDMA request and enable bits shown in Table 8.11 must be set to "1" for IDMA to be invoked. Transfer
conditions, etc. on the IDMA side must also be set in advance.
Channel
Ch.0
Ch.1
S1C33210 FUNCTION PART
Table 8.10 Correspondence between Interrupt Factors
IDMA Ch.
0x17
0x19
Table 8.11 Control Bits for IDMA Transfer
Interrupt factor
Receive-buffer full RSRX0(D6/0x40292)
Transmit-buffer empty RSTX0(D7/0x40292)
Receive-buffer full RSRX1(D0/0x40293)
Transmit-buffer empty RSTX1(D1/0x40293)
III PERIPHERAL BLOCK: SERIAL INTERFACE
Port input interrupt 16-bit timer interrupt
factor
FPT7
FPT5
FPT6
FPT4
FPT2
FPT3
FPT1
FPT0
IDMA request bit
DESRX0(D6/0x40296)
DESTX0(D7/0x40296)
DESRX1(D0/0x40297)
DESTX1(D1/0x40297)
EPSON
factor
Timer 2 compare A
Timer 2 compare B
Timer 4 compare A
Timer 4 compare B
Timer 3 compare A
Timer 5 compare A
Timer 5 compare B
Timer 3 compare B
IDMA enable bit
B-III-8-25