Epson S1C33210 Technical Manual page 521

Cmos 32-bit single chip microcomputer
Table of Contents

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Register name
Address
Bit
Port input 0/1
0040260
D7
interrupt
(B)
D6
priority register
D5
D4
D3
D2
D1
D0
Port input 2/3
0040261
D7
interrupt
(B)
D6
priority register
D5
D4
D3
D2
D1
D0
Key input
0040262
D7
interrupt
(B)
D6
priority register
D5
D4
D3
D2
D1
D0
High-speed
0040263
D7
DMA Ch.0/1
(B)
D6
interrupt
D5
priority register
D4
D3
D2
D1
D0
High-speed
0040264
D7
DMA Ch.2/3
(B)
D6
interrupt
D5
priority register
D4
D3
D2
D1
D0
IDMA interrupt
0040265
D7–3
priority register
(B)
D2
D1
D0
16-bit timer 0/1
0040266
D7
interrupt
(B)
D6
priority register
D5
D4
D3
D2
D1
D0
16-bit timer 2/3
0040267
D7
interrupt
(B)
D6
priority register
D5
D4
D3
D2
D1
D0
16-bit timer 4/5
0040268
D7
interrupt
(B)
D6
priority register
D5
D4
D3
D2
D1
D0
S1C33210 FUNCTION PART
Name
Function
reserved
PP1L2
Port input 1 interrupt level
PP1L1
PP1L0
reserved
PP0L2
Port input 0 interrupt level
PP0L1
PP0L0
reserved
PP3L2
Port input 3 interrupt level
PP3L1
PP3L0
reserved
PP2L2
Port input 2 interrupt level
PP2L1
PP2L0
reserved
PK1L2
Key input 1 interrupt level
PK1L1
PK1L0
reserved
PK0L2
Key input 0 interrupt level
PK0L1
PK0L0
reserved
PHSD1L2
High-speed DMA Ch.1
PHSD1L1
interrupt level
PHSD1L0
reserved
PHSD0L2
High-speed DMA Ch.0
PHSD0L1
interrupt level
PHSD0L0
reserved
PHSD3L2
High-speed DMA Ch.3
PHSD3L1
interrupt level
PHSD3L0
reserved
PHSD2L2
High-speed DMA Ch.2
PHSD2L1
interrupt level
PHSD2L0
reserved
PDM2
IDMA interrupt level
PDM1
PDM0
reserved
P16T12
16-bit timer 1 interrupt level
P16T11
P16T10
reserved
P16T02
16-bit timer 0 interrupt level
P16T01
P16T00
reserved
P16T32
16-bit timer 3 interrupt level
P16T31
P16T30
reserved
P16T22
16-bit timer 2 interrupt level
P16T21
P16T20
reserved
P16T52
16-bit timer 5 interrupt level
P16T51
P16T50
reserved
P16T42
16-bit timer 4 interrupt level
P16T41
P16T40
Setting
0 to 7
0 to 7
0 to 7
0 to 7
0 to 7
0 to 7
0 to 7
0 to 7
0 to 7
0 to 7
0 to 7
0 to 7
0 to 7
0 to 7
0 to 7
0 to 7
0 to 7
EPSON
APPENDIX: I/O MAP
Init. R/W
Remarks
0 when being read.
X
R/W
X
X
0 when being read.
X
R/W
X
X
0 when being read.
X
R/W
X
X
0 when being read.
X
R/W
X
X
0 when being read.
X
R/W
X
X
0 when being read.
X
R/W
X
X
0 when being read.
X
R/W
X
X
0 when being read.
X
R/W
X
X
0 when being read.
X
R/W
X
X
0 when being read.
X
R/W
X
X
0 when being read.
X
R/W
X
X
0 when being read.
X
R/W
X
X
0 when being read.
X
R/W
X
X
0 when being read.
X
R/W
X
X
0 when being read.
X
R/W
X
X
0 when being read.
X
R/W
X
X
0 when being read.
X
R/W
X
X
B-APPENDIX-13

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