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III PERIPHERAL BLOCK: MONITORED MOBILE ACCESS INTERFACES
RXINTS[1:0]: HDLC receive interrupt setup (D[1:0]) / HDLC receive interrupt mode settings register
(0x0200312)
These bits offer a choice of three Rx INT interrupt configurations.
(1)
RXINTS = 00: Rx INT and Sp INT on first receive character
Note that this mode of operation requires a receive queue interrupt threshold setting of zero to guarantee proper
operation. There is an Rx INT interrupt when the first data byte enters the queue
•
after a reset (hardware or software) or
•
after the software writes "1" to the Rx INT on next receive character command bit in the HDLC receive
control register (D0/0x0200314).
There is an Sp INT interrupt immediately after the software reads the byte including the special condition from
the receive data register, the queue exit. The hardware locks the receive queue so that the software can read the
byte and the receive status. Release the lock with an error reset command.
(2)
RXINTS = 01: Rx INT and Sp INT on queue threshold
There is an Rx INT interrupt when the receive queue reaches the specified level.
The Sp INT interrupt timing depends on the threshold.
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If the threshold is 0, there is an Sp INT interrupt when the byte including the special condition reaches the
queue exit regardless of whether the software reads it from the receive data register. The hardware does not
lock the receive queue, so the software must read first the status bits and then the data because reading the
receive data register updates both.
•
If the threshold is not 0, there is an Sp INT interrupt when the byte including the special condition enters
the queue. In other words, the Sp INT interrupt indicates that there is a byte including a special condition
somewhere in the queue. The software determines which by reading the corresponding receive status.
(3)
RXINTS = 10: Sp INT only
Note that this mode of operation requires a receive queue interrupt threshold setting of zero to guarantee proper
operation.
There is no Rx INT interrupt.
The Sp INT interrupt timing is the same as for (1) above.
RXFR:
HDLC receive queue reset (D2) / HDLC receive control register (0x0200314)
ENTHM: HDLC enter Hunt mode (D1) / HDLC receive control register (0x0200314)
RXINXT: HDLC Rx INT on next receive character (D0) / HDLC receive control register (0x0200314)
Writing "1" to a bit issues the corresponding HDLC receive control command.
Note that there is a new command for each such write. Writes of "0" are ignored.
Writing "1" to RXFR resets the receive queue, discarding any data.
Write "1": Rx FIFO Reset
Write "0": Invalid
Writing "1" to ENTHM sets the Hunt status bit to "1" and starts the search for the next flag pattern. This command
immediately terminates the current receive operation. Note, however, that it does not reset the receive queue.
Write "1": Flag detection
Write "0": Invalid
Writing "1" to RXINXT produces an Rx INT interrupt when the next byte enters the empty receive queue or if the
receive queue already contains data. This command is only valid for the Rx INT and Sp INT on first receive
character setting in RXINTS (D[1:0]/0x0200310).
Write "1": Rx INT interrupt when the next byte enters the empty receive queue
Write "0": Invalid
B-III-10-38
EPSON
S1C33210 FUNCTION PART
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