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RXINT: PHS receive interrupt flag (D7) / PHS receive status register (0x0200206)
CRCER: PHS receive data CRC-32 error flag (D2) / PHS receive status register (0x0200206)
RXBS:
PHS receive buffer select (D1) / PHS receive status register (0x0200206)
These bits indicate the status of PHS receive operation.
The hardware updates the contents simultaneously with the PHS receive interrupt after every 640-bit PIAFS frame,
so read the register contents just after the interrupt––that is, within 20 ms for 32 kbps operation and within 10 ms for
64 kbps operation.
A "1" in RXINT indicate that a PHS receive interrupt is pending.
Read "1": PHS receive interrupt genetated
Read "0": No interrupt genetated
Writing "1" to RXINT clears the interrupt request.
Write "1": Clear the interrupt request
Write "0": Invalid
A "1" in CRCER indicates failure of the CRC-32 check.
Read "1": An error occurred
Read "0": No error occurred
RXBS indicates the buffer holding the data for the last receive operation completed.
Read "1": B buffers at 0x0200750 to 0x020079f
Read "0": A buffers at 0x0200700 to 0x020074f
ERES:
HDLC error Reset (D7) / HDLC interrupt control register (0x0200302)
RESINT: HDLC reset E/S INT(D6) / HDLC interrupt control register (0x0200302)
RRXINT: HDLC reset Rx INT(D1) / HDLC interrupt control register (0x0200302)
RTXINT: HDLC reset Tx INT(D0) / HDLC interrupt control register (0x0200302)
Writing "1" to a bit clears the corresponding HDLC interrupt request status bit. Writes of "0" are ignored.
Writing "1" to ERES clears the Sp INT interrupt request flag. Note that it does not clear the CRC error flag.
Write "1": Clear the interrupt request
Write "0": Invalid
Writing "1" to RESINT clears the E/S INT interrupt request flag. It also releases the E/S INT latch, clearing the way
for more interrupt requests.
Write "1": Clear the interrupt request
Write "0": Invalid
Writing "1" to RRXINT clears the Rx INT interrupt request flag.
Write "1": Clear the interrupt request
Write "0": Invalid
Writing "1" to RTXINT clears the Tx INT interrupt request flag.
Write "1": Clear the interrupt request
Write "0": Invalid
Use this command to terminate transmission after the last frame.
The Tx INT timing depends on whether the software supplies more transmit data before the transmission of the
second CRC byte.
1.
If not, the Tx INT is right after the transmission.
2.
Otherwise, the Tx INT is when the data level once again reaches the transmit queue threshold.
S1C33210 FUNCTION PART
III PERIPHERAL BLOCK: MONITORED MOBILE ACCESS INTERFACES
EPSON
B-III-10-31
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