Epson S1C33210 Technical Manual page 552

APPENDIX: I/O MAP
Register name Address Bit
Communications 0200028 D15–5
block CP4 (HW) D4
interrupt select D3
register D2
D1
D0
Communications 020002A D15–12
block modem (HW) D11
status register D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Communications 020002C D15–8
block modem (HW) D7
status interrupt D6
enable register D5
D4
D3
D2
D1
D0
Communications 020002E D15–2
block modem (HW) D1
control register D0
Communications 0200032 D15–1
block debugging (HW) D0
@ mode register
PDC interrupt 0200100 D15–2
register (HW) D1
D0
PDC command 0200102 D15–3
register (HW) D2
D1
D0
PDC status 0200104 D15–8
register (HW) D7
D6
D5–2
D1
D0
PHS transmit 0200200 D15–8
control register (HW) D7
D6–2
D1
D0
PHS transmit 0200202 D15–8
status register (HW) D7
D6–0
PHS receive 0200204 D15–8
control register (HW) D7
D6–1
D0
PHS receive 0200206 D15–8
status register (HW) D7
D6–3
D2
D1
D0
B-APPENDIX-44
Name Function
– –
CP4EN4 Map UINT4 interrupt requests to CP4
CP4EN3 Map UINT3 interrupt requests to CP4
CP4EN2 Map UINT2 interrupt requests to CP4
CP4EN1 Map UINT1 interrupt requests to CP4
CP4EN0 Map UINT0 interrupt requests to CP4
– –
RI RI input status
CTS CTS input status
DCD DCD input status
DSR DSR input status
SDRI RI input status 1 0
SURI RI input status 0 1
SDCTS CTS input status 1
SUCTS CTS input status 0
SDDCD DCD input status 1
SUDCD DCD input status 0
SDDSR DSR input status 1
SUDSR DSR input status 0
– –
EDRI Enable SDRI interrupts
EURI Enable SURI interrupts
EDCTS Enable SDCTS interrupts
EUCTS Enable SUCTS interrupts
EDDCD Enable SDDCD interrupts
EUDCD Enable SUDCD interrupts
EDDSR Enable SDDSR interrupts
EUDSR Enable SUDSR interrupts
– –
DTR DTR output level
RTS RTS output level
– –
STOP Debugging HOLD input control
– –
INTE Enable PDC interrupts
PDCINT PDC interrupt flag
– –
TXBS PDC transmit buffer select
TXEN Enable PDC transmit
RXEN Enable PDC receive
– –
CRCER1 PDC receive CRC-16 error
CRCER2 PDC receive CRC-CCITT error
– –
RXBB Receive buffer B status
RXBA Receive buffer A status
– –
TXINTE Enable PHS transmit interrupt
– –
TXBS PHS transmit buffer select Enable
TXEN PHS transmit
– –
TXINT PHS transmit interrupt flag
– –
– –
RXINTE Enable PHS receive interrupt
– –
RXEN Enable PHS receive
– –
RXINT PHS receive interrupt flag
– –
CRCER PHS receive CRC error flag
RXBS PHS receive buffer
– –
Setting
–
1 Enable 0 Disable
1 Enable 0 Disable
1 Enable 0 Disable
1 Enable 0 Disable
1 Enable 0 Disable
–
1 RI="L" 0 RI="H"
1 CTS="L" 0 CTS="H
1 DCD="L" 0 DCD="H"
1 DSR="L" 0 DSR="H"
1 Changed 0 No change
1 Changed 0 No change
0 1 Changed 0 No change
1 1 Changed 0 No change
0 1 Changed 0 No change
1 1 Changed 0 No change
0 1 Changed 0 No change
1 1 Changed 0 No change
–
1 Enable 0 Disable
1 Enable 0 Disable
1 Enable 0 Disable
1 Enable 0 Disable
1 Enable 0 Disable
1 Enable 0 Disable
1 Enable 0 Disable
1 Enable 0 Disable
–
1 RTS="H" 0 RTS="L"
1 DTR="H" 0 DTR="L"
–
1 HOLD input 0 No input
–
1 Enable 0 Disable
1 Request pending 0 No interrupts
–
1 Buffer B 0 Buffer A
1 Enable 0 Disable
1 Enable 0 Disable
–
1 CRC error 0 No error
1 CRC error 0 No error
–
1 Input available 0 No input
1 Input available 0 No input
–
1 Enable 0 Disable
–
1 Buffer B 0 Buffer A
1 Enable 0 Disable
–
1 Request pending 0 No interrupts
–
–
1 Enable 0 Disable
–
1 Enable 0 Disable
–
1 Request pending 0 No interrupts
–
1 CRC error 0 No error
1 Buffer B 0 Buffer A
–
EPSON
Init. R/W Remarks
– – 0 when being read.
0 R/W CP4= CP4EN4*UINT4
0 R/W +CP4EN3*UINT3
0 R/W +CP4EN2*UINT2
0 R/W +CP4EN1*UINT1
0 R/W +CP4EN0*UINT0
– – 0 when being read.
X R
X R
X R
X R
0 R/W Write "1" to clear.
0 R/W Write "1" to clear.
0 R/W Write "1" to clear.
0 R/W Write "1" to clear.
0 R/W Write "1" to clear.
0 R/W Write "1" to clear.
0 R/W Write "1" to clear.
0 R/W Write "1" to clear.
– – 0 when being read.
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
– – 0 when being read.
0 R/W Only valid for UART
0 R/W operation
– – 0 when being read.
0 R/W
– – 0 when being read.
0 R/W
X R/W Write "1" to clear
– – 0 when being read.
0 R/W
0 R/W
0 R/W
– – 0 when being read.
X R
X R
– – 0 when being read.
X R
X R
– – 0 when being read.
0 R/W
– – 0 when being read.
0 R/W
0 R/W
– – 0 when being read.
0 R/W Write "1" to clear
– – 0 when being read.
– – 0 when being read.
0 R/W
– – 0 when being read.
0 R/W
– – 0 when being read.
0 R/W Write "1" to clear
– – 0 when being read.
X R
X R
– – 0 when being read.
S1C33210 FUNCTION PART