Table of Contents
Advertisement
Register name
Address
Bit
Communications
0200000
D15–2
macro select
(HW)
D1
register
D0
Software reset
0200002
D15–3
register
(HW)
D2
D1
D0
Communications
0200004
D15-4
block clock
(HW)
D3
frequency
D2
divider register
D1
D0
Communications
020000A
D15–4
block output port
(HW)
D3
data register
D2
D1
D0
Communications
020000C
D15–8
block input port
(HW)
D7
data register
D6–2
D1
D0
Communications
0200010
D15–3
block PHS mode
(HW)
D2
settings register
D1
D0
Communications
0200020
D15–5
block CP0
(HW)
D4
interrupt select
D3
register
D2
D1
D0
Communications
0200022
D15–5
block CP1
(HW)
D4
interrupt select
D3
register
D2
D1
D0
Communications
0200024
D15–5
block CP2
(HW)
D4
interrupt select
D3
register
D2
D1
D0
Communications
0200026
D15–5
block CP3
(HW)
D4
interrupt select
D3
register
D2
D1
D0
S1C33210 PRODUCT PART
Name
Function
–
–
MCRS1
Master configuration selection
MCRS0
–
–
PHSRST
Reset PHS communications block
PDCRST
Reset PDC communications block
HDLRST
Reset HDLC communications block
–
–
CKD3
Specify clock frequency divider
CKD2
for communications block
CKD1
CKD0
–
–
MOPORT3
RTS output level
MOPORT2
DTR output level
CNT2
CNT2 output level
CNT1
CNT1 output level
–
–
GOUTE
Enable GOUT output
–
–
MIPORT1
DSR input level
MIPORT0
RI input level
–
–
BMODE
Data conversion switch
BHALF
Speed switch for data conversion
FMODE
Frame frequency division switch
–
–
CP0EN4
Assign UINT4 to CP0
CP0EN3
Assign UINT3 to CP0
CP0EN2
Assign UINT2 to CP0
CP0EN1
Assign UINT1 to CP0
CP0EN0
Assign UINT0 to CP0
–
–
CP1EN4
Assign UINT4 to CP1
CP1EN3
Assign UINT3 to CP1
CP1EN2
Assign UINT2 to CP1
CP1EN1
Assign UINT1 to CP1
CP1EN0
Assign UINT0 to CP1
–
–
CP2EN4
Assign UINT4 to CP2
CP2EN3
Assign UINT3 to CP2
CP2EN2
Assign UINT2 to CP2
CP2EN1
Assign UINT1 to CP2
CP2EN0
Assign UINT0 to CP2
–
–
CP3EN4
Assign UINT4 to CP3
CP3EN3
Assign UINT3 to CP3
CP3EN2
Assign UINT2 to CP3
CP3EN1
Assign UINT1 to CP3
CP3EN0
Assign UINT0 to CP3
Setting
–
MCRS[1:0]
Communications mode
1
1
1
0
0
1
HDLC
0
0
UART
–
1 Reset
0 Ignored
1 Reset
0 Ignored
1 Reset
0 Ignored
–
CKD[3:0]
Net frequency
1
1
1
1
1
1
1
0
1
1
0
1
1
1
0
0
1
0
1
1
1
0
1
0
1
0
0
1
1
0
0
0
0
1
1
1
1
1
0
0
0
1
0
1
1
0
0
0
0
0
1
1
0
0
1
0
0
0
0
1
0
0
0
0
–
1 RTS="L"
0 RTS="H"
1 DTR="L"
0 DTR="H"
1 CNT2="L"
0 CNT2="H"
1 CNT1="L"
0 CNT1="H"
–
1 Enable
0 Disable
–
1 DSR="H"
0 DSR="L"
1 RI="H"
0 RI="L"
–
1 Convert
0 Pass through
1 32kbps
0 64kbps
1 Frequency divider 0 Pass through
–
1 Enable
0 Disable
1 Enable
0 Disable
1 Enable
0 Disable
1 Enable
0 Disable
1 Enable
0 Disable
–
1 Enable
0 Disable
1 Enable
0 Disable
1 Enable
0 Disable
1 Enable
0 Disable
1 Enable
0 Disable
–
1 Enable
0 Disable
1 Enable
0 Disable
1 Enable
0 Disable
1 Enable
0 Disable
1 Enable
0 Disable
–
1 Enable
0 Disable
1 Enable
0 Disable
1 Enable
0 Disable
1 Enable
0 Disable
1 Enable
0 Disable
EPSON
4 PERIPHERAL CIRCUITS
Init. R/W
Remarks
–
–
0 when being read.
0
R/W
Only valid when
PHS
0
MSEL pin input is at
PDC
High level
–
–
0 when being read.
0
W
0
W
0
W
–
–
0 when being read.
1
R/W
fout = PERICLK
fout/16
1
R/W
output
fout/15
1
R/W
frequency
fout/14
1
R/W
fout/13
fout/12
fout/11
fout/10
fout/9
fout/8
fout/7
fout/6
fout/5
fout/4
fout/3
fout/2
fout/2
–
–
0 when being read.
1
R/W
Only valid for PHS, PDC,
1
R/W
and HDLC operation
1
R/W
Always valid
1
R/W
–
–
0 when being read.
0
R/W
–
–
0 when being read.
X
R
X
R
–
–
0 when being read.
0
R/W
0
R/W
0
R/W
–
–
0 when being read.
0
R/W
CP0= CP0EN4*UINT4
0
R/W
+CP0EN3*UINT3
0
R/W
+CP0EN2*UINT2
0
R/W
+CP0EN1*UINT1
0
R/W
+CP0EN0*UINT0
–
–
0 when being read.
0
R/W
CP1= CP1EN4*UINT4
0
R/W
+CP1EN3*UINT3
0
R/W
+CP1EN2*UINT2
0
R/W
+CP1EN1*UINT1
0
R/W
+CP1EN0*UINT0
–
–
0 when being read.
0
R/W
CP2= CP2EN4*UINT4
0
R/W
+CP2EN3*UINT3
0
R/W
+CP2EN2*UINT2
0
R/W
+CP2EN1*UINT1
0
R/W
+CP2EN0*UINT0
–
–
0 when being read.
0
R/W
CP3= CP3EN4*UINT4
0
R/W
+CP3EN3*UINT3
0
R/W
+CP3EN2*UINT2
0
R/W
+CP3EN1*UINT1
0
R/W
+CP3EN0*UINT0
A-57
Advertisement
Table of Contents
