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Register name
Address
Bit
High-speed
0048240
DF
DMA Ch.2
(HW)
DE
transfer
DD
counter
DC
register
DB
DA
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
High-speed
0048242
DF
DMA Ch.2
(HW)
DE
control register
DD–8
Note:
D7
D) Dual address
D6
mode
D5
S) Single
D4
address
D3
mode
D2
D1
D0
High-speed
0048244
DF
DMA Ch.2
(HW)
DE
low-order
DD
source address
DC
set-up register
DB
DA
Note:
D9
D) Dual address
A8
mode
D7
S) Single
D6
address
D5
mode
D4
D3
D2
D1
D0
High-speed
0048246
DF
DMA Ch.2
(HW)
DE
high-order
DD
source address
DC
set-up register
Note:
D) Dual address
DB
mode
DA
S) Single
D9
address
A8
mode
D7
D6
D5
D4
D3
D2
D1
D0
S1C33210 FUNCTION PART
Name
Function
TC2_L7
Ch.2 transfer counter[7:0]
TC2_L6
(block transfer mode)
TC2_L5
TC2_L4
Ch.2 transfer counter[15:8]
TC2_L3
(single/successive transfer mode)
TC2_L2
TC2_L1
TC2_L0
BLKLEN27
Ch.2 block length
BLKLEN26
(block transfer mode)
BLKLEN25
BLKLEN24
Ch.2 transfer counter[7:0]
BLKLEN23
(single/successive transfer mode)
BLKLEN22
BLKLEN21
BLKLEN20
DUALM2
Ch.2 address mode selection
D2DIR
D) Invalid
S) Ch.2 transfer direction control
–
reserved
TC2_H7
Ch.2 transfer counter[15:8]
TC2_H6
(block transfer mode)
TC2_H5
TC2_H4
Ch.2 transfer counter[23:16]
TC2_H3
(single/successive transfer mode)
TC2_H2
TC2_H1
TC2_H0
S2ADRL15
D) Ch.2 source address[15:0]
S2ADRL14
S) Ch.2 memory address[15:0]
S2ADRL13
S2ADRL12
S2ADRL11
S2ADRL10
S2ADRL9
S2ADRL8
S2ADRL7
S2ADRL6
S2ADRL5
S2ADRL4
S2ADRL3
S2ADRL2
S2ADRL1
S2ADRL0
–
reserved
DATSIZE2
Ch.2 transfer data size
S2IN1
D) Ch.2 source address control
S2IN0
S) Ch.2 memory address control
S2ADRH11
D) Ch.2 source address[27:16]
S2ADRH10
S) Ch.2 memory address[27:16]
S2ADRH9
S2ADRH8
S2ADRH7
S2ADRH6
S2ADRH5
S2ADRH4
S2ADRH3
S2ADRH2
S2ADRH1
S2ADRH0
Setting
1 Dual addr
0 Single addr
–
1 Memory WR 0 Memory RD
–
–
1 Half word
0 Byte
S2IN[1:0]
Inc/dec
1
1
Inc.(no init)
1
0
Inc.(init)
0
1
Dec.(no init)
0
0
EPSON
APPENDIX: I/O MAP
Init. R/W
Remarks
X
R/W
X
X
X
X
X
X
X
X
R/W
X
X
X
X
X
X
X
0
R/W
–
–
0
R/W
–
–
Undefined in read.
X
R/W
X
X
X
X
X
X
X
X
R/W
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
–
–
0
R/W
0
R/W
0
Fixed
X
R/W
X
X
X
X
X
X
X
X
X
X
X
B-APPENDIX-39
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