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A.4 SRAM (55ns)
SRAM interface setup examples – 55ns
Operating
frequency
Wait cycle
20MHz
25MHz
33MHz
SRAM interface timing – 55ns
SRAM interface
Parameter
<Read cycle>
Read cycle time
Address access time
#CE access time
#OE access time
Output disable delay time
<Write cycle>
Write cycle time
Address enable time
Write pulse width
Input data setup time
Input data hold time
SRAM: 55ns, CPU: 33/25MHz, read cycle
BCLK
A[23:0]
#CEx
#RD
D[15:0]
SRAM: 55ns, CPU: 33/25MHz, write cycle
S1C33L03 PRODUCT PART
APPENDIX A <REFERENCE> EXTERNAL DEVICE INTERFACE TIMINGS
Read cycle
Read cycle
1
2
2
3
2
3
Symbol
Min.
t
55
RC
t
–
ACC
t
–
ACS
t
–
OE
t
0
OHZ
t
55
WC
t
50
AW
t
45
WP
t
30
DW
t
0
DH
t
RC
t
ACC
t
ACS
t
OE
BCLK
A[23:0]
t
AW
#CEx
#WR
D[15:0]
EPSON
Output disable
Write cycle
delay cycle
2
3
3
33MHz
Max.
Cycle
Time
Cycle
–
3
90
55
3
90
55
3
90
30
2.5
75
30
1.5
45
–
3
90
–
2.5
75
–
2
60
–
2
60
–
0.5
15
t
OHZ
RD data
t
WC
t
WP
t
t
DW
DH
WR data
1.5
1.5
1.5
25MHz
20MHz
Time
Cycle
Time
3
120
2
100
3
120
2
100
3
120
2
100
2.5
100
1.5
75
1.5
60
1.5
75
3
120
2
100
2.5
100
1.5
75
2
80
1
50
2
80
1
50
0.5
20
0.5
25
A-123
A-1
A-ap
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