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Table D–23 Bit Definition of Logout Frame Registers (Continued)
Register
Identification
Bit Field
P0 & 1_ERROR
<63:56>
<55:52>
<51>
<50:16>
<15:12>
<11>
<10>
<9>
<8>
<7>
<6>
<5>
<4>
<3>
<2>
<1>
<0>
2
M refers to PCI Master; T refers to PCI Target
Text Translation Description
ECC Syndrome of CRE or UECC error - Same as EV68.
When CRE or UECC failing transaction: 0000(Bin) =
DMA Read; 0001(Bin) = DMA RMW; 0011(Bin) = S/G
Read.
PCI command of transaction when error not CRE or
UECC : 0000(Bin) = PCI IACKCycle ; 0001(Bin) = PCI
Special Cycle ; 0010(Bin) = PCI I/O Read; 0011(Bin) =
PCI I/O Write; 0100(Bin) = Reserved ; 0101(Bin) = PCI
PTP Write ; 0110(Bin) = PCI Memory Read ; 0111(Bin) =
PCI Memory Write from CPUx; 1000(Bin) = PCI CSR
Read;
If clear = valid <63:56>,<55:52>, and <50:16> error
information if any <11:0> bits are set, otherwise invalid.
If <11> or <10> =set and <51> =clear, <50:19> = System
address <34:3> of erred quadword and <18:16> =
000(Bin); else if any one of <9:0> =set and <51> = clear,
<50:48> = 000(Bin),<47:18> = starting PCI address
<31:2> of erred transaction, <17:16> = 00(Bin) if not
DAC; 01(Bin) if DAC SG Windows 3; 1x(Bin) if Monster
Window
MBZ, RAZ
Set = Correctable ECC Error (M or T
Set = Uncorrectable ECC Error (M or T)
Reserved – MBZ/RAZ
Set = No device select as PCI (M) error
Set = PCI read data parity error as PCI (M)
Set = Target abort error detected as PCI (M)
Set = Address parity error detected as potential PCI
Set = Invalid S/G page table entry detected as PCI
Set = Delayed completion retry time-out error as PCI
Set = PERR# error as PCI (M)
Set = SERR# error as PCI (M or T)
Set = Error occurred / lost after this register locked
2
)
Continued on next page
Registers
D-53
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Troubleshooting
